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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-07-19 00:29:59 +0300 |
|---|---|---|
| committer | Joe Hershberger <joe.hershberger@ni.com> | 2019-07-25 13:13:31 -0500 |
| commit | f588b4d205c209f54209e3aced62fa57c8fbe750 (patch) | |
| tree | 469f783dfa80e8143ff0d4133f4d6e290d9b1406 /include/configs/ls1021atwr.h | |
| parent | 1c8ad086748545f3c0f0fd5abfba4cea7ebfdc15 (diff) | |
| download | u-boot-f588b4d205c209f54209e3aced62fa57c8fbe750.zip u-boot-f588b4d205c209f54209e3aced62fa57c8fbe750.tar.gz u-boot-f588b4d205c209f54209e3aced62fa57c8fbe750.tar.bz2 | |
arm: ls1021atwr: Convert to use driver model TSEC driver
Now that we have added driver model support to the TSEC driver,
convert ls1021atwr board to use it.
This depends on previous DM series for ls1021atwr:
http://patchwork.ozlabs.org/patch/561855/
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[Vladimir] Made the following changes:
- Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi
- Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 -
a mistake ported over from Linux. Each SGMII PCS lies on the private
MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS).
- Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs
- Completely removed non-DM_ETH support from ls1021atwr
- Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio"
and from "fsl,tsec" to "fsl,etsec2" to match Linux
Diffstat (limited to 'include/configs/ls1021atwr.h')
| -rw-r--r-- | include/configs/ls1021atwr.h | 28 |
1 files changed, 1 insertions, 27 deletions
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index de0c9c7..cbf7a49 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -260,33 +260,7 @@ */ #ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 +#define CONFIG_ETHPRIME "ethernet@2d10000" #endif /* PCIe */ |