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| author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:17:54 +0100 |
|---|---|---|
| committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:25 +0200 |
| commit | 21c1502a4a81904706b9883f523ec4a94aba880f (patch) | |
| tree | c04e236d3366a84cdad3b19eb297f33d89d3c283 /include/configs/hrcon.h | |
| parent | ff3bb0c435e0d10ccb61a8fd2dada3ae72f1f97e (diff) | |
| download | u-boot-21c1502a4a81904706b9883f523ec4a94aba880f.zip u-boot-21c1502a4a81904706b9883f523ec4a94aba880f.tar.gz u-boot-21c1502a4a81904706b9883f523ec4a94aba880f.tar.bz2 | |
mpc83xx: Kconfig: Migrate HRCW to Kconfig
The HRCW (hardware reset configuration word) is a constant that must be
hard-coded into the boot loader image. So, it must be available at
compile time, and cannot be migrated to the DT mechanism, but has to be
kept in Kconfig.
Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/hrcon.h')
| -rw-r--r-- | include/configs/hrcon.h | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 8eb12b7..c1fe6b4 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -17,38 +17,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR /* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - -/* * System IO Config */ #define CONFIG_SYS_SICRH (\ |