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| author | Pali Rohár <pali@kernel.org> | 2021-07-31 14:22:52 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-08-11 08:42:26 +0200 |
| commit | 29795302b942e6ee41c9d95f7e6e29f57d108d42 (patch) | |
| tree | 7b13994c6545e80bcf5ed4ccba3e34620e49bd68 /include/configs/clearfog.h | |
| parent | 293a8de6fa0fdc70f6de6d7fb8d70d46e342e42c (diff) | |
| download | u-boot-29795302b942e6ee41c9d95f7e6e29f57d108d42.zip u-boot-29795302b942e6ee41c9d95f7e6e29f57d108d42.tar.gz u-boot-29795302b942e6ee41c9d95f7e6e29f57d108d42.tar.bz2 | |
arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR register
Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz.
Use this information instead of manual configuration in every board file.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/clearfog.h')
| -rw-r--r-- | include/configs/clearfog.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index fbdd2f0..7052170 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -17,7 +17,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI |