Merge branch 'next'

224 files changed, 7998 insertions, 6542 deletions

diff --git a/drivers/Kconfig b/drivers/Kconfig
index b26ca8c..8b6fead 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -40,6 +40,8 @@ source "drivers/fastboot/Kconfig"
 
 source "drivers/firmware/Kconfig"
 
+source "drivers/fuzz/Kconfig"
+
 source "drivers/fpga/Kconfig"
 
 source "drivers/gpio/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 67c8af7..d63fd1c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -115,6 +115,7 @@ obj-$(CONFIG_W1) += w1/
 obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
 
 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
+obj-$(CONFIG_FUZZ) += fuzz/
 obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
 obj-$(CONFIG_DM_RNG) += rng/
 endif
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index ce6907e..7715c40 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -113,12 +113,20 @@ config SATA_CEVA
 
 config FSL_SATA
 	bool "Enable Freescale SATA controller driver support"
+	depends on PPC
 	select AHCI
 	select LIBATA
+	imply LBA48
 	help
 	  Enable this driver to support the SATA controller found in
 	  some Freescale PowerPC SoCs.
 
+config FSL_SATA_V2
+	bool "Enable support for V2 of the Freescale SATA controller"
+	depends on FSL_SATA
+	help
+	  Enable support for V2 of this controller, rather than V1.
+
 config SATA_MV
 	bool "Enable Marvell SATA controller driver support"
 	select AHCI
diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c
index d9fd850..1a2c3c2 100644
--- a/drivers/ata/dwc_ahsata.c
+++ b/drivers/ata/dwc_ahsata.c
@@ -844,138 +844,6 @@ static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
 	return rc;
 }
 
-#if !CONFIG_IS_ENABLED(AHCI)
-static int ahci_init_one(int pdev)
-{
-	int rc;
-	struct ahci_uc_priv *uc_priv = NULL;
-
-	uc_priv = malloc(sizeof(struct ahci_uc_priv));
-	if (!uc_priv)
-		return -ENOMEM;
-
-	memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
-	uc_priv->dev = pdev;
-
-	uc_priv->host_flags = ATA_FLAG_SATA
-				| ATA_FLAG_NO_LEGACY
-				| ATA_FLAG_MMIO
-				| ATA_FLAG_PIO_DMA
-				| ATA_FLAG_NO_ATAPI;
-
-	uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
-
-	/* initialize adapter */
-	rc = ahci_host_init(uc_priv);
-	if (rc)
-		goto err_out;
-
-	ahci_print_info(uc_priv);
-
-	/* Save the uc_private struct to block device struct */
-	sata_dev_desc[pdev].priv = uc_priv;
-
-	return 0;
-
-err_out:
-	if (uc_priv)
-		free(uc_priv);
-	return rc;
-}
-
-int init_sata(int dev)
-{
-	struct ahci_uc_priv *uc_priv = NULL;
-
-#if defined(CONFIG_MX6)
-	if (!is_mx6dq() && !is_mx6dqp())
-		return 1;
-#endif
-	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
-		printf("The sata index %d is out of ranges\n\r", dev);
-		return -1;
-	}
-
-	ahci_init_one(dev);
-
-	uc_priv = sata_dev_desc[dev].priv;
-
-	return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
-}
-
-int reset_sata(int dev)
-{
-	struct ahci_uc_priv *uc_priv;
-	struct sata_host_regs *host_mmio;
-
-	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
-		printf("The sata index %d is out of ranges\n\r", dev);
-		return -1;
-	}
-
-	uc_priv = sata_dev_desc[dev].priv;
-	if (NULL == uc_priv)
-		/* not initialized, so nothing to reset */
-		return 0;
-
-	host_mmio = uc_priv->mmio_base;
-	setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
-	while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
-		udelay(100);
-
-	free(uc_priv);
-	memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc));
-
-	return 0;
-}
-
-int sata_port_status(int dev, int port)
-{
-	struct sata_port_regs *port_mmio;
-	struct ahci_uc_priv *uc_priv = NULL;
-
-	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
-		return -EINVAL;
-
-	if (sata_dev_desc[dev].priv == NULL)
-		return -ENODEV;
-
-	uc_priv = sata_dev_desc[dev].priv;
-	port_mmio = uc_priv->port[port].port_mmio;
-
-	return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
-}
-
-/*
- * SATA interface between low level driver and command layer
- */
-ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
-	struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
-
-	return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
-				buffer);
-}
-
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
-{
-	struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
-
-	return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
-				 buffer);
-}
-
-int scan_sata(int dev)
-{
-	struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
-	struct blk_desc *pdev = &sata_dev_desc[dev];
-
-	return dwc_ahsata_scan_common(uc_priv, pdev);
-}
-#endif /* CONFIG_IS_ENABLED(AHCI) */
-
-#if CONFIG_IS_ENABLED(AHCI)
-
 int dwc_ahsata_port_status(struct udevice *dev, int port)
 {
 	struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -1109,4 +977,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = {
 	.probe    = dwc_ahsata_probe,
 };
 #endif
-#endif
diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c
index d1bab93..6db4247 100644
--- a/drivers/ata/fsl_sata.c
+++ b/drivers/ata/fsl_sata.c
@@ -6,10 +6,13 @@
  */
 
 #include <common.h>
+#include <ahci.h>
 #include <blk.h>
 #include <command.h>
 #include <console.h>
 #include <cpu_func.h>
+#include <dm.h>
+#include <dm/device-internal.h>
 #include <log.h>
 #include <asm/io.h>
 #include <asm/processor.h>
@@ -21,33 +24,6 @@
 #include <linux/delay.h>
 #include "fsl_sata.h"
 
-#if CONFIG_IS_ENABLED(BLK)
-#include <dm.h>
-#include <ahci.h>
-#include <blk.h>
-#include <dm/device-internal.h>
-#else
-#ifndef CONFIG_SYS_SATA1_FLAGS
-	#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
-#endif
-#ifndef CONFIG_SYS_SATA2_FLAGS
-	#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
-#endif
-
-static struct fsl_sata_info fsl_sata_info[] = {
-#ifdef CONFIG_SATA1
-	{CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
-#else
-	{0, 0},
-#endif
-#ifdef CONFIG_SATA2
-	{CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
-#else
-	{0, 0},
-#endif
-};
-#endif
-
 static inline void sdelay(unsigned long sec)
 {
 	unsigned long i;
@@ -86,11 +62,7 @@ static int ata_wait_register(unsigned __iomem *addr, u32 mask,
 	return (i < timeout_msec) ? 0 : -1;
 }
 
-#if !CONFIG_IS_ENABLED(BLK)
-int init_sata(int dev)
-#else
 static int init_sata(struct fsl_ata_priv *priv, int dev)
-#endif
 {
 	u32 length, align;
 	cmd_hdr_tbl_t *cmd_hdr;
@@ -129,15 +101,9 @@ static int init_sata(struct fsl_ata_priv *priv, int dev)
 	snprintf(sata->name, 12, "SATA%d:", dev);
 
 	/* Set the controller register base address to device struct */
-#if !CONFIG_IS_ENABLED(BLK)
-	sata_dev_desc[dev].priv = (void *)sata;
-	reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
-	sata->dma_flag = fsl_sata_info[dev].flags;
-#else
 	reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev);
 	sata->dma_flag = priv->flag;
 	priv->fsl_sata = sata;
-#endif
 	sata->reg_base = reg;
 
 	/* Allocate the command header table, 4 bytes aligned */
@@ -738,17 +704,11 @@ static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
 /*
  * SATA interface between low level driver and command layer
  */
-#if !CONFIG_IS_ENABLED(BLK)
-ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
-{
-	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
-#else
 static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		       void *buffer)
 {
 	struct fsl_ata_priv *priv = dev_get_plat(dev);
 	fsl_sata_t *sata = priv->fsl_sata;
-#endif
 	u32 rc;
 
 	if (sata->lba48)
@@ -760,17 +720,11 @@ static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 	return rc;
 }
 
-#if !CONFIG_IS_ENABLED(BLK)
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
-{
-	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
-#else
 static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 			const void *buffer)
 {
 	struct fsl_ata_priv *priv = dev_get_plat(dev);
 	fsl_sata_t *sata = priv->fsl_sata;
-#endif
 	u32 rc;
 
 	if (sata->lba48) {
@@ -801,17 +755,11 @@ static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
 	ata_swap_buf_le16(id, ATA_ID_WORDS);
 }
 
-#if !CONFIG_IS_ENABLED(BLK)
-int scan_sata(int dev)
-{
-	fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
-#else
 static int scan_sata(struct udevice *dev)
 {
 	struct blk_desc *desc = dev_get_uclass_plat(dev);
 	struct fsl_ata_priv *priv = dev_get_plat(dev);
 	fsl_sata_t *sata = priv->fsl_sata;
-#endif
 
 	unsigned char serial[ATA_ID_SERNO_LEN + 1];
 	unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
@@ -853,15 +801,6 @@ static int scan_sata(struct udevice *dev)
 		debug("Device supports LBA28\n\r");
 #endif
 
-#if !CONFIG_IS_ENABLED(BLK)
-	memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
-	memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
-	memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
-	sata_dev_desc[dev].lba = (u32)n_sectors;
-#ifdef CONFIG_LBA48
-	sata_dev_desc[dev].lba48 = sata->lba48;
-#endif
-#else
 	memcpy(desc->product, serial, sizeof(serial));
 	memcpy(desc->revision, firmware, sizeof(firmware));
 	memcpy(desc->vendor, product, sizeof(product));
@@ -869,7 +808,6 @@ static int scan_sata(struct udevice *dev)
 #ifdef CONFIG_LBA48
 	desc->lba48 = sata->lba48;
 #endif
-#endif
 
 	/* Get the NCQ queue depth from device */
 	sata->queue_depth = ata_id_queue_depth(id);
@@ -890,7 +828,6 @@ static int scan_sata(struct udevice *dev)
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(BLK)
 static const struct blk_ops sata_fsl_blk_ops = {
 	.read	= sata_read,
 	.write	= sata_write,
@@ -1042,4 +979,3 @@ U_BOOT_DRIVER(fsl_ahci) = {
 	.remove = fsl_ata_remove,
 	.priv_auto	= sizeof(struct fsl_ata_priv),
 };
-#endif
diff --git a/drivers/ata/fsl_sata.h b/drivers/ata/fsl_sata.h
index 5b9daa7..e1ea8eb3 100644
--- a/drivers/ata/fsl_sata.h
+++ b/drivers/ata/fsl_sata.h
@@ -319,7 +319,6 @@ typedef struct fsl_sata {
 #define READ_CMD	0
 #define WRITE_CMD	1
 
-#if CONFIG_IS_ENABLED(BLK)
 struct fsl_ata_priv {
 	u32 base;
 	u32 flag;
@@ -327,6 +326,5 @@ struct fsl_ata_priv {
 	u32 offset;
 	fsl_sata_t *fsl_sata;
 };
-#endif
 
 #endif /* __FSL_SATA_H__ */
diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h
index bea4322..9ad09e5 100644
--- a/drivers/ata/sata_sil.h
+++ b/drivers/ata/sata_sil.h
@@ -212,12 +212,10 @@ enum {
 	CMD_ERR		= 0x21,
 };
 
-#if CONFIG_IS_ENABLED(BLK)
 #define ATA_MAX_PORTS		32
 struct sil_sata_priv {
 	int		port_num;
 	struct sil_sata	*sil_sata_desc[ATA_MAX_PORTS];
 };
-#endif
 
 #endif
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index d6d1c6e..b5b4820 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -218,3 +218,19 @@ config IDE_RESET
 	  must be defined in a board-specific file.
 
 endif  # IDE
+
+config LBA48
+	bool "Enable LBA support for disks larger than 137GB"
+	depends on HAVE_BLOCK_DEVICE
+	help
+	  Set this to enable support for disks larger than 137GB.
+	  Also look at CONFIG_SYS_64BIT_LBA.  Without both of these, LBA48
+	  support uses 32bit variables and will 'only' support disks up to
+	  2.1TB.
+
+config SYS_64BIT_LBA
+	bool "Enable 64bit number of blocks on a block device"
+	depends on HAVE_BLOCK_DEVICE
+	help
+	  Make the block subsystem use 64bit sector addresses, rather than the
+	  default of 32bit.
diff --git a/drivers/block/ide.c b/drivers/block/ide.c
index e8518ff..3270a9f 100644
--- a/drivers/block/ide.c
+++ b/drivers/block/ide.c
@@ -695,15 +695,6 @@ void ide_init(void)
 	unsigned char c;
 	int i, bus;
 
-#ifdef CONFIG_IDE_PREINIT
-	WATCHDOG_RESET();
-
-	if (ide_preinit()) {
-		puts("ide_preinit failed\n");
-		return;
-	}
-#endif /* CONFIG_IDE_PREINIT */
-
 	WATCHDOG_RESET();
 
 	/* ATAPI Drives seems to need a proper IDE Reset */
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 66ce4cc..e918f74 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -237,4 +237,15 @@ config SYS_BOOTCOUNT_MAGIC
 	help
 	  Set the magic value used for the boot counter.
 
+choice
+	prompt "Endianness of bootcount accessors"
+	default SYS_BOOTCOUNT_LE
+
+config SYS_BOOTCOUNT_LE
+	bool "Little endian accessors"
+
+config SYS_BOOTCOUNT_BE
+	bool "Big endian accessors"
+
+endchoice
 endif
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a62b81a..fd9e1a8 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -166,22 +166,6 @@ config CLK_SCMI
 	  by a SCMI agent based on SCMI clock protocol communication
 	  with a SCMI server.
 
-config CLK_STM32F
-	bool "Enable clock driver support for STM32F family"
-	depends on CLK && (STM32F7 || STM32F4)
-	default y
-	help
-	  This clock driver adds support for RCC clock management
-	  for STM32F4 and STM32F7 SoCs.
-
-config CLK_STM32MP1
-	bool "Enable RCC clock driver for STM32MP1"
-	depends on ARCH_STM32MP && CLK
-	default y
-	help
-	  Enable the STM32 clock (RCC) driver. Enable support for
-	  manipulating STM32MP1's on-SoC clocks.
-
 config CLK_HSDK
 	bool "Enable cgu clock driver for HSDK boards"
 	depends on CLK && TARGET_HSDK
@@ -251,6 +235,7 @@ source "drivers/clk/owl/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/sunxi/Kconfig"
 source "drivers/clk/sifive/Kconfig"
+source "drivers/clk/stm32/Kconfig"
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/ti/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f5b5531..c274cda 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -23,6 +23,8 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
 obj-$(CONFIG_ARCH_NPCM) += nuvoton/
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_ARCH_SOCFPGA) += altera/
+obj-$(CONFIG_ARCH_STM32) += stm32/
+obj-$(CONFIG_ARCH_STM32MP) += stm32/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_CLK_AT91) += at91/
 obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
@@ -39,8 +41,6 @@ obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
 obj-$(CONFIG_CLK_SCMI) += clk_scmi.o
 obj-$(CONFIG_CLK_SIFIVE) += sifive/
-obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
-obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o
 obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
@@ -53,4 +53,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-obj-$(CONFIG_STM32H7) += clk_stm32h7.o
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index a1b4496..623c691 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -12,6 +12,7 @@
 #include <asm/arch/scu_ast2500.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/aspeed-clock.h>
+#include <dt-bindings/reset/ast2500-reset.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 
@@ -173,6 +174,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
 		rate = ast2500_get_uart_clk_rate(priv->scu, 5);
 		break;
 	default:
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
@@ -425,6 +427,25 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
 	return new_rate;
 }
 
+#define SCU_CLKSTOP_SDIO 27
+static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
+{
+	u32 reset_bit;
+	u32 clkstop_bit;
+
+	reset_bit = BIT(ASPEED_RESET_SDIO);
+	clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
+
+	setbits_le32(&scu->sysreset_ctrl1, reset_bit);
+	udelay(100);
+	//enable clk
+	clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
+	mdelay(10);
+	clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
+
+	return 0;
+}
+
 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 {
 	struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
@@ -438,6 +459,7 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
 		new_rate = ast2500_configure_d2pll(priv->scu, rate);
 		break;
 	default:
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
@@ -479,7 +501,11 @@ static int ast2500_clk_enable(struct clk *clk)
 	case ASPEED_CLK_D2PLL:
 		ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
 		break;
+	case ASPEED_CLK_GATE_SDCLK:
+		ast2500_enable_sdclk(priv->scu);
+		break;
 	default:
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index f191b0f..0df1dc3 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -471,7 +471,7 @@ static ulong ast2600_clk_get_rate(struct clk *clk)
 		rate = ast2600_get_uart_huxclk_rate(priv->scu);
 		break;
 	default:
-		debug("can't get clk rate\n");
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
@@ -1073,13 +1073,13 @@ static int ast2600_clk_enable(struct clk *clk)
 	case ASPEED_CLK_GATE_SDCLK:
 		ast2600_enable_sdclk(priv->scu);
 		break;
-	case ASPEED_CLK_GATE_SDEXTCLK:
+	case ASPEED_CLK_SDIO:
 		ast2600_enable_extsdclk(priv->scu);
 		break;
 	case ASPEED_CLK_GATE_EMMCCLK:
 		ast2600_enable_emmcclk(priv->scu);
 		break;
-	case ASPEED_CLK_GATE_EMMCEXTCLK:
+	case ASPEED_CLK_EMMC:
 		ast2600_enable_extemmcclk(priv->scu);
 		break;
 	case ASPEED_CLK_GATE_FSICLK:
@@ -1098,7 +1098,7 @@ static int ast2600_clk_enable(struct clk *clk)
 		ast2600_enable_rsaclk(priv->scu);
 		break;
 	default:
-		pr_err("can't enable clk\n");
+		debug("%s: unknown clk %ld\n", __func__, clk->id);
 		return -ENOENT;
 	}
 
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index 5aaabcf..d172fed 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2019-2020 Linaro Limited
+ * Copyright (C) 2019-2022 Linaro Limited
  */
 
 #define LOG_CATEGORY UCLASS_CLK
@@ -13,8 +13,17 @@
 #include <asm/types.h>
 #include <linux/clk-provider.h>
 
+/**
+ * struct scmi_clk_priv - Private data for SCMI clocks
+ * @channel: Reference to the SCMI channel to use
+ */
+struct scmi_clk_priv {
+	struct scmi_channel *channel;
+};
+
 static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
 {
+	struct scmi_clk_priv *priv = dev_get_priv(dev);
 	struct scmi_clk_protocol_attr_out out;
 	struct scmi_msg msg = {
 		.protocol_id = SCMI_PROTOCOL_ID_CLOCK,
@@ -24,7 +33,7 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
 	};
 	int ret;
 
-	ret = devm_scmi_process_msg(dev, &msg);
+	ret = devm_scmi_process_msg(dev, priv->channel, &msg);
 	if (ret)
 		return ret;
 
@@ -35,6 +44,7 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
 
 static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
 {
+	struct scmi_clk_priv *priv = dev_get_priv(dev);
 	struct scmi_clk_attribute_in in = {
 		.clock_id = clkid,
 	};
@@ -49,7 +59,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
 	};
 	int ret;
 
-	ret = devm_scmi_process_msg(dev, &msg);
+	ret = devm_scmi_process_msg(dev, priv->channel, &msg);
 	if (ret)
 		return ret;
 
@@ -60,6 +70,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
 
 static int scmi_clk_gate(struct clk *clk, int enable)
 {
+	struct scmi_clk_priv *priv = dev_get_priv(clk->dev);
 	struct scmi_clk_state_in in = {
 		.clock_id = clk->id,
 		.attributes = enable,
@@ -70,7 +81,7 @@ static int scmi_clk_gate(struct clk *clk, int enable)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(clk->dev, &msg);
+	ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg);
 	if (ret)
 		return ret;
 
@@ -89,6 +100,7 @@ static int scmi_clk_disable(struct clk *clk)
 
 static ulong scmi_clk_get_rate(struct clk *clk)
 {
+	struct scmi_clk_priv *priv = dev_get_priv(clk->dev);
 	struct scmi_clk_rate_get_in in = {
 		.clock_id = clk->id,
 	};
@@ -98,7 +110,7 @@ static ulong scmi_clk_get_rate(struct clk *clk)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(clk->dev, &msg);
+	ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg);
 	if (ret < 0)
 		return ret;
 
@@ -111,6 +123,7 @@ static ulong scmi_clk_get_rate(struct clk *clk)
 
 static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
 {
+	struct scmi_clk_priv *priv = dev_get_priv(clk->dev);
 	struct scmi_clk_rate_set_in in = {
 		.clock_id = clk->id,
 		.flags = SCMI_CLK_RATE_ROUND_CLOSEST,
@@ -123,7 +136,7 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(clk->dev, &msg);
+	ret = devm_scmi_process_msg(clk->dev, priv->channel, &msg);
 	if (ret < 0)
 		return ret;
 
@@ -136,10 +149,15 @@ static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
 
 static int scmi_clk_probe(struct udevice *dev)
 {
+	struct scmi_clk_priv *priv = dev_get_priv(dev);
 	struct clk *clk;
 	size_t num_clocks, i;
 	int ret;
 
+	ret = devm_scmi_of_get_channel(dev, &priv->channel);
+	if (ret)
+		return ret;
+
 	if (!CONFIG_IS_ENABLED(CLK_CCF))
 		return 0;
 
@@ -186,5 +204,6 @@ U_BOOT_DRIVER(scmi_clock) = {
 	.name = "scmi_clk",
 	.id = UCLASS_CLK,
 	.ops = &scmi_clk_ops,
-	.probe = &scmi_clk_probe,
+	.probe = scmi_clk_probe,
+	.priv_auto = sizeof(struct scmi_clk_priv *),
 };
diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig
new file mode 100644
index 0000000..eac3fc1
--- /dev/null
+++ b/drivers/clk/stm32/Kconfig
@@ -0,0 +1,23 @@
+config CLK_STM32F
+	bool "Enable clock driver support for STM32F family"
+	depends on CLK && (STM32F7 || STM32F4)
+	default y
+	help
+	  This clock driver adds support for RCC clock management
+	  for STM32F4 and STM32F7 SoCs.
+
+config CLK_STM32H7
+	bool "Enable clock driver support for STM32H7 family"
+	depends on CLK && STM32H7
+	default y
+	help
+	  This clock driver adds support for RCC clock management
+	  for STM32H7 SoCs.
+
+config CLK_STM32MP1
+	bool "Enable RCC clock driver for STM32MP15"
+	depends on ARCH_STM32MP && CLK
+	default y if STM32MP15x
+	help
+	  Enable the STM32 clock (RCC) driver. Enable support for
+	  manipulating STM32MP15's on-SoC clocks.
diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile
new file mode 100644
index 0000000..f66f295
--- /dev/null
+++ b/drivers/clk/stm32/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+
+obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o
+obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o
+obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/stm32/clk-stm32f.c
index ed76601..ed76601 100644
--- a/drivers/clk/clk_stm32f.c
+++ b/drivers/clk/stm32/clk-stm32f.c
diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c
index d440c28..d440c28 100644
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/stm32/clk-stm32h7.c
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c
index 4525500..4525500 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/stm32/clk-stm32mp1.c
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index 74beb4d..0dd6593 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -74,6 +74,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
 		.data = &j721s2_clk_platdata,
 	},
 #endif
+#ifdef CONFIG_SOC_K3_AM625
+	{
+		.family = "AM62X",
+		.data = &am62x_clk_platdata,
+	},
+#endif
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 408a8d8..8eb0070 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -15,7 +15,7 @@ config SPL_DM
 	  Enable driver model in SPL. You will need to provide a
 	  suitable malloc() implementation. If you are not using the
 	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
-	  consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
+	  consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you
 	  must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
 	  In most cases driver model will only allocate a few uclasses
 	  and devices in SPL, so 1KB should be enable. See
@@ -28,7 +28,7 @@ config TPL_DM
 	  Enable driver model in TPL. You will need to provide a
 	  suitable malloc() implementation. If you are not using the
 	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
-	  consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
+	  consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you
 	  must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size.
 	  In most cases driver model will only allocate a few uclasses
 	  and devices in SPL, so 1KB should be enough. See
@@ -43,7 +43,7 @@ config VPL_DM
 	  Enable driver model in VPL. You will need to provide a
 	  suitable malloc() implementation. If you are not using the
 	  full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
-	  consider using CONFIG_SYS_MALLOC_SIMPLE.
+	  consider using CONFIG_SPL_SYS_MALLOC_SIMPLE.
 
 config DM_WARN
 	bool "Enable warnings in driver model"
@@ -75,6 +75,27 @@ config DM_DEBUG
 	help
 	  Say Y here if you want to compile in debug messages in DM core.
 
+config DM_STATS
+	bool "Collect and show driver model stats"
+	depends on DM
+	default y if SANDBOX
+	help
+	  Enable this to collect and display memory statistics about driver
+	  model. This can help to figure out where all the memory is going and
+	  to find optimisations.
+
+	  To display the memory stats, use the 'dm mem' command.
+
+config SPL_DM_STATS
+	bool "Collect and show driver model stats in SPL"
+	depends on DM_SPL
+	help
+	  Enable this to collect and display memory statistics about driver
+	  model. This can help to figure out where all the memory is going and
+	  to find optimisations.
+
+	  The stats are displayed just before SPL boots to the next phase.
+
 config DM_DEVICE_REMOVE
 	bool "Support device removal"
 	depends on DM
@@ -89,8 +110,7 @@ config DM_DEVICE_REMOVE
 
 config DM_EVENT
 	bool "Support events with driver model"
-	depends on DM
-	imply EVENT
+	depends on DM && EVENT
 	default y if SANDBOX
 	help
 	  This enables support for generating events related to driver model
@@ -225,7 +245,7 @@ config SPL_SYSCON
 
 config TPL_SYSCON
 	bool "Support system controllers in TPL"
-	depends on SPL_REGMAP
+	depends on TPL_REGMAP
 	help
 	  Many SoCs have a number of system controllers which are dealt with
 	  as a group by a single driver. Some common functionality is provided
diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index 73d2e9e..a86b932 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -29,7 +29,7 @@ int device_chld_unbind(struct udevice *dev, struct driver *drv)
 
 	assert(dev);
 
-	list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+	device_foreach_child_safe(pos, n, dev) {
 		if (drv && (pos->driver != drv))
 			continue;
 
@@ -52,7 +52,7 @@ int device_chld_remove(struct udevice *dev, struct driver *drv,
 
 	assert(dev);
 
-	list_for_each_entry_safe(pos, n, &dev->child_head, sibling_node) {
+	device_foreach_child_safe(pos, n, dev) {
 		int ret;
 
 		if (drv && (pos->driver != drv))
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 3ab2583..d9ce546 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -284,8 +284,7 @@ int device_reparent(struct udevice *dev, struct udevice *new_parent)
 	assert(dev);
 	assert(new_parent);
 
-	list_for_each_entry_safe(pos, n, &dev->parent->child_head,
-				 sibling_node) {
+	device_foreach_child_safe(pos, n, dev->parent) {
 		if (pos->driver != dev->driver)
 			continue;
 
@@ -328,13 +327,8 @@ static void *alloc_priv(int size, uint flags)
 			 * within this range at the start. The driver can then
 			 * use normal flush-after-write, invalidate-before-read
 			 * procedures.
-			 *
-			 * TODO(sjg@chromium.org): Drop this microblaze
-			 * exception.
 			 */
-#ifndef CONFIG_MICROBLAZE
 			flush_dcache_range((ulong)priv, (ulong)priv + size);
-#endif
 		}
 	} else {
 		priv = calloc(1, size);
@@ -680,6 +674,71 @@ void *dev_get_parent_priv(const struct udevice *dev)
 	return dm_priv_to_rw(dev->parent_priv_);
 }
 
+void *dev_get_attach_ptr(const struct udevice *dev, enum dm_tag_t tag)
+{
+	switch (tag) {
+	case DM_TAG_PLAT:
+		return dev_get_plat(dev);
+	case DM_TAG_PARENT_PLAT:
+		return dev_get_parent_plat(dev);
+	case DM_TAG_UC_PLAT:
+		return dev_get_uclass_plat(dev);
+	case DM_TAG_PRIV:
+		return dev_get_priv(dev);
+	case DM_TAG_PARENT_PRIV:
+		return dev_get_parent_priv(dev);
+	case DM_TAG_UC_PRIV:
+		return dev_get_uclass_priv(dev);
+	default:
+		return NULL;
+	}
+}
+
+int dev_get_attach_size(const struct udevice *dev, enum dm_tag_t tag)
+{
+	const struct udevice *parent = dev_get_parent(dev);
+	const struct uclass *uc = dev->uclass;
+	const struct uclass_driver *uc_drv = uc->uc_drv;
+	const struct driver *parent_drv = NULL;
+	int size = 0;
+
+	if (parent)
+		parent_drv = parent->driver;
+
+	switch (tag) {
+	case DM_TAG_PLAT:
+		size = dev->driver->plat_auto;
+		break;
+	case DM_TAG_PARENT_PLAT:
+		if (parent) {
+			size = parent_drv->per_child_plat_auto;
+			if (!size)
+				size = parent->uclass->uc_drv->per_child_plat_auto;
+		}
+		break;
+	case DM_TAG_UC_PLAT:
+		size = uc_drv->per_device_plat_auto;
+		break;
+	case DM_TAG_PRIV:
+		size = dev->driver->priv_auto;
+		break;
+	case DM_TAG_PARENT_PRIV:
+		if (parent) {
+			size = parent_drv->per_child_auto;
+			if (!size)
+				size = parent->uclass->uc_drv->per_child_auto;
+		}
+		break;
+	case DM_TAG_UC_PRIV:
+		size = uc_drv->per_device_auto;
+		break;
+	default:
+		break;
+	}
+
+	return size;
+}
+
 static int device_get_device_tail(struct udevice *dev, int ret,
 				  struct udevice **devp)
 {
@@ -729,7 +788,7 @@ int device_get_child(const struct udevice *parent, int index,
 {
 	struct udevice *dev;
 
-	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+	device_foreach_child(dev, parent) {
 		if (!index--)
 			return device_get_device_tail(dev, 0, devp);
 	}
@@ -742,7 +801,7 @@ int device_get_child_count(const struct udevice *parent)
 	struct udevice *dev;
 	int count = 0;
 
-	list_for_each_entry(dev, &parent->child_head, sibling_node)
+	device_foreach_child(dev, parent)
 		count++;
 
 	return count;
@@ -753,7 +812,7 @@ int device_get_decendent_count(const struct udevice *parent)
 	const struct udevice *dev;
 	int count = 1;
 
-	list_for_each_entry(dev, &parent->child_head, sibling_node)
+	device_foreach_child(dev, parent)
 		count += device_get_decendent_count(dev);
 
 	return count;
@@ -766,7 +825,7 @@ int device_find_child_by_seq(const struct udevice *parent, int seq,
 
 	*devp = NULL;
 
-	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+	device_foreach_child(dev, parent) {
 		if (dev->seq_ == seq) {
 			*devp = dev;
 			return 0;
@@ -795,7 +854,7 @@ int device_find_child_by_of_offset(const struct udevice *parent, int of_offset,
 
 	*devp = NULL;
 
-	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+	device_foreach_child(dev, parent) {
 		if (dev_of_offset(dev) == of_offset) {
 			*devp = dev;
 			return 0;
@@ -824,7 +883,7 @@ static struct udevice *_device_find_global_by_ofnode(struct udevice *parent,
 	if (ofnode_equal(dev_ofnode(parent), ofnode))
 		return parent;
 
-	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+	device_foreach_child(dev, parent) {
 		found = _device_find_global_by_ofnode(dev, ofnode);
 		if (found)
 			return found;
@@ -902,7 +961,7 @@ int device_find_first_inactive_child(const struct udevice *parent,
 	struct udevice *dev;
 
 	*devp = NULL;
-	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+	device_foreach_child(dev, parent) {
 		if (!device_active(dev) &&
 		    device_get_uclass_id(dev) == uclass_id) {
 			*devp = dev;
@@ -920,7 +979,7 @@ int device_find_first_child_by_uclass(const struct udevice *parent,
 	struct udevice *dev;
 
 	*devp = NULL;
-	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+	device_foreach_child(dev, parent) {
 		if (device_get_uclass_id(dev) == uclass_id) {
 			*devp = dev;
 			return 0;
@@ -937,7 +996,7 @@ int device_find_child_by_namelen(const struct udevice *parent, const char *name,
 
 	*devp = NULL;
 
-	list_for_each_entry(dev, &parent->child_head, sibling_node) {
+	device_foreach_child(dev, parent) {
 		if (!strncmp(dev->name, name, len) &&
 		    strlen(dev->name) == len) {
 			*devp = dev;
@@ -1125,9 +1184,7 @@ bool device_is_compatible(const struct udevice *dev, const char *compat)
 
 bool of_machine_is_compatible(const char *compat)
 {
-	const void *fdt = gd->fdt_blob;
-
-	return !fdt_node_check_compatible(fdt, 0, compat);
+	return ofnode_device_is_compatible(ofnode_root(), compat);
 }
 
 int dev_disable_by_path(const char *path)
diff --git a/drivers/core/devres.c b/drivers/core/devres.c
index 313ddc7..78914bd 100644
--- a/drivers/core/devres.c
+++ b/drivers/core/devres.c
@@ -232,7 +232,7 @@ static void dump_resources(struct udevice *dev, int depth)
 		       (unsigned long)dr->size, dr->name,
 		       devres_phase_name[dr->phase]);
 
-	list_for_each_entry(child, &dev->child_head, sibling_node)
+	device_foreach_child(child, dev)
 		dump_resources(child, depth + 1);
 }
 
diff --git a/drivers/core/dump.c b/drivers/core/dump.c
index f2f9cac..1c1f7e4 100644
--- a/drivers/core/dump.c
+++ b/drivers/core/dump.c
@@ -39,13 +39,13 @@ static void show_devices(struct udevice *dev, int depth, int last_flag)
 
 	printf("%s\n", dev->name);
 
-	list_for_each_entry(child, &dev->child_head, sibling_node) {
+	device_foreach_child(child, dev) {
 		is_last = list_is_last(&child->sibling_node, &dev->child_head);
 		show_devices(child, depth + 1, (last_flag << 1) | is_last);
 	}
 }
 
-void dm_dump_all(void)
+void dm_dump_tree(void)
 {
 	struct udevice *root;
 
@@ -89,8 +89,6 @@ void dm_dump_uclass(void)
 			continue;
 
 		printf("uclass %d: %s\n", id, uc->uc_drv->name);
-		if (list_empty(&uc->dev_head))
-			continue;
 		uclass_foreach_dev(dev, uc) {
 			dm_display_line(dev, i);
 			i++;
@@ -171,8 +169,79 @@ void dm_dump_static_driver_info(void)
 
 	puts("Driver                    Address\n");
 	puts("---------------------------------\n");
-	for (entry = drv; entry != drv + n_ents; entry++) {
-		printf("%-25.25s @%08lx\n", entry->name,
-		       (ulong)map_to_sysmem(entry->plat));
+	for (entry = drv; entry != drv + n_ents; entry++)
+		printf("%-25.25s %p\n", entry->name, entry->plat);
+}
+
+void dm_dump_mem(struct dm_stats *stats)
+{
+	int total, total_delta;
+	int i;
+
+	/* Support SPL printf() */
+	printf("Struct sizes: udevice %x, driver %x, uclass %x, uc_driver %x\n",
+	       (int)sizeof(struct udevice), (int)sizeof(struct driver),
+	       (int)sizeof(struct uclass), (int)sizeof(struct uclass_driver));
+	printf("Memory: device %x:%x, device names %x, uclass %x:%x\n",
+	       stats->dev_count, stats->dev_size, stats->dev_name_size,
+	       stats->uc_count, stats->uc_size);
+	printf("\n");
+	printf("%-15s  %5s  %5s  %5s  %5s  %5s\n", "Attached type", "Count",
+	       "Size", "Cur", "Tags", "Save");
+	printf("%-15s  %5s  %5s  %5s  %5s  %5s\n", "---------------", "-----",
+	       "-----", "-----", "-----", "-----");
+	total_delta = 0;
+	for (i = 0; i < DM_TAG_ATTACH_COUNT; i++) {
+		int cur_size, new_size, delta;
+
+		cur_size = stats->dev_count * sizeof(struct udevice);
+		new_size = stats->dev_count * (sizeof(struct udevice) -
+			sizeof(void *));
+		/*
+		 * Let's assume we can fit each dmtag_node into 32 bits. We can
+		 * limit the 'tiny tags' feature to SPL with
+		 * CONFIG_SPL_SYS_MALLOC_F_LEN <= 64KB, so needing 14 bits to
+		 * point to anything in that region (with 4-byte alignment).
+		 * So:
+		 *    4 bits for tag
+		 *    14 bits for offset of dev
+		 *    14 bits for offset of data
+		 */
+		new_size += stats->attach_count[i] * sizeof(u32);
+		delta = cur_size - new_size;
+		total_delta += delta;
+		printf("%-16s %5x %6x %6x %6x %6x (%d)\n", tag_get_name(i),
+		       stats->attach_count[i], stats->attach_size[i],
+		       cur_size, new_size, delta > 0 ? delta : 0, delta);
 	}
+	printf("%-16s %5x %6x\n", "uclass", stats->uc_attach_count,
+	       stats->uc_attach_size);
+	printf("%-16s %5x %6x  %5s  %5s  %6x (%d)\n", "Attached total",
+	       stats->attach_count_total + stats->uc_attach_count,
+	       stats->attach_size_total + stats->uc_attach_size, "", "",
+	       total_delta > 0 ? total_delta : 0, total_delta);
+	printf("%-16s %5x %6x\n", "tags", stats->tag_count, stats->tag_size);
+	printf("\n");
+	printf("Total size: %x (%d)\n", stats->total_size, stats->total_size);
+	printf("\n");
+
+	total = stats->total_size;
+	total -= total_delta;
+	printf("With tags:       %x (%d)\n", total, total);
+
+	/* Use singly linked lists in struct udevice (3 nodes in each) */
+	total -= sizeof(void *) * 3 * stats->dev_count;
+	printf("- singly-linked: %x (%d)\n", total, total);
+
+	/* Use an index into the struct_driver list instead of a pointer */
+	total = total + stats->dev_count * (1 - sizeof(void *));
+	printf("- driver index:  %x (%d)\n", total, total);
+
+	/* Same with the uclass */
+	total = total + stats->dev_count * (1 - sizeof(void *));
+	printf("- uclass index:  %x (%d)\n", total, total);
+
+	/* Drop the device name */
+	printf("Drop device name (not SRAM): %x (%d)\n", stats->dev_name_size,
+	       stats->dev_name_size);
 }
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 17dd120..f24ddfa 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -449,6 +449,59 @@ void dm_get_stats(int *device_countp, int *uclass_countp)
 	*uclass_countp = uclass_get_count();
 }
 
+void dev_collect_stats(struct dm_stats *stats, const struct udevice *parent)
+{
+	const struct udevice *dev;
+	int i;
+
+	stats->dev_count++;
+	stats->dev_size += sizeof(struct udevice);
+	stats->dev_name_size += strlen(parent->name) + 1;
+	for (i = 0; i < DM_TAG_ATTACH_COUNT; i++) {
+		int size = dev_get_attach_size(parent, i);
+
+		if (size ||
+		    (i == DM_TAG_DRIVER_DATA && parent->driver_data)) {
+			stats->attach_count[i]++;
+			stats->attach_size[i] += size;
+			stats->attach_count_total++;
+			stats->attach_size_total += size;
+		}
+	}
+
+	list_for_each_entry(dev, &parent->child_head, sibling_node)
+		dev_collect_stats(stats, dev);
+}
+
+void uclass_collect_stats(struct dm_stats *stats)
+{
+	struct uclass *uc;
+
+	list_for_each_entry(uc, gd->uclass_root, sibling_node) {
+		int size;
+
+		stats->uc_count++;
+		stats->uc_size += sizeof(struct uclass);
+		size = uc->uc_drv->priv_auto;
+		if (size) {
+			stats->uc_attach_count++;
+			stats->uc_attach_size += size;
+		}
+	}
+}
+
+void dm_get_mem(struct dm_stats *stats)
+{
+	memset(stats, '\0', sizeof(*stats));
+	dev_collect_stats(stats, gd->dm_root);
+	uclass_collect_stats(stats);
+	dev_tag_collect_stats(stats);
+
+	stats->total_size = stats->dev_size + stats->uc_size +
+		stats->attach_size_total + stats->uc_attach_size +
+		stats->tag_size;
+}
+
 #ifdef CONFIG_ACPIGEN
 static int root_acpi_get_name(const struct udevice *dev, char *out_name)
 {
diff --git a/drivers/core/tag.c b/drivers/core/tag.c
index 2299919..a3c5cb7 100644
--- a/drivers/core/tag.c
+++ b/drivers/core/tag.c
@@ -6,6 +6,7 @@
 
 #include <malloc.h>
 #include <asm/global_data.h>
+#include <dm/root.h>
 #include <dm/tag.h>
 #include <linux/err.h>
 #include <linux/list.h>
@@ -15,6 +16,24 @@ struct udevice;
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const char *const tag_name[] = {
+	[DM_TAG_PLAT]		= "plat",
+	[DM_TAG_PARENT_PLAT]	= "parent_plat",
+	[DM_TAG_UC_PLAT]	= "uclass_plat",
+
+	[DM_TAG_PRIV]		= "priv",
+	[DM_TAG_PARENT_PRIV]	= "parent_priv",
+	[DM_TAG_UC_PRIV]	= "uclass_priv",
+	[DM_TAG_DRIVER_DATA]	= "driver_data",
+
+	[DM_TAG_EFI]		= "efi",
+};
+
+const char *tag_get_name(enum dm_tag_t tag)
+{
+	return tag_name[tag];
+}
+
 int dev_tag_set_ptr(struct udevice *dev, enum dm_tag_t tag, void *ptr)
 {
 	struct dmtag_node *node;
@@ -137,3 +156,13 @@ int dev_tag_del_all(struct udevice *dev)
 
 	return -ENOENT;
 }
+
+void dev_tag_collect_stats(struct dm_stats *stats)
+{
+	struct dmtag_node *node;
+
+	list_for_each_entry(node, &gd->dmtag_list, sibling) {
+		stats->tag_count++;
+		stats->tag_size += sizeof(struct dmtag_node);
+	}
+}
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index 7897281..2187433 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -19,3 +19,12 @@ config CPU_RISCV
 	depends on CPU && RISCV
 	help
 	  Support CPU cores for RISC-V architecture.
+
+config CPU_MICROBLAZE
+	bool "Enable Microblaze CPU driver"
+	depends on CPU && MICROBLAZE
+	select EVENT
+	select DM_EVENT
+	select XILINX_MICROBLAZE0_PVR
+	help
+	  Support CPU cores for Microblaze architecture.
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index c853263..20884b1 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
 obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
 obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
 obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
+obj-$(CONFIG_CPU_MICROBLAZE) += microblaze_cpu.o
 obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index a5cda6a..71e5900 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -14,6 +14,9 @@
 #include <dm/lists.h>
 #include <dm/root.h>
 #include <linux/err.h>
+#include <relocate.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 int cpu_probe_all(void)
 {
@@ -136,9 +139,36 @@ static int uclass_cpu_init(struct uclass *uc)
 	return ret;
 }
 
+static int uclass_cpu_post_bind(struct udevice *dev)
+{
+	if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) &&
+	    (gd->flags & GD_FLG_RELOC)) {
+		struct cpu_ops *ops = cpu_get_ops(dev);
+		static int reloc_done;
+
+		if (!reloc_done) {
+			if (ops->get_desc)
+				MANUAL_RELOC(ops->get_desc);
+			if (ops->get_info)
+				MANUAL_RELOC(ops->get_info);
+			if (ops->get_count)
+				MANUAL_RELOC(ops->get_count);
+			if (ops->get_vendor)
+				MANUAL_RELOC(ops->get_vendor);
+			if (ops->is_current)
+				MANUAL_RELOC(ops->is_current);
+
+			reloc_done++;
+		}
+	}
+
+	return 0;
+}
+
 UCLASS_DRIVER(cpu) = {
 	.id		= UCLASS_CPU,
 	.name		= "cpu",
 	.flags		= DM_UC_FLAG_SEQ_ALIAS,
 	.init		= uclass_cpu_init,
+	.post_bind	= uclass_cpu_post_bind,
 };
diff --git a/drivers/cpu/microblaze_cpu.c b/drivers/cpu/microblaze_cpu.c
new file mode 100644
index 0000000..969a104
--- /dev/null
+++ b/drivers/cpu/microblaze_cpu.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
+ */
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <asm/cpuinfo.h>
+#include <asm/global_data.h>
+#include <asm/pvr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define update_cpuinfo_pvr(pvr, ci, name)					\
+{										\
+	u32 tmp = PVR_##name(pvr);						\
+	if (ci != tmp)								\
+		printf("PVR value for " #name " does not match static data!\n");\
+	ci = tmp;								\
+}
+
+static int microblaze_cpu_probe_all(void *ctx, struct event *event)
+{
+	int ret;
+
+	ret = cpu_probe_all();
+	if (ret)
+		return log_msg_ret("Microblaze cpus probe failed\n", ret);
+
+	return 0;
+}
+EVENT_SPY(EVT_DM_POST_INIT, microblaze_cpu_probe_all);
+
+static void microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo *ci)
+{
+	u32 pvr[PVR_FULL_COUNT];
+
+	microblaze_get_all_pvrs(pvr);
+
+	update_cpuinfo_pvr(pvr, ci->icache_size, ICACHE_BYTE_SIZE);
+	update_cpuinfo_pvr(pvr, ci->icache_line_length, ICACHE_LINE_LEN);
+
+	update_cpuinfo_pvr(pvr, ci->dcache_size, DCACHE_BYTE_SIZE);
+	update_cpuinfo_pvr(pvr, ci->dcache_line_length, DCACHE_LINE_LEN);
+
+	update_cpuinfo_pvr(pvr, ci->use_mmu, USE_MMU);
+	update_cpuinfo_pvr(pvr, ci->ver_code, VERSION);
+	update_cpuinfo_pvr(pvr, ci->fpga_code, TARGET_FAMILY);
+}
+
+static void microblaze_set_cpuinfo_static(struct udevice *dev,
+					  struct microblaze_cpuinfo *ci)
+{
+	const char *hw_ver = CONFIG_XILINX_MICROBLAZE0_HW_VER;
+	const char *fpga_family = CONFIG_XILINX_MICROBLAZE0_FPGA_FAMILY;
+
+	ci->icache_size = dev_read_u32_default(dev, "i-cache-size", 0);
+	ci->icache_line_length = dev_read_u32_default(dev,
+						"i-cache-line-size", 0);
+
+	ci->dcache_size = dev_read_u32_default(dev, "d-cache-size", 0);
+	ci->dcache_line_length = dev_read_u32_default(dev,
+						"d-cache-line-size", 0);
+
+	ci->cpu_freq = dev_read_u32_default(dev, "clock-frequency", 0);
+	ci->addr_size = dev_read_u32_default(dev, "xlnx,addr-size", 32);
+	ci->use_mmu = dev_read_u32_default(dev, "xlnx,use-mmu", 0);
+
+	ci->ver_code = microblaze_lookup_cpu_version_code(hw_ver);
+	ci->fpga_code = microblaze_lookup_fpga_family_code(fpga_family);
+}
+
+static int microblaze_cpu_probe(struct udevice *dev)
+{
+	microblaze_set_cpuinfo_static(dev, gd_cpuinfo());
+
+	if (microblaze_cpu_has_pvr_full())
+		microblaze_set_cpuinfo_pvr(gd_cpuinfo());
+	else
+		debug("No PVR support. Using only static CPU info.\n");
+
+	return 0;
+}
+
+static int microblaze_cpu_get_desc(const struct udevice *dev, char *buf,
+				   int size)
+{
+	struct microblaze_cpuinfo *ci = gd_cpuinfo();
+	const char *cpu_ver, *fpga_family;
+	u32 cpu_freq_mhz;
+	int ret;
+
+	cpu_freq_mhz = ci->cpu_freq / 1000000;
+	cpu_ver = microblaze_lookup_cpu_version_string(ci->ver_code);
+	fpga_family = microblaze_lookup_fpga_family_string(ci->fpga_code);
+
+	ret = snprintf(buf, size,
+		       "MicroBlaze @ %uMHz, Rev: %s, FPGA family: %s",
+		       cpu_freq_mhz, cpu_ver, fpga_family);
+
+	return 0;
+}
+
+static int microblaze_cpu_get_info(const struct udevice *dev,
+				   struct cpu_info *info)
+{
+	struct microblaze_cpuinfo *ci = gd_cpuinfo();
+
+	info->cpu_freq = ci->cpu_freq;
+	info->address_width = ci->addr_size;
+
+	if (ci->icache_size || ci->dcache_size)
+		info->features |= BIT(CPU_FEAT_L1_CACHE);
+
+	if (ci->use_mmu)
+		info->features |= BIT(CPU_FEAT_MMU);
+
+	return 0;
+}
+
+static int microblaze_cpu_get_count(const struct udevice *dev)
+{
+	return 1;
+}
+
+static const struct cpu_ops microblaze_cpu_ops = {
+	.get_desc	= microblaze_cpu_get_desc,
+	.get_info	= microblaze_cpu_get_info,
+	.get_count	= microblaze_cpu_get_count,
+};
+
+static const struct udevice_id microblaze_cpu_ids[] = {
+	{ .compatible = "xlnx,microblaze-11.0" },
+	{ .compatible = "xlnx,microblaze-10.0" },
+	{ .compatible = "xlnx,microblaze-9.6" },
+	{ .compatible = "xlnx,microblaze-9.5" },
+	{ .compatible = "xlnx,microblaze-9.4" },
+	{ .compatible = "xlnx,microblaze-9.3" },
+	{ .compatible = "xlnx,microblaze-9.2" },
+	{ .compatible = "xlnx,microblaze-9.1" },
+	{ .compatible = "xlnx,microblaze-9.0" },
+	{ .compatible = "xlnx,microblaze-8.50.c" },
+	{ .compatible = "xlnx,microblaze-8.50.b" },
+	{ .compatible = "xlnx,microblaze-8.50.a" },
+	{ .compatible = "xlnx,microblaze-8.40.b" },
+	{ .compatible = "xlnx,microblaze-8.40.a" },
+	{ .compatible = "xlnx,microblaze-8.30.a" },
+	{ .compatible = "xlnx,microblaze-8.20.b" },
+	{ .compatible = "xlnx,microblaze-8.20.a" },
+	{ .compatible = "xlnx,microblaze-8.10.a" },
+	{ .compatible = "xlnx,microblaze-8.00.b" },
+	{ .compatible = "xlnx,microblaze-8.00.a" },
+	{ .compatible = "xlnx,microblaze-7.30.b" },
+	{ .compatible = "xlnx,microblaze-7.30.a" },
+	{ .compatible = "xlnx,microblaze-7.20.d" },
+	{ .compatible = "xlnx,microblaze-7.20.c" },
+	{ .compatible = "xlnx,microblaze-7.20.b" },
+	{ .compatible = "xlnx,microblaze-7.20.a" },
+	{ .compatible = "xlnx,microblaze-7.10.d" },
+	{ .compatible = "xlnx,microblaze-7.10.c" },
+	{ .compatible = "xlnx,microblaze-7.10.b" },
+	{ .compatible = "xlnx,microblaze-7.10.a" },
+	{ .compatible = "xlnx,microblaze-7.00.b" },
+	{ .compatible = "xlnx,microblaze-7.00.a" },
+	{ .compatible = "xlnx,microblaze-6.00.b" },
+	{ .compatible = "xlnx,microblaze-6.00.a" },
+	{ .compatible = "xlnx,microblaze-5.00.c" },
+	{ .compatible = "xlnx,microblaze-5.00.b" },
+	{ .compatible = "xlnx,microblaze-5.00.a" },
+	{ }
+};
+
+U_BOOT_DRIVER(microblaze_cpu) = {
+	.name		= "microblaze_cpu",
+	.id		= UCLASS_CPU,
+	.of_match	= microblaze_cpu_ids,
+	.probe		= microblaze_cpu_probe,
+	.ops		= &microblaze_cpu_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 675081e..12ef84c 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -6,4 +6,6 @@ source drivers/crypto/fsl/Kconfig
 
 source drivers/crypto/aspeed/Kconfig
 
+source drivers/crypto/nuvoton/Kconfig
+
 endmenu
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 6b76256..b910518 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -8,3 +8,4 @@ obj-y += rsa_mod_exp/
 obj-y += fsl/
 obj-y += hash/
 obj-y += aspeed/
+obj-y += nuvoton/
diff --git a/drivers/crypto/nuvoton/Kconfig b/drivers/crypto/nuvoton/Kconfig
new file mode 100644
index 0000000..034fcad
--- /dev/null
+++ b/drivers/crypto/nuvoton/Kconfig
@@ -0,0 +1,14 @@
+config NPCM_AES
+	bool "Support the NPCM AES algorithm"
+	select NPCM_OTP
+	help
+	  This provides a means to encrypt and decrypt data using the NPCM
+	  AES (Advanced Encryption Standard). This algorithm uses a symmetric
+	  key and is widely used as a streaming cipher. This command only
+	  supports AES256-CBC.
+
+config NPCM_SHA
+	bool "Enable NPCM cryptographic HW SHA accelerator"
+	help
+	  This option enables support of NPCM cryptographic HW SHA accelerator.
+	  It supports SHA1 and SHA256 hashing algorithms.
diff --git a/drivers/crypto/nuvoton/Makefile b/drivers/crypto/nuvoton/Makefile
new file mode 100644
index 0000000..5a1173d
--- /dev/null
+++ b/drivers/crypto/nuvoton/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_NPCM_AES) += npcm_aes.o
+obj-$(CONFIG_NPCM_SHA) += npcm_sha.o
diff --git a/drivers/crypto/nuvoton/npcm_aes.c b/drivers/crypto/nuvoton/npcm_aes.c
new file mode 100644
index 0000000..6493ea1
--- /dev/null
+++ b/drivers/crypto/nuvoton/npcm_aes.c
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <uboot_aes.h>
+#include <asm/io.h>
+#include <asm/arch/aes.h>
+#include <asm/arch/otp.h>
+#include <malloc.h>
+
+#define ONE_SECOND 0xC00000
+
+struct npcm_aes_priv {
+	struct npcm_aes_regs *regs;
+};
+
+static struct npcm_aes_priv *aes_priv;
+static u8 fkeyind_to_set = 0xff;
+
+static int second_timeout(u32 *addr, u32 bitmask, u32 bitpol)
+{
+	ulong time, i = 0;
+
+	time = get_timer(0);
+
+	/* default 1 second timeout */
+	while (((readl(addr) & bitmask) == bitpol) && i < ONE_SECOND)
+		i++;
+
+	if (i == ONE_SECOND) {
+		printf("%xms timeout: addr = %x, mask = %x\n", (u32)get_timer(time),
+		       *addr, bitmask);
+		return -1;
+	}
+
+	return 0;
+}
+
+int npcm_aes_select_key(u8 fkeyind)
+{
+	if (npcm_otp_is_fuse_array_disabled(NPCM_KEY_SA)) {
+		printf("AES key access denied\n");
+		return -EACCES;
+	}
+
+	if (fkeyind < 4)
+		fkeyind_to_set = fkeyind;
+
+	return 0;
+}
+
+static int npcm_aes_init(u8 dec_enc)
+{
+	struct npcm_aes_regs *regs = aes_priv->regs;
+	u32 ctrl, orgctrlval, wrtimeout;
+
+	/* reset hw */
+	writel(readl(&regs->aes_sw_reset) | SW_RESET_BIT, &regs->aes_sw_reset);
+	writel(readl(&regs->aes_fifo_status) | DIN_FIFO_OVERFLOW, &regs->aes_fifo_status);
+	writel(readl(&regs->aes_fifo_status) | DOUT_FIFO_UNDERFLOW, &regs->aes_fifo_status);
+
+	/* Workaround to over come Errata #648 */
+	orgctrlval = readl(&regs->aes_control);
+	ctrl = (0x00002004 | dec_enc);    /* AES256(CBC) */
+
+	if (ctrl != orgctrlval) {
+		writel(ctrl, &regs->aes_control);
+
+		if (ctrl != readl(&regs->aes_control)) {
+			u32 read_ctrl;
+			int intwr;
+
+			for (wrtimeout = 0; wrtimeout < 1000; wrtimeout++) {
+				for (intwr = 0 ; intwr < 10; intwr++) {
+					writel(ctrl, &regs->aes_control);
+					writew(ctrl, (u16 *)&regs->aes_control + 1);
+					/* Write configurable info in a single write operation */
+					mb();
+				}
+
+				read_ctrl = readl(&regs->aes_control);
+				if (ctrl == read_ctrl)
+					break;
+			}
+
+			if (wrtimeout == 1000) {
+				printf("\nTIMEOUT expected data=0x%x Actual AES_CONTROL data 0x%x\n\n",
+				       ctrl, read_ctrl);
+				return -EAGAIN;
+			}
+
+			printf("Workaround success, wrtimeout = %d\n", wrtimeout);
+		}
+	}
+
+	if (second_timeout(&regs->aes_busy, AES_BUSY_BIT, AES_BUSY_BIT))
+		return -EAGAIN;
+
+	return 0;
+}
+
+static inline void npcm_aes_load_iv(u8 *iv)
+{
+	struct npcm_aes_regs *regs = aes_priv->regs;
+	u32 *p = (u32 *)iv;
+	u32 i;
+
+	/* Initialization Vector is loaded in 32-bit chunks */
+	for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++)
+		writel(p[i], &regs->aes_iv_0 + i);
+}
+
+static inline void npcm_aes_load_key(u8 *key)
+{
+	struct npcm_aes_regs *regs = aes_priv->regs;
+	u32 *p = (u32 *)key;
+	u32 i;
+
+	/* The key can be loaded either via the configuration or by using sideband
+	 *  key port (aes_select_key).
+	 *  If aes_select_key has been called ('fkeyind_to_set' was set to desired
+	 *  key index) and no key is specified (key is NULL), we should use the
+	 *  key index. Otherwise, we write the given key to the registers.
+	 */
+	if (!key && fkeyind_to_set < 4) {
+		npcm_otp_select_key(fkeyind_to_set);
+
+		/* Sample the new key */
+		writel(readl(&regs->aes_sk) | AES_SK_BIT, &regs->aes_sk);
+
+	} else {
+		/* Initialization Vector is loaded in 32-bit chunks */
+		for (i = 0; i < (2 * SIZE_AES_BLOCK / sizeof(u32)); i++)
+			writel(p[i], &regs->aes_key_0 + i);
+
+		fkeyind_to_set = 0xff;
+	}
+}
+
+static inline void npcm_aes_write(u32 *in)
+{
+	struct npcm_aes_regs *regs = aes_priv->regs;
+	u32 i;
+
+	/* 16 Byte AES Block is written in 32-bit chunks */
+	for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++)
+		writel(in[i], &regs->aes_fifo_data);
+}
+
+static inline void npcm_aes_read(u32 *out)
+{
+	struct npcm_aes_regs *regs = aes_priv->regs;
+	u32 i;
+
+	/* Data is read in 32-bit chunks */
+	for (i = 0; i < (SIZE_AES_BLOCK / sizeof(u32)); i++)
+		out[i] = readl(&regs->aes_fifo_data);
+}
+
+static void npcm_aes_feed(u32 num_aes_blocks, u32 *datain, u32 *dataout)
+{
+	struct npcm_aes_regs *regs = aes_priv->regs;
+	u32 aes_datablk;
+	u32 total_blocks = num_aes_blocks;
+	u32 blocks_left = num_aes_blocks;
+
+	/* data mode */
+	writel(readl(&regs->aes_busy) | AES_BUSY_BIT, &regs->aes_busy);
+
+	/* Clear overflow and underflow */
+	writel(readl(&regs->aes_fifo_status) | DIN_FIFO_OVERFLOW, &regs->aes_fifo_status);
+	writel(readl(&regs->aes_fifo_status) | DOUT_FIFO_UNDERFLOW, &regs->aes_fifo_status);
+
+	/* datain/dataout is advanced in 32-bit chunks */
+	aes_datablk = (SIZE_AES_BLOCK / sizeof(u32));
+
+	/* Quit if there is no complete blocks */
+	if (total_blocks == 0)
+		return;
+
+	/* Write the first block */
+	if (total_blocks > 1) {
+		npcm_aes_write(datain);
+		datain += aes_datablk;
+		blocks_left--;
+	}
+
+	/* Write the second block */
+	if (total_blocks > 2) {
+		second_timeout(&regs->aes_fifo_status, DIN_FIFO_EMPTY, 0);
+		npcm_aes_write(datain);
+		datain += aes_datablk;
+		blocks_left--;
+	}
+
+	/* Write & read available blocks */
+	while (blocks_left > 0) {
+		second_timeout(&regs->aes_fifo_status, DIN_FIFO_FULL, DIN_FIFO_FULL);
+
+		/* Write next block */
+		npcm_aes_write(datain);
+		datain  += aes_datablk;
+
+		/* Wait till DOUT FIFO is empty */
+		second_timeout(&regs->aes_fifo_status, DOUT_FIFO_EMPTY, DOUT_FIFO_EMPTY);
+
+		/* Read next block */
+		npcm_aes_read(dataout);
+		dataout += aes_datablk;
+
+		blocks_left--;
+	}
+
+	if (total_blocks > 2) {
+		second_timeout(&regs->aes_fifo_status, DOUT_FIFO_FULL, 0);
+
+		/* Read next block */
+		npcm_aes_read(dataout);
+		dataout += aes_datablk;
+
+		second_timeout(&regs->aes_fifo_status, DOUT_FIFO_FULL, 0);
+
+		/* Read next block */
+		npcm_aes_read(dataout);
+		dataout += aes_datablk;
+	} else if (total_blocks > 1) {
+		second_timeout(&regs->aes_fifo_status, DOUT_FIFO_FULL, 0);
+
+		/* Read next block */
+		npcm_aes_read(dataout);
+		dataout += aes_datablk;
+	}
+}
+
+void aes_expand_key(u8 *key, u32 key_size, u8 *expkey)
+{
+	/* npcm hw expands the key automatically, just copy it */
+	memcpy(expkey, key, SIZE_AES_BLOCK * 2);
+}
+
+void aes_cbc_encrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+			    u32 num_aes_blocks)
+{
+	if (npcm_aes_init(AES_OP_ENCRYPT))
+		return;
+
+	npcm_aes_load_iv(iv);
+
+	npcm_aes_load_key(key_exp);
+
+	npcm_aes_feed(num_aes_blocks, (u32 *)src, (u32 *)dst);
+}
+
+void aes_cbc_decrypt_blocks(u32 key_size, u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+			    u32 num_aes_blocks)
+{
+	if (npcm_aes_init(AES_OP_DECRYPT))
+		return;
+
+	npcm_aes_load_iv(iv);
+
+	npcm_aes_load_key(key_exp);
+
+	npcm_aes_feed(num_aes_blocks, (u32 *)src, (u32 *)dst);
+}
+
+static int npcm_aes_bind(struct udevice *dev)
+{
+	aes_priv = calloc(1, sizeof(struct npcm_aes_priv));
+	if (!aes_priv) {
+		printf("%s: %d\n", __func__, __LINE__);
+		return -ENOMEM;
+	}
+
+	aes_priv->regs = dev_read_addr_ptr(dev);
+	if (!aes_priv->regs) {
+		printf("Cannot find aes reg address, binding failed\n");
+		return -EINVAL;
+	}
+
+	printf("AES: NPCM AES module bind OK\n");
+
+	return 0;
+}
+
+static const struct udevice_id npcm_aes_ids[] = {
+	{ .compatible = "nuvoton,npcm845-aes" },
+	{ .compatible = "nuvoton,npcm750-aes" },
+	{ }
+};
+
+U_BOOT_DRIVER(npcm_aes) = {
+	.name = "npcm_aes",
+	.id = UCLASS_MISC,
+	.of_match = npcm_aes_ids,
+	.priv_auto = sizeof(struct npcm_aes_priv),
+	.bind = npcm_aes_bind,
+};
diff --git a/drivers/crypto/nuvoton/npcm_sha.c b/drivers/crypto/nuvoton/npcm_sha.c
new file mode 100644
index 0000000..7ebdfa1
--- /dev/null
+++ b/drivers/crypto/nuvoton/npcm_sha.c
@@ -0,0 +1,897 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <hash.h>
+#include <malloc.h>
+#include <uboot_aes.h>
+#include <asm/io.h>
+
+#define HASH_DIG_H_NUM			8
+
+#define HASH_CTR_STS_SHA_EN             BIT(0)
+#define HASH_CTR_STS_SHA_BUSY           BIT(1)
+#define HASH_CTR_STS_SHA_RST            BIT(2)
+#define HASH_CFG_SHA1_SHA2              BIT(0)
+
+/* SHA type */
+enum npcm_sha_type {
+	npcm_sha_type_sha2 = 0,
+	npcm_sha_type_sha1,
+	npcm_sha_type_num
+};
+
+struct npcm_sha_regs {
+	unsigned int hash_data_in;
+	unsigned char hash_ctr_sts;
+	unsigned char reserved_0[0x03];
+	unsigned char hash_cfg;
+	unsigned char reserved_1[0x03];
+	unsigned char hash_ver;
+	unsigned char reserved_2[0x13];
+	unsigned int hash_dig[HASH_DIG_H_NUM];
+};
+
+struct npcm_sha_priv {
+	struct npcm_sha_regs *regs;
+};
+
+static struct npcm_sha_priv *sha_priv;
+
+#ifdef SHA_DEBUG_MODULE
+#define sha_print(fmt, args...)  printf(fmt, ##args)
+#else
+#define sha_print(fmt, args...)  (void)0
+#endif
+
+#define SHA_BLOCK_LENGTH        (512 / 8)
+#define SHA_2_HASH_LENGTH       (256 / 8)
+#define SHA_1_HASH_LENGTH       (160 / 8)
+#define SHA_HASH_LENGTH(type)   ((type == npcm_sha_type_sha2) ? \
+							(SHA_2_HASH_LENGTH) : (SHA_1_HASH_LENGTH))
+
+#define SHA_SECRUN_BUFF_SIZE    64
+#define SHA_TIMEOUT             100
+#define SHA_DATA_LAST_BYTE      0x80
+
+#define SHA2_NUM_OF_SELF_TESTS  3
+#define SHA1_NUM_OF_SELF_TESTS  4
+
+#define NUVOTON_ALIGNMENT       4
+
+/*-----------------------------------------------------------------------------*/
+/* SHA instance struct handler                                                 */
+/*-----------------------------------------------------------------------------*/
+struct SHA_HANDLE_T {
+	u32                 hv[SHA_2_HASH_LENGTH / sizeof(u32)];
+	u32                 length0;
+	u32                 length1;
+	u32					block[SHA_BLOCK_LENGTH / sizeof(u32)];
+	u8					type;
+	bool                active;
+};
+
+// The # of bytes currently in the sha  block buffer
+#define SHA_BUFF_POS(length)        ((length) & (SHA_BLOCK_LENGTH - 1))
+
+// The # of free bytes in the sha block buffer
+#define SHA_BUFF_FREE(length)       (SHA_BLOCK_LENGTH - SHA_BUFF_POS(length))
+
+static void SHA_FlushLocalBuffer_l(const u32 *buff);
+static int  SHA_BusyWait_l(void);
+static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type);
+static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type);
+static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block);
+static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block);
+static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block);
+
+static int SHA_Init(struct SHA_HANDLE_T *handleptr);
+static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type);
+static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len);
+static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest);
+static int SHA_Reset(void);
+static int SHA_Power(bool on);
+#ifdef SHA_PRINT
+static void SHA_PrintRegs(void);
+static void SHA_PrintVersion(void);
+#endif
+
+static struct SHA_HANDLE_T sha_handle;
+
+/*----------------------------------------------------------------------------*/
+/* Checks if give function returns int error, and returns the error           */
+/* immediately after SHA disabling                                            */
+/*----------------------------------------------------------------------------*/
+int npcm_sha_check(int status)
+{
+	if (status != 0) {
+		SHA_Power(false);
+		return status;
+	}
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_sha_calc                                          */
+/*                                                                            */
+/* Parameters:      type - SHA module type                                    */
+/*                  inBuff  - Pointer to a buffer containing the data to      */
+/*                            be hashed                                       */
+/*                  len     - Length of the data to hash                      */
+/*                  hashDigest - Pointer to a buffer where the reseulting     */
+/*                               digest will be copied to                     */
+/*                                                                            */
+/* Returns:         0 on success or other int error code on error             */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine performs complete SHA calculation in one     */
+/*                  step                                                      */
+/*----------------------------------------------------------------------------*/
+int npcm_sha_calc(u8 type, const u8 *inbuff, u32 len, u8 *hashdigest)
+{
+	int status;
+	struct SHA_HANDLE_T handle;
+
+	SHA_Init(&handle);
+	SHA_Power(true);
+	SHA_Reset();
+	SHA_Start(&handle, type);
+	status = SHA_Update(&handle, inbuff, len);
+	npcm_sha_check(status);
+	status = SHA_Finish(&handle, hashdigest);
+	npcm_sha_check(status);
+	SHA_Power(false);
+
+	return 0;
+}
+
+/*
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr    A pointer to the input buffer
+ * @param bufleni    Byte length of input buffer
+ * @param out_addr   A pointer to the output buffer. When complete
+ *           32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ *           should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size chunk size for sha256
+ */
+void hw_sha256(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size)
+{
+	puts("\nhw_sha256 using BMC HW accelerator\t");
+	npcm_sha_calc(npcm_sha_type_sha2, (u8 *)in_addr, buflen, (u8 *)out_addr);
+}
+
+/*
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr    A pointer to the input buffer
+ * @param bufleni    Byte length of input buffer
+ * @param out_addr   A pointer to the output buffer. When complete
+ *           32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ *           should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size chunk_size for sha1
+ */
+void hw_sha1(const uchar *in_addr, uint buflen, uchar *out_addr, uint chunk_size)
+{
+	puts("\nhw_sha1 using BMC HW accelerator\t");
+	npcm_sha_calc(npcm_sha_type_sha1, (u8 *)in_addr, buflen, (u8 *)out_addr);
+}
+
+/*
+ * Create the context for sha progressive hashing using h/w acceleration
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctxp: Pointer to the pointer of the context for hashing
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_init(struct hash_algo *algo, void **ctxp)
+{
+	const char *algo_name1 = "sha1";
+	const char *algo_name2 = "sha256";
+
+	SHA_Init(&sha_handle);
+	SHA_Power(true);
+	SHA_Reset();
+	if (!strcmp(algo_name1, algo->name))
+		return SHA_Start(&sha_handle, npcm_sha_type_sha1);
+	else if (!strcmp(algo_name2, algo->name))
+		return SHA_Start(&sha_handle, npcm_sha_type_sha2);
+	else
+		return -EPROTO;
+}
+
+/*
+ * Update buffer for sha progressive hashing using h/w acceleration
+ *
+ * The context is freed by this function if an error occurs.
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctx: Pointer to the context for hashing
+ * @buf: Pointer to the buffer being hashed
+ * @size: Size of the buffer being hashed
+ * @is_last: 1 if this is the last update; 0 otherwise
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
+		  unsigned int size, int is_last)
+{
+	return SHA_Update(&sha_handle, buf, size);
+}
+
+/*
+ * Copy sha hash result at destination location
+ *
+ * The context is freed after completion of hash operation or after an error.
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctx: Pointer to the context for hashing
+ * @dest_buf: Pointer to the destination buffer where hash is to be copied
+ * @size: Size of the buffer being hashed
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, int size)
+{
+	int status;
+
+	status = SHA_Finish(&sha_handle, dest_buf);
+	npcm_sha_check(status);
+	return SHA_Power(false);
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_Init                                                  */
+/*                                                                            */
+/* Parameters:      handlePtr - SHA processing handle pointer                 */
+/* Returns:         0 on success or other int error code on error.            */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine initialize the SHA module                    */
+/*----------------------------------------------------------------------------*/
+static int SHA_Init(struct SHA_HANDLE_T *handleptr)
+{
+	handleptr->active = false;
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_Start                                                 */
+/*                                                                            */
+/* Parameters:      handlePtr   - SHA processing handle pointer               */
+/*                  type        - SHA module type                             */
+/*                                                                            */
+/* Returns:         0 on success or other int error code on error.            */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine start a single SHA process                   */
+/*----------------------------------------------------------------------------*/
+static int SHA_Start(struct SHA_HANDLE_T *handleptr, u8 type)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+
+	// Initialize handle
+	handleptr->length0 = 0;
+	handleptr->length1 = 0;
+	handleptr->type = type;
+	handleptr->active = true;
+
+	// Set SHA type
+	writeb(handleptr->type & HASH_CFG_SHA1_SHA2, &regs->hash_cfg);
+
+	// Reset SHA hardware
+	SHA_Reset();
+
+	/* The handlePtr->hv is initialized with the correct IV as the SHA engine
+	 * automatically fill the HASH_DIG_Hn registers according to SHA spec
+	 * (following SHA_RST assertion)
+	 */
+	SHA_GetShaDigest_l((u8 *)handleptr->hv, type);
+
+	// Init block with zeros
+	memset(handleptr->block, 0, sizeof(handleptr->block));
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_Update                                                */
+/*                                                                            */
+/* Parameters:      handlePtr - SHA processing handle pointer                 */
+/*                  buffer    - Pointer to the data that will be added to     */
+/*                              the hash calculation                          */
+/*                  len -      Length of data to add to SHA calculation       */
+/*                                                                            */
+/*                                                                            */
+/* Returns:         0 on success or other int error code on error             */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine adds data to previously started SHA          */
+/*                  calculation                                               */
+/*----------------------------------------------------------------------------*/
+static int SHA_Update(struct SHA_HANDLE_T *handleptr, const u8 *buffer, u32 len)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+	u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)];
+	u32 bufferlen = len;
+	u16 pos = 0;
+	u8 *blockptr;
+	int status;
+
+	// Error check
+	if (!handleptr->active)
+		return -EPROTO;
+
+	// Wait till SHA is not busy
+	status = SHA_BusyWait_l();
+	npcm_sha_check(status);
+
+	// Set SHA type
+	writeb(handleptr->type & HASH_CFG_SHA1_SHA2, &regs->hash_cfg);
+
+	// Write SHA latest digest into SHA module
+	SHA_SetShaDigest_l(handleptr->hv, handleptr->type);
+
+	// Set number of unhashed bytes which remained from last update
+	pos = SHA_BUFF_POS(handleptr->length0);
+
+	// Copy unhashed bytes which remained from last update to secrun buffer
+	SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer);
+
+	while (len) {
+		// Wait for the hardware to be available (in case we are hashing)
+		status = SHA_BusyWait_l();
+		npcm_sha_check(status);
+
+		// Move as much bytes  as we can into the secrun buffer
+		bufferlen = min(len, SHA_BUFF_FREE(handleptr->length0));
+
+		// Copy current given buffer to the secrun buffer
+		SHA_SetBlock_l((u8 *)buffer, bufferlen, pos, localbuffer);
+
+		// Update size of hashed bytes
+		handleptr->length0 += bufferlen;
+
+		if (handleptr->length0 < bufferlen)
+			handleptr->length1++;
+
+		// Update length of data left to digest
+		len -= bufferlen;
+
+		// Update given buffer pointer
+		buffer += bufferlen;
+
+		// If secrun buffer is full
+		if (SHA_BUFF_POS(handleptr->length0) == 0) {
+			/* We just filled up the buffer perfectly, so let it hash (we'll
+			 * unload the hash only when we are done with all hashing)
+			 */
+			SHA_FlushLocalBuffer_l(localbuffer);
+
+			pos = 0;
+			bufferlen = 0;
+		}
+	}
+
+	// Wait till SHA is not busy
+	status = SHA_BusyWait_l();
+	npcm_sha_check(status);
+
+	/* Copy unhashed bytes from given buffer to handle block for next update/finish */
+	blockptr = (u8 *)handleptr->block;
+	while (bufferlen)
+		blockptr[--bufferlen + pos] = *(--buffer);
+
+	// Save SHA current digest
+	SHA_GetShaDigest_l((u8 *)handleptr->hv, handleptr->type);
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_Finish                                                */
+/*                                                                            */
+/* Parameters:      handlePtr  - SHA processing handle pointer                */
+/*                  hashDigest - Pointer to a buffer where the final digest   */
+/*                               will be copied to                            */
+/*                                                                            */
+/* Returns:         0 on success or other int error code on error             */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine finish SHA calculation and get               */
+/*                  the resulting SHA digest                                  */
+/*----------------------------------------------------------------------------*/
+static int SHA_Finish(struct SHA_HANDLE_T *handleptr, u8 *hashdigest)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+	u32 localbuffer[SHA_SECRUN_BUFF_SIZE / sizeof(u32)];
+	const u8 lastbyte = SHA_DATA_LAST_BYTE;
+	u16 pos;
+	int status;
+
+	// Error check
+	if (!handleptr->active)
+		return -EPROTO;
+
+	// Set SHA type
+	writeb(handleptr->type & HASH_CFG_SHA1_SHA2, &regs->hash_cfg);
+
+	// Wait till SHA is not busy
+	status = SHA_BusyWait_l();
+	npcm_sha_check(status);
+
+	// Finish off the current buffer with the SHA spec'ed padding
+	pos = SHA_BUFF_POS(handleptr->length0);
+
+	// Init SHA digest
+	SHA_SetShaDigest_l(handleptr->hv, handleptr->type);
+
+	// Load data into secrun buffer
+	SHA_SetBlock_l((u8 *)handleptr->block, pos, 0, localbuffer);
+
+	// Set data last byte as in SHA algorithm spec
+	SHA_SetBlock_l(&lastbyte, 1, pos++, localbuffer);
+
+	// If the remainder of data is longer then one block
+	if (pos > (SHA_BLOCK_LENGTH - 8)) {
+		/* The length will be in the next block Pad the rest of the last block with 0's */
+		SHA_ClearBlock_l((SHA_BLOCK_LENGTH - pos), pos, localbuffer);
+
+		// Hash the current block
+		SHA_FlushLocalBuffer_l(localbuffer);
+
+		pos = 0;
+
+		// Wait till SHA is not busy
+		status = SHA_BusyWait_l();
+		npcm_sha_check(status);
+	}
+
+	// Pad the rest of the last block with 0's except for the last 8-3 bytes
+	SHA_ClearBlock_l((SHA_BLOCK_LENGTH - (8 - 3)) - pos, pos, localbuffer);
+
+	/* The last 8-3 bytes are set to the bit-length of the message in big-endian form */
+	SHA_SetLength32_l(handleptr, localbuffer);
+
+	// Hash all that, and save the hash for the caller
+	SHA_FlushLocalBuffer_l(localbuffer);
+
+	// Wait till SHA is not busy
+	status = SHA_BusyWait_l();
+	npcm_sha_check(status);
+
+	// Save SHA final digest into given buffer
+	SHA_GetShaDigest_l(hashdigest, handleptr->type);
+
+	// Free handle
+	handleptr->active = false;
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_Reset                                                 */
+/*                                                                            */
+/* Parameters:      none                                                      */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine reset SHA module                             */
+/*----------------------------------------------------------------------------*/
+static int SHA_Reset(void)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+
+	writel(readl(&regs->hash_ctr_sts) | HASH_CTR_STS_SHA_RST, &regs->hash_ctr_sts);
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_Power                                                 */
+/*                                                                            */
+/* Parameters:      on - true enable the module, false disable the module     */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine set SHA module power on/off                  */
+/*----------------------------------------------------------------------------*/
+static int SHA_Power(bool on)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+	u8 hash_sts;
+
+	hash_sts = readb(&regs->hash_ctr_sts) & ~HASH_CTR_STS_SHA_EN;
+	writeb(hash_sts | (on & HASH_CTR_STS_SHA_EN), &regs->hash_ctr_sts);
+
+	return 0;
+}
+
+#ifdef SHA_PRINT
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_PrintRegs                                             */
+/*                                                                            */
+/* Parameters:      none                                                      */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine prints the module registers                  */
+/*----------------------------------------------------------------------------*/
+static void SHA_PrintRegs(void)
+{
+#ifdef SHA_DEBUG_MODULE
+	struct npcm_sha_regs *regs = sha_priv->regs;
+#endif
+	unsigned int i;
+
+	sha_print("/*--------------*/\n");
+	sha_print("/*     SHA      */\n");
+	sha_print("/*--------------*/\n\n");
+
+	sha_print("HASH_CTR_STS    = 0x%02X\n", readb(&regs->hash_ctr_sts));
+	sha_print("HASH_CFG        = 0x%02X\n", readb(&regs->hash_cfg));
+
+	for (i = 0; i < HASH_DIG_H_NUM; i++)
+		sha_print("HASH_DIG_H%d     = 0x%08X\n", i, readl(&regs->hash_dig[i]));
+
+	sha_print("HASH_VER         = 0x%08X\n", readb(&regs->hash_ver));
+
+	sha_print("\n");
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_PrintVersion                                          */
+/*                                                                            */
+/* Parameters:      none                                                      */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine prints the module version                    */
+/*----------------------------------------------------------------------------*/
+static void SHA_PrintVersion(void)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+
+	printf("SHA MODULE VER  = %d\n", readb(&regs->hash_ver));
+}
+#endif
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_sha_selftest                                      */
+/*                                                                            */
+/* Parameters:      type - SHA module type                                    */
+/* Returns:         0 on success or other int error code on error             */
+/* Side effects:                                                              */
+/* Description:                                                               */
+/*                  This routine performs various tests on the SHA HW and SW  */
+/*----------------------------------------------------------------------------*/
+int npcm_sha_selftest(u8 type)
+{
+	int status;
+	struct SHA_HANDLE_T handle;
+	u8 hashdigest[max(SHA_1_HASH_LENGTH, SHA_2_HASH_LENGTH)];
+	u16 i, j;
+
+	/*------------------------------------------------------------------------*/
+	/* SHA1 tests info                                                        */
+	/*------------------------------------------------------------------------*/
+
+	static const u8 sha1selftestbuff[SHA1_NUM_OF_SELF_TESTS][94] = {
+		{"abc"},
+		{"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"},
+		{"0123456789012345678901234567890123456789012345678901234567890123"},
+		{0x30, 0x5c, 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b,
+		 0x0e, 0x03, 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a,
+		 0x01, 0x0c, 0x04, 0x14, 0xe1, 0xb6, 0x93, 0xfe, 0x33, 0x43, 0xc1, 0x20,
+		 0x5d, 0x4b, 0xaa, 0xb8, 0x63, 0xfb, 0xcf, 0x6c, 0x46, 0x1e, 0x88, 0x04,
+		 0x30, 0x2c, 0x02, 0x01, 0x00, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e, 0x03,
+		 0x02, 0x1a, 0x05, 0x00, 0x30, 0x06, 0x06, 0x04, 0x67, 0x2a, 0x01, 0x0c,
+		 0x04, 0x14, 0x13, 0xc1, 0x0c, 0xfc, 0xc8, 0x92, 0xd7, 0xde, 0x07, 0x1c,
+		 0x40, 0xde, 0x4f, 0xcd, 0x07, 0x5b, 0x68, 0x20, 0x5a, 0x6c}
+	};
+
+	static const u8 sha1selftestbufflen[SHA1_NUM_OF_SELF_TESTS] = {
+		3, 56, 64, 94
+	};
+
+	static const u8 sha1selftestexpres[SHA1_NUM_OF_SELF_TESTS][SHA_1_HASH_LENGTH] = {
+		{0xA9, 0x99, 0x3E, 0x36,
+		 0x47, 0x06, 0x81, 0x6A,
+		 0xBA, 0x3E, 0x25, 0x71,
+		 0x78, 0x50, 0xC2, 0x6C,
+		 0x9C, 0xD0, 0xD8, 0x9D},
+		{0x84, 0x98, 0x3E, 0x44,
+		 0x1C, 0x3B, 0xD2, 0x6E,
+		 0xBA, 0xAE, 0x4A, 0xA1,
+		 0xF9, 0x51, 0x29, 0xE5,
+		 0xE5, 0x46, 0x70, 0xF1},
+		{0xCF, 0x08, 0x00, 0xF7,
+		 0x64, 0x4A, 0xCE, 0x3C,
+		 0xB4, 0xC3, 0xFA, 0x33,
+		 0x38, 0x8D, 0x3B, 0xA0,
+		 0xEA, 0x3C, 0x8B, 0x6E},
+		{0xc9, 0x84, 0x45, 0xc8,
+		 0x64, 0x04, 0xb1, 0xe3,
+		 0x3c, 0x6b, 0x0a, 0x8c,
+		 0x8b, 0x80, 0x94, 0xfc,
+		 0xf3, 0xc9, 0x98, 0xab}
+	};
+
+	/*------------------------------------------------------------------------*/
+	/* SHA2 tests info                                                        */
+	/*------------------------------------------------------------------------*/
+
+	static const u8 sha2selftestbuff[SHA2_NUM_OF_SELF_TESTS][100] = {
+		{ "abc" },
+		{ "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" },
+		{'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a',
+		 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a', 'a'}
+	};
+
+	static const u8 sha2selftestbufflen[SHA2_NUM_OF_SELF_TESTS] = {
+		3, 56, 100
+	};
+
+	static const u8 sha2selftestexpres[SHA2_NUM_OF_SELF_TESTS][SHA_2_HASH_LENGTH] = {
+		/*
+		 * SHA-256 test vectors
+		 */
+		{ 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA,
+		  0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23,
+		  0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C,
+		  0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD },
+		{ 0x24, 0x8D, 0x6A, 0x61, 0xD2, 0x06, 0x38, 0xB8,
+		  0xE5, 0xC0, 0x26, 0x93, 0x0C, 0x3E, 0x60, 0x39,
+		  0xA3, 0x3C, 0xE4, 0x59, 0x64, 0xFF, 0x21, 0x67,
+		  0xF6, 0xEC, 0xED, 0xD4, 0x19, 0xDB, 0x06, 0xC1 },
+		{ 0xCD, 0xC7, 0x6E, 0x5C, 0x99, 0x14, 0xFB, 0x92,
+		  0x81, 0xA1, 0xC7, 0xE2, 0x84, 0xD7, 0x3E, 0x67,
+		  0xF1, 0x80, 0x9A, 0x48, 0xA4, 0x97, 0x20, 0x0E,
+		  0x04, 0x6D, 0x39, 0xCC, 0xC7, 0x11, 0x2C, 0xD0 },
+	};
+
+	if (type == npcm_sha_type_sha1) {
+		/*--------------------------------------------------------------------*/
+		/* SHA 1 TESTS                                                        */
+		/*--------------------------------------------------------------------*/
+		for (i = 0; i < SHA1_NUM_OF_SELF_TESTS; i++) {
+			if (i != 3) {
+				status = npcm_sha_calc(npcm_sha_type_sha1, sha1selftestbuff[i], sha1selftestbufflen[i], hashdigest);
+				npcm_sha_check(status);
+			} else {
+				SHA_Power(true);
+				SHA_Reset();
+				status = SHA_Start(&handle, npcm_sha_type_sha1);
+				npcm_sha_check(status);
+				status = SHA_Update(&handle, sha1selftestbuff[i], 73);
+				npcm_sha_check(status);
+				status = SHA_Update(&handle, &sha1selftestbuff[i][73], sha1selftestbufflen[i] - 73);
+				npcm_sha_check(status);
+				status = SHA_Finish(&handle, hashdigest);
+				npcm_sha_check(status);
+				SHA_Power(false);
+			}
+
+			if (memcmp(hashdigest, sha1selftestexpres[i], SHA_1_HASH_LENGTH))
+				return -1;
+		}
+
+	} else {
+		/*--------------------------------------------------------------------*/
+		/* SHA 2 TESTS                                                        */
+		/*--------------------------------------------------------------------*/
+		for (i = 0; i < SHA2_NUM_OF_SELF_TESTS; i++) {
+			SHA_Power(true);
+			SHA_Reset();
+			status = SHA_Start(&handle, npcm_sha_type_sha2);
+			npcm_sha_check(status);
+			if (i == 2) {
+				for (j = 0; j < 10000; j++) { //not working
+					status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]);
+					npcm_sha_check(status);
+				}
+			} else {
+				status = SHA_Update(&handle, sha2selftestbuff[i], sha2selftestbufflen[i]);
+				npcm_sha_check(status);
+			}
+
+			status = SHA_Finish(&handle, hashdigest);
+			npcm_sha_check(status);
+			SHA_Power(false);
+			if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH))
+				return -1;
+
+			npcm_sha_calc(npcm_sha_type_sha2, sha2selftestbuff[i], sha2selftestbufflen[i], hashdigest);
+			if (memcmp(hashdigest, sha2selftestexpres[i], SHA_2_HASH_LENGTH))
+				return -1;
+		}
+	}
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_FlushLocalBuffer_l                                    */
+/*                                                                            */
+/* Parameters:                                                                */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     This routine flush secrun buffer to SHA module            */
+/*----------------------------------------------------------------------------*/
+static void SHA_FlushLocalBuffer_l(const u32 *buff)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+	u32 i;
+
+	for (i = 0; i < (SHA_BLOCK_LENGTH / sizeof(u32)); i++)
+		writel(buff[i], &regs->hash_data_in);
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_BusyWait_l                                            */
+/*                                                                            */
+/* Parameters:                                                                */
+/* Returns:         0 if no error was found or DEFS_STATUS_ERROR otherwise    */
+/* Side effects:                                                              */
+/* Description:     This routine wait for SHA unit to no longer be busy       */
+/*----------------------------------------------------------------------------*/
+static int SHA_BusyWait_l(void)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+	u32 timeout = SHA_TIMEOUT;
+
+	do {
+		if (timeout-- == 0)
+			return -ETIMEDOUT;
+	} while ((readb(&regs->hash_ctr_sts) & HASH_CTR_STS_SHA_BUSY)
+						== HASH_CTR_STS_SHA_BUSY);
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_GetShaDigest_l                                        */
+/*                                                                            */
+/* Parameters:      hashDigest - buffer for the hash output.                  */
+/*                  type - SHA module type                                    */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     This routine copy the hash digest from the hardware       */
+/*                  and into given buffer (in ram)                            */
+/*----------------------------------------------------------------------------*/
+static void SHA_GetShaDigest_l(u8 *hashdigest, u8 type)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+	u16 j;
+	u8 len = SHA_HASH_LENGTH(type) / sizeof(u32);
+
+	// Copy Bytes from SHA module to given buffer
+	for (j = 0; j < len; j++)
+		((u32 *)hashdigest)[j] = readl(&regs->hash_dig[j]);
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_SetShaDigest_l                                        */
+/*                                                                            */
+/* Parameters:      hashDigest - input buffer to set as hash digest           */
+/*                  type - SHA module type                                    */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     This routine set the hash digest in the hardware from     */
+/*                  a given buffer (in ram)                                   */
+/*----------------------------------------------------------------------------*/
+static void SHA_SetShaDigest_l(const u32 *hashdigest, u8 type)
+{
+	struct npcm_sha_regs *regs = sha_priv->regs;
+	u16 j;
+	u8 len = SHA_HASH_LENGTH(type) / sizeof(u32);
+
+	// Copy Bytes from given buffer to SHA module
+	for (j = 0; j < len; j++)
+		writel(hashdigest[j], &regs->hash_dig[j]);
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_SetBlock_l                                            */
+/*                                                                            */
+/* Parameters:      data        - data to copy                                */
+/*                  len         - size of data                                */
+/*                  position    - byte offset into the block at which data    */
+/*                                should be placed                            */
+/*                  block       - block buffer                                */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     This routine load bytes into block buffer                 */
+/*----------------------------------------------------------------------------*/
+static void SHA_SetBlock_l(const u8 *data, u32 len, u16 position, u32 *block)
+{
+	u8 *dest = (u8 *)block;
+
+	memcpy(dest + position, data, len);
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_SetBlock_l                                            */
+/*                                                                            */
+/* Parameters:                                                                */
+/*                  len - size of data                                        */
+/*                  position - byte offset into the block at which data       */
+/*                             should be placed                               */
+/*                  block - block buffer                                      */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     This routine load zero's into the block buffer            */
+/*----------------------------------------------------------------------------*/
+static void SHA_ClearBlock_l(u16 len, u16 position, u32 *block)
+{
+	u8 *dest = (u8 *)block;
+
+	memset(dest + position, 0, len);
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        SHA_SetLength32_l                                         */
+/*                                                                            */
+/* Parameters:                                                                */
+/*                  handlePtr  -   SHA processing handle pointer              */
+/*                  block - block buffer                                      */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     This routine set the length of the hash's data            */
+/*                  len is the 32-bit byte length of the message              */
+/*lint -efunc(734,SHA_SetLength32_l) Supperess loss of percision lint warning */
+/*----------------------------------------------------------------------------*/
+static void SHA_SetLength32_l(struct SHA_HANDLE_T *handleptr, u32 *block)
+{
+	u16 *secrunbufferswappedptr = (u16 *)(void *)(block);
+
+	secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 1] = (u16)
+	((handleptr->length0 << 3) << 8) | ((u16)(handleptr->length0 << 3) >> 8);
+	secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 2] = (u16)
+	((handleptr->length0 >> (16 - 3)) >> 8) | ((u16)(handleptr->length0 >> (16 - 3)) << 8);
+	secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 3] = (u16)
+	((handleptr->length1 << 3) << 8) | ((u16)(handleptr->length1 << 3) >> 8);
+	secrunbufferswappedptr[(SHA_BLOCK_LENGTH / sizeof(u16)) - 4] = (u16)
+	((handleptr->length1 >> (16 - 3)) >> 8) | ((u16)(handleptr->length1 >> (16 - 3)) << 8);
+}
+
+static int npcm_sha_bind(struct udevice *dev)
+{
+	sha_priv = calloc(1, sizeof(struct npcm_sha_priv));
+	if (!sha_priv)
+		return -ENOMEM;
+
+	sha_priv->regs = dev_remap_addr_index(dev, 0);
+	if (!sha_priv->regs) {
+		printf("Cannot find sha reg address, binding failed\n");
+		return -EINVAL;
+	}
+
+	printf("SHA: NPCM SHA module bind OK\n");
+
+	return 0;
+}
+
+static const struct udevice_id npcm_sha_ids[] = {
+	{ .compatible = "nuvoton,npcm845-sha" },
+	{ .compatible = "nuvoton,npcm750-sha" },
+	{ }
+};
+
+U_BOOT_DRIVER(npcm_sha) = {
+	.name = "npcm_sha",
+	.id = UCLASS_MISC,
+	.of_match = npcm_sha_ids,
+	.priv_auto = sizeof(struct npcm_sha_priv),
+	.bind = npcm_sha_bind,
+};
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
index eec9d48..738b788 100644
--- a/drivers/ddr/Kconfig
+++ b/drivers/ddr/Kconfig
@@ -30,5 +30,10 @@ config DDR_SPD
 	  For memory controllers that can utilize it, add enable support for
 	  using the JEDEC SDP standard.
 
+config SYS_SPD_BUS_NUM
+	int "I2C bus number for DDR SPD"
+	depends on DDR_SPD || SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY
+	default 0
+
 source "drivers/ddr/altera/Kconfig"
 source "drivers/ddr/imx/Kconfig"
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 5925fe9..d93ed8d 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -10,6 +10,12 @@ config SYS_FSL_MMDC
 	help
 	  Select Freescale Multi Mode DDR controller (MMDC).
 
+config SYS_FSL_DDR_EMU
+	bool
+	help
+	  Specify emulator support for DDR. Some DDR features such as deskew
+	  training are not available.
+
 if SYS_FSL_DDR || SYS_FSL_MMDC
 
 config SYS_FSL_DDR_BE
@@ -169,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER
 	  Use the DDR controller to auto initialize memory.  If not enabled,
 	  the DMA controller is responsible for doing this.
 
+config SYS_DDR_RAW_TIMING
+	bool "Get DDR timing information from something other than SPD"
+	help
+	  This is common with soldered DDR chips onboard without SPD. DDR raw
+	  timing parameters are extracted from datasheet and hard-coded into
+	  header files or board specific files.
+
 endif
 
 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
@@ -263,6 +276,20 @@ config SYS_OR7_PRELIM
 	depends on SYS_BR7_PRELIM_BOOL
 endmenu
 
+if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
+	TARGET_P1020RDB_PD || TARGET_P2020RDB
+
+config COMMON_INIT_DDR
+	bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
+
+config SPL_COMMON_INIT_DDR
+	bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
+
+config TPL_COMMON_INIT_DDR
+	bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
+
+endif
+
 config SYS_FSL_ERRATUM_A008378
 	bool
 
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 6a4f4f1..56f3487 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -7,3 +7,4 @@ k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
 k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
 k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
 k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
+k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
diff --git a/drivers/dma/ti/k3-psil-am62.c b/drivers/dma/ti/k3-psil-am62.c
new file mode 100644
index 0000000..9527da4
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am62.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt)		\
+	{							\
+		.thread_id = x,					\
+		.ep_config = {					\
+			.ep_type = PSIL_EP_NATIVE,		\
+			.pkt_mode = 1,				\
+			.needs_epib = 1,			\
+			.psd_size = 16,				\
+			.mapped_channel_id = ch,		\
+			.flow_start = flow_base,		\
+			.flow_num = flow_cnt,			\
+			.default_flow_id = flow_base,		\
+		},						\
+	}
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am62_src_ep_map[] = {
+	/* CPSW3G */
+	PSIL_ETHERNET(0x4600, 19, 19, 16),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am62_dst_ep_map[] = {
+	/* CPSW3G */
+	PSIL_ETHERNET(0xc600, 19, 19, 8),
+	PSIL_ETHERNET(0xc601, 20, 27, 8),
+	PSIL_ETHERNET(0xc602, 21, 35, 8),
+	PSIL_ETHERNET(0xc603, 22, 43, 8),
+	PSIL_ETHERNET(0xc604, 23, 51, 8),
+	PSIL_ETHERNET(0xc605, 24, 59, 8),
+	PSIL_ETHERNET(0xc606, 25, 67, 8),
+	PSIL_ETHERNET(0xc607, 26, 75, 8),
+};
+
+struct psil_ep_map am62_ep_map = {
+	.name = "am62",
+	.src = am62_src_ep_map,
+	.src_count = ARRAY_SIZE(am62_src_ep_map),
+	.dst = am62_dst_ep_map,
+	.dst_count = ARRAY_SIZE(am62_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index 77acaf2..28078c6 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -41,5 +41,6 @@ extern struct psil_ep_map am654_ep_map;
 extern struct psil_ep_map j721e_ep_map;
 extern struct psil_ep_map j721s2_ep_map;
 extern struct psil_ep_map am64_ep_map;
+extern struct psil_ep_map am62_ep_map;
 
 #endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index 8b2129d..f1330bf 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -24,6 +24,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
 			soc_ep_map = &j721s2_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
 			soc_ep_map = &am64_ep_map;
+		else if (IS_ENABLED(CONFIG_SOC_K3_AM625))
+			soc_ep_map = &am62_ep_map;
 	}
 
 	if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index ef958b3..eae1c8d 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -3,7 +3,7 @@ config FIRMWARE
 
 config SPL_FIRMWARE
 	bool "Enable Firmware driver support in SPL"
-	depends on FIRMWARE
+	depends on FIRMWARE && SPL
 
 config SPL_ARM_PSCI_FW
 	bool
@@ -37,4 +37,12 @@ config ZYNQMP_FIRMWARE
 	  Say yes to enable ZynqMP firmware interface driver.
 	  If in doubt, say N.
 
+config ARM_SMCCC_FEATURES
+	bool "Arm SMCCC features discovery"
+	depends on ARM_PSCI_FW
+	help
+	  Discover Arm SMCCC features for which a U-Boot driver is defined. When enabled,
+	  the PSCI driver is always probed and binds dirvers registered to the Arm SMCCC
+	  services if any and reported as supported by the SMCCC firmware.
+
 source "drivers/firmware/scmi/Kconfig"
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 0f0d2b0..b0cd647 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -26,7 +26,7 @@
 struct zynqmp_power {
 	struct mbox_chan tx_chan;
 	struct mbox_chan rx_chan;
-} zynqmp_power;
+} zynqmp_power = {};
 
 #define NODE_ID_LOCATION	5
 
@@ -79,6 +79,20 @@ int zynqmp_pmufw_node(u32 id)
 	return 0;
 }
 
+static int do_pm_probe(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
+					  DM_DRIVER_GET(zynqmp_power),
+					  &dev);
+	if (ret)
+		debug("%s: Probing device failed: %d\n", __func__, ret);
+
+	return ret;
+}
+
 static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
 {
 	struct zynqmp_ipi_msg msg;
@@ -92,8 +106,11 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
 	    res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
 		return -EINVAL;
 
-	if (!(zynqmp_power.tx_chan.dev) || !(&zynqmp_power.rx_chan.dev))
-		return -EINVAL;
+	if (!(zynqmp_power.tx_chan.dev) || !(zynqmp_power.rx_chan.dev)) {
+		ret = do_pm_probe();
+		if (ret)
+			return ret;
+	}
 
 	debug("%s, Sending IPI message with ID: 0x%0x\n", __func__, req[0]);
 	msg.buf = (u32 *)req;
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index 657e7eb..ef3e983 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -9,18 +9,20 @@
 #include <common.h>
 #include <command.h>
 #include <dm.h>
+#include <efi_loader.h>
 #include <irq_func.h>
+#include <linker_lists.h>
 #include <log.h>
-#include <dm/lists.h>
-#include <efi_loader.h>
 #include <sysreset.h>
-#include <linux/delay.h>
-#include <linux/libfdt.h>
+#include <asm/system.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
 #include <linux/arm-smccc.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/libfdt.h>
 #include <linux/printk.h>
 #include <linux/psci.h>
-#include <asm/system.h>
 
 #define DRIVER_NAME "psci"
 
@@ -95,6 +97,76 @@ static bool psci_is_system_reset2_supported(void)
 	return false;
 }
 
+static void smccc_invoke_hvc(unsigned long a0, unsigned long a1,
+			     unsigned long a2, unsigned long a3,
+			     unsigned long a4, unsigned long a5,
+			     unsigned long a6, unsigned long a7,
+			     struct arm_smccc_res *res)
+{
+	arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res);
+}
+
+static void smccc_invoke_smc(unsigned long a0, unsigned long a1,
+			     unsigned long a2, unsigned long a3,
+			     unsigned long a4, unsigned long a5,
+			     unsigned long a6, unsigned long a7,
+			     struct arm_smccc_res *res)
+{
+	arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res);
+}
+
+static int bind_smccc_features(struct udevice *dev, int psci_method)
+{
+	struct psci_plat_data *pdata = dev_get_plat(dev);
+	struct arm_smccc_feature *feature;
+	size_t feature_cnt, n;
+
+	if (!IS_ENABLED(CONFIG_ARM_SMCCC_FEATURES))
+		return 0;
+
+	/*
+	 * SMCCC features discovery invoke SMCCC standard function ID
+	 * ARM_SMCCC_ARCH_FEATURES but this sequence requires that this
+	 * standard ARM_SMCCC_ARCH_FEATURES function ID itself is supported.
+	 * It is queried here with invoking PSCI_FEATURES known available
+	 * from PSCI 1.0.
+	 */
+	if (!device_is_compatible(dev, "arm,psci-1.0") ||
+	    PSCI_VERSION_MAJOR(psci_0_2_get_version()) == 0)
+		return 0;
+
+	if (request_psci_features(ARM_SMCCC_ARCH_FEATURES) ==
+	    PSCI_RET_NOT_SUPPORTED)
+		return 0;
+
+	if (psci_method == PSCI_METHOD_HVC)
+		pdata->invoke_fn = smccc_invoke_hvc;
+	else
+		pdata->invoke_fn = smccc_invoke_smc;
+
+	feature_cnt = ll_entry_count(struct arm_smccc_feature, arm_smccc_feature);
+	feature = ll_entry_start(struct arm_smccc_feature, arm_smccc_feature);
+
+	for (n = 0; n < feature_cnt; n++, feature++) {
+		const char *drv_name = feature->driver_name;
+		struct udevice *dev2;
+		int ret;
+
+		if (!feature->is_supported || !feature->is_supported(pdata->invoke_fn))
+			continue;
+
+		ret = device_bind_driver(dev, drv_name, drv_name, &dev2);
+		if (ret) {
+			pr_warn("%s was not bound: %d, ignore\n", drv_name, ret);
+			continue;
+		}
+
+		dev_set_parent_plat(dev2, dev_get_plat(dev));
+	}
+
+	return 0;
+}
+
 static int psci_bind(struct udevice *dev)
 {
 	/* No SYSTEM_RESET support for PSCI 0.1 */
@@ -109,6 +181,10 @@ static int psci_bind(struct udevice *dev)
 			pr_debug("PSCI System Reset was not bound.\n");
 	}
 
+	/* From PSCI v1.0 onward we can discover services through ARM_SMCCC_FEATURE */
+	if (IS_ENABLED(CONFIG_ARM_SMCCC_FEATURES) && device_is_compatible(dev, "arm,psci-1.0"))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
 	return 0;
 }
 
@@ -136,7 +212,7 @@ static int psci_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	return 0;
+	return bind_smccc_features(dev, psci_method);
 }
 
 /**
@@ -240,4 +316,7 @@ U_BOOT_DRIVER(psci) = {
 	.of_match = psci_of_match,
 	.bind = psci_bind,
 	.probe = psci_probe,
+#ifdef CONFIG_ARM_SMCCC_FEATURES
+	.plat_auto = sizeof(struct psci_plat_data),
+#endif
 };
diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c
index 8e4af0c..3efdab9 100644
--- a/drivers/firmware/scmi/mailbox_agent.c
+++ b/drivers/firmware/scmi/mailbox_agent.c
@@ -31,9 +31,19 @@ struct scmi_mbox_channel {
 	ulong timeout_us;
 };
 
-static int scmi_mbox_process_msg(struct udevice *dev, struct scmi_msg *msg)
+/**
+ * struct scmi_channel - Channel instance referenced in SCMI drivers
+ * @ref: Reference to local channel instance
+ **/
+struct scmi_channel {
+	struct scmi_mbox_channel ref;
+};
+
+static int scmi_mbox_process_msg(struct udevice *dev,
+				 struct scmi_channel *channel,
+				 struct scmi_msg *msg)
 {
-	struct scmi_mbox_channel *chan = dev_get_plat(dev);
+	struct scmi_mbox_channel *chan = &channel->ref;
 	int ret;
 
 	ret = scmi_write_msg_to_smt(dev, &chan->smt, msg);
@@ -62,13 +72,10 @@ out:
 	return ret;
 }
 
-int scmi_mbox_of_to_plat(struct udevice *dev)
+static int setup_channel(struct udevice *dev, struct scmi_mbox_channel *chan)
 {
-	struct scmi_mbox_channel *chan = dev_get_plat(dev);
 	int ret;
 
-	chan->timeout_us = TIMEOUT_US_10MS;
-
 	ret = mbox_get_by_index(dev, 0, &chan->mbox);
 	if (ret) {
 		dev_err(dev, "Failed to find mailbox: %d\n", ret);
@@ -76,10 +83,51 @@ int scmi_mbox_of_to_plat(struct udevice *dev)
 	}
 
 	ret = scmi_dt_get_smt_buffer(dev, &chan->smt);
-	if (ret)
+	if (ret) {
 		dev_err(dev, "Failed to get shm resources: %d\n", ret);
+		return ret;
+	}
 
-	return ret;
+	chan->timeout_us = TIMEOUT_US_10MS;
+
+	return 0;
+}
+
+static int scmi_mbox_get_channel(struct udevice *dev,
+				 struct scmi_channel **channel)
+{
+	struct scmi_mbox_channel *base_chan = dev_get_plat(dev->parent);
+	struct scmi_mbox_channel *chan;
+	int ret;
+
+	if (!dev_read_prop(dev, "shmem", NULL)) {
+		/* Uses agent base channel */
+		*channel = container_of(base_chan, struct scmi_channel, ref);
+
+		return 0;
+	}
+
+	chan = calloc(1, sizeof(*chan));
+	if (!chan)
+		return -ENOMEM;
+
+	/* Setup a dedicated channel for the protocol */
+	ret = setup_channel(dev, chan);
+	if (ret) {
+		free(chan);
+		return ret;
+	}
+
+	*channel = (void *)chan;
+
+	return 0;
+}
+
+int scmi_mbox_of_to_plat(struct udevice *dev)
+{
+	struct scmi_mbox_channel *chan = dev_get_plat(dev);
+
+	return setup_channel(dev, chan);
 }
 
 static const struct udevice_id scmi_mbox_ids[] = {
@@ -88,6 +136,7 @@ static const struct udevice_id scmi_mbox_ids[] = {
 };
 
 static const struct scmi_agent_ops scmi_mbox_ops = {
+	.of_get_channel = scmi_mbox_get_channel,
 	.process_msg = scmi_mbox_process_msg,
 };
 
diff --git a/drivers/firmware/scmi/optee_agent.c b/drivers/firmware/scmi/optee_agent.c
index 1f26592..2b2b8c1 100644
--- a/drivers/firmware/scmi/optee_agent.c
+++ b/drivers/firmware/scmi/optee_agent.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2020-2021 Linaro Limited.
+ * Copyright (C) 2020-2022 Linaro Limited.
  */
 
 #define LOG_CATEGORY UCLASS_SCMI_AGENT
@@ -36,6 +36,14 @@ struct scmi_optee_channel {
 };
 
 /**
+ * struct scmi_channel - Channel instance referenced in SCMI drivers
+ * @ref: Reference to local channel instance
+ **/
+struct scmi_channel {
+	struct scmi_optee_channel ref;
+};
+
+/**
  * struct channel_session - Aggreates SCMI service session context references
  * @tee:		OP-TEE device to invoke
  * @tee_session:	OP-TEE session identifier
@@ -91,13 +99,27 @@ enum optee_smci_pta_cmd {
 	/*
 	 * PTA_SCMI_CMD_GET_CHANNEL - Get channel handle
 	 *
-	 * SCMI shm information are 0 if agent expects to use OP-TEE regular SHM
-	 *
 	 * [in]     value[0].a: Channel identifier
 	 * [out]    value[0].a: Returned channel handle
 	 * [in]     value[0].b: Requested capabilities mask (enum pta_scmi_caps)
 	 */
 	PTA_SCMI_CMD_GET_CHANNEL = 3,
+
+	/*
+	 * PTA_SCMI_CMD_PROCESS_MSG_CHANNEL - Process SCMI message in MSG
+	 * buffers pointed by memref parameters
+	 *
+	 * [in]     value[0].a: Channel handle
+	 * [in]     memref[1]: Message buffer (MSG header and SCMI payload)
+	 * [out]    memref[2]: Response buffer (MSG header and SCMI payload)
+	 *
+	 * Shared memories used for SCMI message/response are MSG buffers
+	 * referenced by param[1] and param[2]. MSG transport protocol
+	 * uses a 32bit header to carry SCMI meta-data (protocol ID and
+	 * protocol message ID) followed by the effective SCMI message
+	 * payload.
+	 */
+	PTA_SCMI_CMD_PROCESS_MSG_CHANNEL = 4,
 };
 
 /*
@@ -106,14 +128,22 @@ enum optee_smci_pta_cmd {
  * PTA_SCMI_CAPS_SMT_HEADER
  * When set, OP-TEE supports command using SMT header protocol (SCMI shmem) in
  * shared memory buffers to carry SCMI protocol synchronisation information.
+ *
+ * PTA_SCMI_CAPS_MSG_HEADER
+ * When set, OP-TEE supports command using MSG header protocol in an OP-TEE
+ * shared memory to carry SCMI protocol synchronisation information and SCMI
+ * message payload.
  */
 #define PTA_SCMI_CAPS_NONE		0
 #define PTA_SCMI_CAPS_SMT_HEADER	BIT(0)
+#define PTA_SCMI_CAPS_MSG_HEADER	BIT(1)
+#define PTA_SCMI_CAPS_MASK		(PTA_SCMI_CAPS_SMT_HEADER | \
+					 PTA_SCMI_CAPS_MSG_HEADER)
 
-static int open_channel(struct udevice *dev, struct channel_session *sess)
+static int open_channel(struct udevice *dev, struct scmi_optee_channel *chan,
+			struct channel_session *sess)
 {
 	const struct tee_optee_ta_uuid uuid = TA_SCMI_UUID;
-	struct scmi_optee_channel *chan = dev_get_plat(dev);
 	struct tee_open_session_arg sess_arg = { };
 	struct tee_invoke_arg cmd_arg = { };
 	struct tee_param param[1] = { };
@@ -139,7 +169,10 @@ static int open_channel(struct udevice *dev, struct channel_session *sess)
 
 	param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INOUT;
 	param[0].u.value.a = chan->channel_id;
-	param[0].u.value.b = PTA_SCMI_CAPS_SMT_HEADER;
+	if (chan->dyn_shm)
+		param[0].u.value.b = PTA_SCMI_CAPS_MSG_HEADER;
+	else
+		param[0].u.value.b = PTA_SCMI_CAPS_SMT_HEADER;
 
 	ret = tee_invoke_func(sess->tee, &cmd_arg, ARRAY_SIZE(param), param);
 	if (ret || cmd_arg.ret) {
@@ -162,45 +195,58 @@ static void close_channel(struct channel_session *sess)
 	tee_close_session(sess->tee, sess->tee_session);
 }
 
-static int invoke_cmd(struct udevice *dev, struct channel_session *sess,
-		      struct scmi_msg *msg)
+static int invoke_cmd(struct udevice *dev, struct scmi_optee_channel *chan,
+		      struct channel_session *sess, struct scmi_msg *msg)
 {
-	struct scmi_optee_channel *chan = dev_get_plat(dev);
 	struct tee_invoke_arg arg = { };
-	struct tee_param param[2] = { };
+	struct tee_param param[3] = { };
 	int ret;
 
-	scmi_write_msg_to_smt(dev, &chan->smt, msg);
-
 	arg.session = sess->tee_session;
 	param[0].attr = TEE_PARAM_ATTR_TYPE_VALUE_INPUT;
 	param[0].u.value.a = sess->channel_hdl;
 
-	if (chan->dyn_shm) {
-		arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE;
-		param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT;
+	if (sess->tee_shm) {
+		size_t in_size;
+
+		ret = scmi_msg_to_smt_msg(dev, &chan->smt, msg, &in_size);
+		if (ret < 0)
+			return ret;
+
+		arg.func = PTA_SCMI_CMD_PROCESS_MSG_CHANNEL;
+		param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT;
 		param[1].u.memref.shm = sess->tee_shm;
-		param[1].u.memref.size = SCMI_SHM_SIZE;
+		param[1].u.memref.size = in_size;
+		param[2].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT;
+		param[2].u.memref.shm = sess->tee_shm;
+		param[2].u.memref.size = sess->tee_shm->size;
 	} else {
 		arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL;
+		scmi_write_msg_to_smt(dev, &chan->smt, msg);
 	}
 
 	ret = tee_invoke_func(sess->tee, &arg, ARRAY_SIZE(param), param);
 	if (ret || arg.ret) {
 		if (!ret)
 			ret = -EPROTO;
+
+		return ret;
+	}
+
+	if (sess->tee_shm) {
+		ret = scmi_msg_from_smt_msg(dev, &chan->smt, msg,
+					    param[2].u.memref.size);
 	} else {
 		ret = scmi_read_resp_from_smt(dev, &chan->smt, msg);
+		scmi_clear_smt_channel(&chan->smt);
 	}
 
-	scmi_clear_smt_channel(&chan->smt);
-
 	return ret;
 }
 
-static int prepare_shm(struct udevice *dev, struct channel_session *sess)
+static int prepare_shm(struct udevice *dev, struct scmi_optee_channel *chan,
+		       struct channel_session *sess)
 {
-	struct scmi_optee_channel *chan = dev_get_plat(dev);
 	int ret;
 
 	/* Static shm is already prepared by the firmware: nothing to do */
@@ -217,9 +263,6 @@ static int prepare_shm(struct udevice *dev, struct channel_session *sess)
 
 	chan->smt.buf = sess->tee_shm->addr;
 
-	/* Initialize shm buffer for message exchanges */
-	scmi_clear_smt_channel(&chan->smt);
-
 	return 0;
 }
 
@@ -231,20 +274,23 @@ static void release_shm(struct udevice *dev, struct channel_session *sess)
 		tee_shm_free(sess->tee_shm);
 }
 
-static int scmi_optee_process_msg(struct udevice *dev, struct scmi_msg *msg)
+static int scmi_optee_process_msg(struct udevice *dev,
+				  struct scmi_channel *channel,
+				  struct scmi_msg *msg)
 {
-	struct channel_session sess;
+	struct scmi_optee_channel *chan = &channel->ref;
+	struct channel_session sess = { };
 	int ret;
 
-	ret = open_channel(dev, &sess);
+	ret = open_channel(dev, chan, &sess);
 	if (ret)
 		return ret;
 
-	ret = prepare_shm(dev, &sess);
+	ret = prepare_shm(dev, chan, &sess);
 	if (ret)
 		goto out;
 
-	ret = invoke_cmd(dev, &sess, msg);
+	ret = invoke_cmd(dev, chan, &sess, msg);
 
 	release_shm(dev, &sess);
 
@@ -254,9 +300,8 @@ out:
 	return ret;
 }
 
-static int scmi_optee_of_to_plat(struct udevice *dev)
+static int setup_channel(struct udevice *dev, struct scmi_optee_channel *chan)
 {
-	struct scmi_optee_channel *chan = dev_get_plat(dev);
 	int ret;
 
 	if (dev_read_u32(dev, "linaro,optee-channel-id", &chan->channel_id)) {
@@ -278,13 +323,52 @@ static int scmi_optee_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
+static int scmi_optee_get_channel(struct udevice *dev,
+				  struct scmi_channel **channel)
+{
+	struct scmi_optee_channel *base_chan = dev_get_plat(dev->parent);
+	struct scmi_optee_channel *chan;
+	u32 channel_id;
+	int ret;
+
+	if (dev_read_u32(dev, "linaro,optee-channel-id", &channel_id)) {
+		/* Uses agent base channel */
+		*channel = container_of(base_chan, struct scmi_channel, ref);
+
+		return 0;
+	}
+
+	/* Setup a dedicated channel */
+	chan = calloc(1, sizeof(*chan));
+	if (!chan)
+		return -ENOMEM;
+
+	ret = setup_channel(dev, chan);
+	if (ret) {
+		free(chan);
+		return ret;
+	}
+
+	*channel = container_of(chan, struct scmi_channel, ref);
+
+	return 0;
+}
+
+static int scmi_optee_of_to_plat(struct udevice *dev)
+{
+	struct scmi_optee_channel *chan = dev_get_plat(dev);
+
+	return setup_channel(dev, chan);
+}
+
 static int scmi_optee_probe(struct udevice *dev)
 {
+	struct scmi_optee_channel *chan = dev_get_plat(dev);
 	struct channel_session sess;
 	int ret;
 
 	/* Check OP-TEE service acknowledges the SCMI channel */
-	ret = open_channel(dev, &sess);
+	ret = open_channel(dev, chan, &sess);
 	if (!ret)
 		close_channel(&sess);
 
@@ -297,6 +381,7 @@ static const struct udevice_id scmi_optee_ids[] = {
 };
 
 static const struct scmi_agent_ops scmi_optee_ops = {
+	.of_get_channel = scmi_optee_get_channel,
 	.process_msg = scmi_optee_process_msg,
 };
 
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c
index c555164..0318829 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c
@@ -471,6 +471,7 @@ static int sandbox_scmi_voltd_level_get(struct udevice *dev,
 }
 
 static int sandbox_scmi_test_process_msg(struct udevice *dev,
+					 struct scmi_channel *channel,
 					 struct scmi_msg *msg)
 {
 	switch (msg->protocol_id) {
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 3819f2f..2b6211c 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -109,30 +109,56 @@ static int scmi_bind_protocols(struct udevice *dev)
 	return ret;
 }
 
-static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev)
+static struct udevice *find_scmi_transport_device(struct udevice *dev)
 {
-	return (const struct scmi_agent_ops *)dev->driver->ops;
-}
-
-int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg)
-{
-	const struct scmi_agent_ops *ops;
 	struct udevice *parent = dev;
 
-	/* Find related SCMI agent device */
 	do {
 		parent = dev_get_parent(parent);
 	} while (parent && device_get_uclass_id(parent) != UCLASS_SCMI_AGENT);
 
-	if (!parent) {
+	if (!parent)
 		dev_err(dev, "Invalid SCMI device, agent not found\n");
+
+	return parent;
+}
+
+static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev)
+{
+	return (const struct scmi_agent_ops *)dev->driver->ops;
+}
+
+int devm_scmi_of_get_channel(struct udevice *dev, struct scmi_channel **channel)
+{
+	struct udevice *parent;
+
+	parent = find_scmi_transport_device(dev);
+	if (!parent)
+		return -ENODEV;
+
+	if (transport_dev_ops(parent)->of_get_channel)
+		return transport_dev_ops(parent)->of_get_channel(dev, channel);
+
+	/* Drivers without a get_channel operator don't need a channel ref */
+	*channel = NULL;
+
+	return 0;
+}
+
+int devm_scmi_process_msg(struct udevice *dev, struct scmi_channel *channel,
+			  struct scmi_msg *msg)
+{
+	const struct scmi_agent_ops *ops;
+	struct udevice *parent;
+
+	parent = find_scmi_transport_device(dev);
+	if (!parent)
 		return -ENODEV;
-	}
 
 	ops = transport_dev_ops(parent);
 
 	if (ops->process_msg)
-		return ops->process_msg(parent, msg);
+		return ops->process_msg(parent, channel, msg);
 
 	return -EPROTONOSUPPORT;
 }
diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c
index 5e166ca..bc2eb67 100644
--- a/drivers/firmware/scmi/smccc_agent.c
+++ b/drivers/firmware/scmi/smccc_agent.c
@@ -30,9 +30,19 @@ struct scmi_smccc_channel {
 	struct scmi_smt smt;
 };
 
-static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg)
+/**
+ * struct scmi_channel - Channel instance referenced in SCMI drivers
+ * @ref: Reference to local channel instance
+ **/
+struct scmi_channel {
+	struct scmi_smccc_channel ref;
+};
+
+static int scmi_smccc_process_msg(struct udevice *dev,
+				  struct scmi_channel *channel,
+				  struct scmi_msg *msg)
 {
-	struct scmi_smccc_channel *chan = dev_get_plat(dev);
+	struct scmi_smccc_channel *chan = &channel->ref;
 	struct arm_smccc_res res;
 	int ret;
 
@@ -51,9 +61,8 @@ static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg)
 	return ret;
 }
 
-static int scmi_smccc_of_to_plat(struct udevice *dev)
+static int setup_channel(struct udevice *dev, struct scmi_smccc_channel *chan)
 {
-	struct scmi_smccc_channel *chan = dev_get_plat(dev);
 	u32 func_id;
 	int ret;
 
@@ -71,12 +80,51 @@ static int scmi_smccc_of_to_plat(struct udevice *dev)
 	return ret;
 }
 
+static int scmi_smccc_get_channel(struct udevice *dev,
+				  struct scmi_channel **channel)
+{
+	struct scmi_smccc_channel *base_chan = dev_get_plat(dev->parent);
+	struct scmi_smccc_channel *chan;
+	u32 func_id;
+	int ret;
+
+	if (dev_read_u32(dev, "arm,smc-id", &func_id)) {
+		/* Uses agent base channel */
+		*channel = container_of(base_chan, struct scmi_channel, ref);
+
+		return 0;
+	}
+
+	/* Setup a dedicated channel */
+	chan = calloc(1, sizeof(*chan));
+	if (!chan)
+		return -ENOMEM;
+
+	ret = setup_channel(dev, chan);
+	if (ret) {
+		free(chan);
+		return ret;
+	}
+
+	*channel = container_of(chan, struct scmi_channel, ref);
+
+	return 0;
+}
+
+static int scmi_smccc_of_to_plat(struct udevice *dev)
+{
+	struct scmi_smccc_channel *chan = dev_get_plat(dev);
+
+	return setup_channel(dev, chan);
+}
+
 static const struct udevice_id scmi_smccc_ids[] = {
 	{ .compatible = "arm,scmi-smc" },
 	{ }
 };
 
 static const struct scmi_agent_ops scmi_smccc_ops = {
+	.of_get_channel = scmi_smccc_get_channel,
 	.process_msg = scmi_smccc_process_msg,
 };
 
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index e60c2ae..509ed61 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
- * Copyright (C) 2019-2020 Linaro Limited.
+ * Copyright (C) 2019-2022 Linaro Limited.
  */
 
 #define LOG_CATEGORY UCLASS_SCMI_AGENT
@@ -137,3 +137,54 @@ void scmi_clear_smt_channel(struct scmi_smt *smt)
 
 	hdr->channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR;
 }
+
+/**
+ * Write SCMI message @msg into a SMT_MSG shared buffer @smt.
+ * Return 0 on success and with a negative errno in case of error.
+ */
+int scmi_msg_to_smt_msg(struct udevice *dev, struct scmi_smt *smt,
+			struct scmi_msg *msg, size_t *buf_size)
+{
+	struct scmi_smt_msg_header *hdr = (void *)smt->buf;
+
+	if ((!msg->in_msg && msg->in_msg_sz) ||
+	    (!msg->out_msg && msg->out_msg_sz))
+		return -EINVAL;
+
+	if (smt->size < (sizeof(*hdr) + msg->in_msg_sz) ||
+	    smt->size < (sizeof(*hdr) + msg->out_msg_sz)) {
+		dev_dbg(dev, "Buffer too small\n");
+		return -ETOOSMALL;
+	}
+
+	*buf_size = msg->in_msg_sz + sizeof(hdr->msg_header);
+
+	hdr->msg_header = SMT_HEADER_TOKEN(0) |
+			  SMT_HEADER_MESSAGE_TYPE(0) |
+			  SMT_HEADER_PROTOCOL_ID(msg->protocol_id) |
+			  SMT_HEADER_MESSAGE_ID(msg->message_id);
+
+	memcpy(hdr->msg_payload, msg->in_msg, msg->in_msg_sz);
+
+	return 0;
+}
+
+/**
+ * Read SCMI message from a SMT shared buffer @smt and copy it into @msg.
+ * Return 0 on success and with a negative errno in case of error.
+ */
+int scmi_msg_from_smt_msg(struct udevice *dev, struct scmi_smt *smt,
+			  struct scmi_msg *msg, size_t buf_size)
+{
+	struct scmi_smt_msg_header *hdr = (void *)smt->buf;
+
+	if (buf_size > msg->out_msg_sz + sizeof(hdr->msg_header)) {
+		dev_err(dev, "Buffer to small\n");
+		return -ETOOSMALL;
+	}
+
+	msg->out_msg_sz = buf_size - sizeof(hdr->msg_header);
+	memcpy(msg->out_msg, hdr->msg_payload, msg->out_msg_sz);
+
+	return 0;
+}
diff --git a/drivers/firmware/scmi/smt.h b/drivers/firmware/scmi/smt.h
index a8c0987..9d669a6 100644
--- a/drivers/firmware/scmi/smt.h
+++ b/drivers/firmware/scmi/smt.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
- * Copyright (C) 2019-2020 Linaro Limited.
+ * Copyright (C) 2019-2022 Linaro Limited.
  */
 #ifndef SCMI_SMT_H
 #define SCMI_SMT_H
@@ -29,6 +29,17 @@ struct scmi_smt_header {
 	u8 msg_payload[0];
 };
 
+/**
+ * struct scmi_msg_header - Description of a MSG shared memory message buffer
+ *
+ * MSG communication protocol uses a 32bit header memory cell to store SCMI
+ * protocol data followed by the exchange SCMI message payload.
+ */
+struct scmi_smt_msg_header {
+	__le32 msg_header;
+	u8 msg_payload[0];
+};
+
 #define SMT_HEADER_TOKEN(token)		(((token) << 18) & GENMASK(31, 18))
 #define SMT_HEADER_PROTOCOL_ID(proto)	(((proto) << 10) & GENMASK(17, 10))
 #define SMT_HEADER_MESSAGE_TYPE(type)	(((type) << 18) & GENMASK(9, 8))
@@ -75,12 +86,44 @@ static inline void scmi_smt_put_channel(struct scmi_smt *smt)
 
 int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt);
 
+/*
+ * Write SCMI message to a SMT shared memory
+ * @dev: SCMI device
+ * @smt: Reference to shared memory using SMT header
+ * @msg: Input SCMI message transmitted
+ */
 int scmi_write_msg_to_smt(struct udevice *dev, struct scmi_smt *smt,
 			  struct scmi_msg *msg);
 
+/*
+ * Read SCMI message from a SMT shared memory
+ * @dev: SCMI device
+ * @smt: Reference to shared memory using SMT header
+ * @msg: Output SCMI message received
+ */
 int scmi_read_resp_from_smt(struct udevice *dev, struct scmi_smt *smt,
 			    struct scmi_msg *msg);
 
 void scmi_clear_smt_channel(struct scmi_smt *smt);
 
+/*
+ * Write SCMI message to SMT_MSG shared memory
+ * @dev: SCMI device
+ * @smt: Reference to shared memory using SMT_MSG header
+ * @msg: Input SCMI message transmitted
+ * @buf_size: Size of the full SMT_MSG buffer transmitted
+ */
+int scmi_msg_to_smt_msg(struct udevice *dev, struct scmi_smt *smt,
+			struct scmi_msg *msg, size_t *buf_size);
+
+/*
+ * Read SCMI message from SMT_MSG shared memory
+ * @dev: SCMI device
+ * @smt: Reference to shared memory using SMT_MSG header
+ * @msg: Output SCMI message received
+ * @buf_size: Size of the full SMT_MSG buffer received
+ */
+int scmi_msg_from_smt_msg(struct udevice *dev, struct scmi_smt *smt,
+			  struct scmi_msg *msg, size_t buf_size);
+
 #endif /* SCMI_SMT_H */
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index e6a3b66..5ae0556 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -16,7 +16,7 @@ struct ti_sci_resource_static_data {
 
 #if IS_ENABLED(CONFIG_K3_DM_FW)
 
-#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM)
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
 static struct ti_sci_resource_static_data rm_static_data[] = {
 	/* Free rings */
 	{
@@ -48,43 +48,9 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
 	},
 	{ },
 };
-#endif /* CONFIG_TARGET_J721E_R5_EVM */
+#endif /* CONFIG_SOC_K3_J721E */
 
-#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)
-static struct ti_sci_resource_static_data rm_static_data[] = {
-	/* Free rings */
-	{
-		.dev_id = 235,
-		.subtype = 1,
-		.range_start = 124,
-		.range_num = 32,
-	},
-	/* TX channels */
-	{
-		.dev_id = 236,
-		.subtype = 13,
-		.range_start = 6,
-		.range_num = 2,
-	},
-	/* RX channels */
-	{
-		.dev_id = 236,
-		.subtype = 10,
-		.range_start = 6,
-		.range_num = 2,
-	},
-	/* RX Free flows */
-	{
-		.dev_id = 236,
-		.subtype = 0,
-		.range_start = 60,
-		.range_num = 8,
-	},
-	{ },
-};
-#endif /* CONFIG_TARGET_J7200_R5_EVM */
-
-#if IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
 static struct ti_sci_resource_static_data rm_static_data[] = {
 	/* Free rings */
 	{
@@ -116,7 +82,20 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
 	},
 	{ },
 };
-#endif /* CONFIG_TARGET_J721S2_R5_EVM */
+#endif /* CONFIG_SOC_K3_J721S2 */
+
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+	/* BC channels */
+	{
+		.dev_id = 26,
+		.subtype = 32,
+		.range_start = 18,
+		.range_num = 2,
+	},
+	{ },
+};
+#endif /* CONFIG_SOC_K3_AM625 */
 
 #else
 static struct ti_sci_resource_static_data rm_static_data[] = {
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index dc0b3dd..7671951 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -21,6 +21,12 @@ config FPGA_SOCFPGA
 
 	  This provides common functionality for Gen5 and Arria10 devices.
 
+config FPGA_STRATIX_V
+	bool "Enable Stratix V FPGA drivers"
+	depends on FPGA_ALTERA
+	help
+	  Say Y here to enable the Altera Stratix V FPGA specific driver.
+
 config FPGA_CYCLON2
 	bool "Enable Altera FPGA driver for Cyclone II"
 	depends on FPGA_ALTERA
diff --git a/drivers/fuzz/Kconfig b/drivers/fuzz/Kconfig
new file mode 100644
index 0000000..6311385
--- /dev/null
+++ b/drivers/fuzz/Kconfig
@@ -0,0 +1,17 @@
+config DM_FUZZING_ENGINE
+	bool "Driver support for fuzzing engine devices"
+	depends on DM
+	help
+	  Enable driver model for fuzzing engine devices. This interface is
+	  used to get fuzzing inputs from a fuzzing engine.
+
+if DM_FUZZING_ENGINE
+
+config FUZZING_ENGINE_SANDBOX
+	bool "Sanbox fuzzing engine"
+	depends on SANDBOX
+	default y
+	help
+	  Enable fuzzing engine for sandbox.
+
+endif
diff --git a/drivers/fuzz/Makefile b/drivers/fuzz/Makefile
new file mode 100644
index 0000000..073743b
--- /dev/null
+++ b/drivers/fuzz/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Google, Inc.
+# Written by Andrew Scull <ascull@google.com>
+#
+
+obj-$(CONFIG_DM_FUZZING_ENGINE) += fuzzing_engine-uclass.o
+obj-$(CONFIG_FUZZING_ENGINE_SANDBOX) += sandbox_fuzzing_engine.o
diff --git a/drivers/fuzz/fuzzing_engine-uclass.c b/drivers/fuzz/fuzzing_engine-uclass.c
new file mode 100644
index 0000000..b16f1c4
--- /dev/null
+++ b/drivers/fuzz/fuzzing_engine-uclass.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull <ascull@google.com>
+ */
+
+#define LOG_CATEGORY UCLASS_FUZZING_ENGINE
+
+#include <common.h>
+#include <dm.h>
+#include <fuzzing_engine.h>
+
+int dm_fuzzing_engine_get_input(struct udevice *dev,
+				const uint8_t **data,
+				size_t *size)
+{
+	const struct dm_fuzzing_engine_ops *ops = device_get_ops(dev);
+
+	if (!ops->get_input)
+		return -ENOSYS;
+
+	return ops->get_input(dev, data, size);
+}
+
+UCLASS_DRIVER(fuzzing_engine) = {
+	.name = "fuzzing_engine",
+	.id = UCLASS_FUZZING_ENGINE,
+};
diff --git a/drivers/fuzz/sandbox_fuzzing_engine.c b/drivers/fuzz/sandbox_fuzzing_engine.c
new file mode 100644
index 0000000..ebb938e
--- /dev/null
+++ b/drivers/fuzz/sandbox_fuzzing_engine.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull <ascull@google.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fuzzing_engine.h>
+#include <asm/fuzzing_engine.h>
+
+static int get_input(struct udevice *dev,
+		     const uint8_t **data,
+		     size_t *size)
+{
+	return sandbox_fuzzing_engine_get_input(data, size);
+}
+
+static const struct dm_fuzzing_engine_ops sandbox_fuzzing_engine_ops = {
+	.get_input = get_input,
+};
+
+static const struct udevice_id sandbox_fuzzing_engine_match[] = {
+	{
+		.compatible = "sandbox,fuzzing-engine",
+	},
+	{},
+};
+
+U_BOOT_DRIVER(sandbox_fuzzing_engine) = {
+	.name = "sandbox-fuzzing-engine",
+	.id = UCLASS_FUZZING_ENGINE,
+	.of_match = sandbox_fuzzing_engine_match,
+	.ops = &sandbox_fuzzing_engine_ops,
+};
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d7f37f0..3c73a7f 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -89,7 +89,7 @@ config DM_GPIO_LOOKUP_LABEL
 
 config SPL_DM_GPIO_LOOKUP_LABEL
 	bool "Enable searching for gpio labelnames"
-	depends on DM_GPIO && SPL_DM && SPL_GPIO
+	depends on SPL_DM_GPIO
 	help
 	  This option enables searching for gpio names in
 	  the defined gpio labels, if the search for the
@@ -491,7 +491,7 @@ config DM_PCA953X
 
 config SPL_DM_PCA953X
 	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL"
-	depends on DM_GPIO
+	depends on SPL_DM_GPIO
 	help
 	  Say yes here to provide access to several register-oriented
 	  SMBus I/O expanders, made mostly by NXP or TI.  Compatible
diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c
index bea609d..77a76c1 100644
--- a/drivers/gpio/atmel_pio4.c
+++ b/drivers/gpio/atmel_pio4.c
@@ -36,6 +36,11 @@ static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
 	case AT91_PIO_PORTD:
 		base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
 		break;
+#if (ATMEL_PIO_PORTS > 4)
+	case AT91_PIO_PORTE:
+		base = (struct atmel_pio4_port *)ATMEL_BASE_PIOE;
+		break;
+#endif
 	default:
 		printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
 		       port);
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index d25c573..72d06e4 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -687,9 +687,9 @@ config SYS_I2C_SPEED
 
 config SYS_I2C_BUS_MAX
 	int "Max I2C busses"
-	depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
+	depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
 	default 2 if TI816X
-	default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
+	default 3 if OMAP34XX || AM33XX || AM43XX
 	default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
 	default 5 if OMAP54XX
 	help
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
index 2d3feca..c9ffe2d 100644
--- a/drivers/i2c/ast_i2c.c
+++ b/drivers/i2c/ast_i2c.c
@@ -16,6 +16,7 @@
 #include <asm/arch/scu_ast2500.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <reset.h>
 
 #include "ast_i2c.h"
 
@@ -108,19 +109,26 @@ static int ast_i2c_of_to_plat(struct udevice *dev)
 
 static int ast_i2c_probe(struct udevice *dev)
 {
-	struct ast2500_scu *scu;
+	struct reset_ctl reset_ctl;
+	int rc;
 
 	debug("Enabling I2C%u\n", dev_seq(dev));
 
 	/*
 	 * Get all I2C devices out of Reset.
-	 * Only needs to be done once, but doing it for every
-	 * device does not hurt.
+	 *
+	 * Only needs to be done once so test before performing reset.
 	 */
-	scu = ast_get_scu();
-	ast_scu_unlock(scu);
-	clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
-	ast_scu_lock(scu);
+	rc = reset_get_by_index(dev, 0, &reset_ctl);
+	if (rc) {
+		printf("%s: Failed to get reset signal\n", __func__);
+		return rc;
+	}
+
+	if (reset_status(&reset_ctl) > 0) {
+		reset_assert(&reset_ctl);
+		reset_deassert(&reset_ctl);
+	}
 
 	ast_i2c_init_bus(dev);
 
@@ -343,6 +351,7 @@ static const struct dm_i2c_ops ast_i2c_ops = {
 static const struct udevice_id ast_i2c_ids[] = {
 	{ .compatible = "aspeed,ast2400-i2c-bus" },
 	{ .compatible = "aspeed,ast2500-i2c-bus" },
+	{ .compatible = "aspeed,ast2600-i2c-bus" },
 	{ },
 };
 
diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c
index a4abd25..ae17722 100644
--- a/drivers/i2c/davinci_i2c.c
+++ b/drivers/i2c/davinci_i2c.c
@@ -21,14 +21,12 @@
 #include <linux/delay.h>
 #include "davinci_i2c.h"
 
-#if CONFIG_IS_ENABLED(DM_I2C)
 /* Information about i2c controller */
 struct i2c_bus {
 	int			id;
 	uint			speed;
 	struct i2c_regs		*regs;
 };
-#endif
 
 #define CHECK_NACK() \
 	do {\
@@ -340,99 +338,6 @@ static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
 	return rc;
 }
 
-#if !CONFIG_IS_ENABLED(DM_I2C)
-static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
-{
-	switch (adap->hwadapnr) {
-#if CONFIG_SYS_I2C_BUS_MAX >= 3
-	case 2:
-		return (struct i2c_regs *)I2C2_BASE;
-#endif
-#if CONFIG_SYS_I2C_BUS_MAX >= 2
-	case 1:
-		return (struct i2c_regs *)I2C1_BASE;
-#endif
-	case 0:
-		return (struct i2c_regs *)I2C_BASE;
-
-	default:
-		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
-	}
-
-	return NULL;
-}
-
-static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
-{
-	struct i2c_regs *i2c_base = davinci_get_base(adap);
-	uint ret;
-
-	adap->speed = speed;
-	ret =  _davinci_i2c_setspeed(i2c_base, speed);
-
-	return ret;
-}
-
-static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
-			     int slaveadd)
-{
-	struct i2c_regs *i2c_base = davinci_get_base(adap);
-
-	adap->speed = speed;
-	_davinci_i2c_init(i2c_base, speed, slaveadd);
-
-	return;
-}
-
-static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
-			    uint32_t addr, int alen, uint8_t *buf, int len)
-{
-	struct i2c_regs *i2c_base = davinci_get_base(adap);
-	return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
-}
-
-static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
-			     uint32_t addr, int alen, uint8_t *buf, int len)
-{
-	struct i2c_regs *i2c_base = davinci_get_base(adap);
-
-	return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
-}
-
-static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
-{
-	struct i2c_regs *i2c_base = davinci_get_base(adap);
-
-	return _davinci_i2c_probe_chip(i2c_base, chip);
-}
-
-U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
-			 davinci_i2c_read, davinci_i2c_write,
-			 davinci_i2c_setspeed,
-			 CONFIG_SYS_DAVINCI_I2C_SPEED,
-			 CONFIG_SYS_DAVINCI_I2C_SLAVE,
-			 0)
-
-#if CONFIG_SYS_I2C_BUS_MAX >= 2
-U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
-			 davinci_i2c_read, davinci_i2c_write,
-			 davinci_i2c_setspeed,
-			 CONFIG_SYS_DAVINCI_I2C_SPEED1,
-			 CONFIG_SYS_DAVINCI_I2C_SLAVE1,
-			 1)
-#endif
-
-#if CONFIG_SYS_I2C_BUS_MAX >= 3
-U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
-			 davinci_i2c_read, davinci_i2c_write,
-			 davinci_i2c_setspeed,
-			 CONFIG_SYS_DAVINCI_I2C_SPEED2,
-			 CONFIG_SYS_DAVINCI_I2C_SLAVE2,
-			 2)
-#endif
-
-#else /* CONFIG_DM_I2C */
-
 static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 			  int nmsgs)
 {
@@ -507,5 +412,3 @@ U_BOOT_DRIVER(i2c_davinci) = {
 	.priv_auto	= sizeof(struct i2c_bus),
 	.ops	= &davinci_i2c_ops,
 };
-
-#endif /* CONFIG_DM_I2C */
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 1aae6b6..e54de42 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  */
 
 #include <common.h>
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index a9c50c9..049976e 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  */
 
 #ifndef __DW_I2C_H_
diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index 1572c2c..46c2545 100644
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  * Copyright 2019 Google Inc
  */
 
diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c
index 39bcacc..a7349e0 100644
--- a/drivers/i2c/exynos_hs_i2c.c
+++ b/drivers/i2c/exynos_hs_i2c.c
@@ -147,7 +147,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
 	unsigned int i = 0, utemp0 = 0, utemp1 = 0;
 	unsigned int t_ftl_cycle;
 
-#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
+#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
 	clkin = get_i2c_clk();
 #else
 	clkin = get_PCLK();
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index 39683fc..323c4fb 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -9,7 +9,7 @@ config I2C_MUX
 
 config SPL_I2C_MUX
 	bool "Support I2C multiplexers on SPL"
-	depends on I2C_MUX
+	depends on SPL && I2C_MUX
 	help
 	  This enables I2C buses to be multiplexed, so that you can select
 	  one of several buses using some sort of control mechanism. The
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index aaccb3a..505e20b 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -8,7 +8,7 @@
 #include <errno.h>
 #include <dm.h>
 #include <fdtdec.h>
-#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
+#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
 #include <log.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/cpu.h>
@@ -53,7 +53,7 @@ static void read_write_byte(struct s3c24x0_i2c *i2c)
 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 {
 	ulong freq, pres = 16, div;
-#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
+#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
 	freq = get_i2c_clk();
 #else
 	freq = get_PCLK();
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 418ed21..ccdd7d7 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -67,7 +67,7 @@ config LED_BLINK
 
 config SPL_LED
 	bool "Enable LED support in SPL"
-	depends on SPL && SPL_DM
+	depends on SPL_DM
 	help
 	  The LED subsystem adds a small amount of overhead to the image.
 	  If this is acceptable and you have a need to use LEDs in SPL,
@@ -85,7 +85,7 @@ config LED_GPIO
 
 config SPL_LED_GPIO
 	bool "LED support for GPIO-connected LEDs in SPL"
-        depends on SPL_LED && DM_GPIO
+        depends on SPL_LED && SPL_DM_GPIO
 	help
 	  This option is an SPL-variant of the LED_GPIO option.
 	  See the help of LED_GPIO for details.
diff --git a/drivers/led/led_pwm.c b/drivers/led/led_pwm.c
index 10bd163..0ebae35 100644
--- a/drivers/led/led_pwm.c
+++ b/drivers/led/led_pwm.c
@@ -95,27 +95,17 @@ static enum led_state_t led_pwm_get_state(struct udevice *dev)
 static int led_pwm_probe(struct udevice *dev)
 {
 	struct led_pwm_priv *priv = dev_get_priv(dev);
-	struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
-
-	/* Ignore the top-level LED node */
-	if (!uc_plat->label)
-		return 0;
 
 	return led_pwm_set_state(dev, (priv->enabled) ? LEDST_ON : LEDST_OFF);
 }
 
 static int led_pwm_of_to_plat(struct udevice *dev)
 {
-	struct led_uc_plat *uc_plat = dev_get_uclass_plat(dev);
 	struct led_pwm_priv *priv = dev_get_priv(dev);
 	struct ofnode_phandle_args args;
 	uint def_brightness, max_brightness;
 	int ret;
 
-	/* Ignore the top-level LED node */
-	if (!uc_plat->label)
-		return 0;
-
 	ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0, &args);
 	if (ret)
 		return ret;
@@ -173,10 +163,15 @@ static const struct udevice_id led_pwm_ids[] = {
 U_BOOT_DRIVER(led_pwm) = {
 	.name = LEDS_PWM_DRIVER_NAME,
 	.id = UCLASS_LED,
-	.of_match = led_pwm_ids,
 	.ops = &led_pwm_ops,
 	.priv_auto = sizeof(struct led_pwm_priv),
-	.bind = led_pwm_bind,
 	.probe = led_pwm_probe,
 	.of_to_plat = led_pwm_of_to_plat,
 };
+
+U_BOOT_DRIVER(led_pwm_wrap) = {
+	.name = LEDS_PWM_DRIVER_NAME "_wrap",
+	.id = UCLASS_NOP,
+	.of_match = led_pwm_ids,
+	.bind = led_pwm_bind,
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 007c728..e839c08 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -43,6 +43,22 @@ config VPL_MISC
 	  set of generic read, write and ioctl methods may be used to
 	  access the device.
 
+config NVMEM
+	bool "NVMEM support"
+	help
+	  This adds support for a common interface to different types of
+	  non-volatile memory. Consumers can use nvmem-cells properties to look
+	  up hardware configuration data such as MAC addresses and calibration
+	  settings.
+
+config SPL_NVMEM
+	bool "NVMEM support in SPL"
+	help
+	  This adds support for a common interface to different types of
+	  non-volatile memory. Consumers can use nvmem-cells properties to look
+	  up hardware configuration data such as MAC addresses and calibration
+	  settings.
+
 config ALTERA_SYSID
 	bool "Altera Sysid support"
 	depends on MISC
@@ -125,7 +141,7 @@ config CROS_EC
 
 config SPL_CROS_EC
 	bool "Enable Chrome OS EC in SPL"
-	depends on SPL
+	depends on SPL_MISC
 	help
 	  Enable access to the Chrome OS EC in SPL. This is a separate
 	  microcontroller typically available on a SPI bus on Chromebooks. It
@@ -135,7 +151,7 @@ config SPL_CROS_EC
 
 config TPL_CROS_EC
 	bool "Enable Chrome OS EC in TPL"
-	depends on TPL
+	depends on TPL_MISC
 	help
 	  Enable access to the Chrome OS EC in TPL. This is a separate
 	  microcontroller typically available on a SPI bus on Chromebooks. It
@@ -145,7 +161,7 @@ config TPL_CROS_EC
 
 config VPL_CROS_EC
 	bool "Enable Chrome OS EC in VPL"
-	depends on VPL
+	depends on VPL_MISC
 	help
 	  Enable access to the Chrome OS EC in VPL. This is a separate
 	  microcontroller typically available on a SPI bus on Chromebooks. It
@@ -173,7 +189,7 @@ config CROS_EC_LPC
 
 config SPL_CROS_EC_LPC
 	bool "Enable Chrome OS EC LPC driver in SPL"
-	depends on CROS_EC
+	depends on CROS_EC && SPL_MISC
 	help
 	  Enable I2C access to the Chrome OS EC. This is used on x86
 	  Chromebooks such as link and falco. The keyboard is provided
@@ -182,7 +198,7 @@ config SPL_CROS_EC_LPC
 
 config TPL_CROS_EC_LPC
 	bool "Enable Chrome OS EC LPC driver in TPL"
-	depends on CROS_EC
+	depends on CROS_EC && TPL_MISC
 	help
 	  Enable I2C access to the Chrome OS EC. This is used on x86
 	  Chromebooks such as link and falco. The keyboard is provided
@@ -191,7 +207,7 @@ config TPL_CROS_EC_LPC
 
 config VPL_CROS_EC_LPC
 	bool "Enable Chrome OS EC LPC driver in VPL"
-	depends on CROS_EC
+	depends on CROS_EC && VPL_MISC
 	help
 	  Enable I2C access to the Chrome OS EC. This is used on x86
 	  Chromebooks such as link and falco. The keyboard is provided
@@ -259,6 +275,20 @@ config FSL_SEC_MON
 	  Security Monitor can be transitioned on any security failures,
 	  like software violations or hardware security violations.
 
+choice
+	prompt "Security monitor interaction endianess"
+	depends on FSL_SEC_MON
+	default SYS_FSL_SEC_MON_BE if PPC
+	default SYS_FSL_SEC_MON_LE
+
+config SYS_FSL_SEC_MON_LE
+	bool "Security monitor interactions are little endian"
+
+config SYS_FSL_SEC_MON_BE
+	bool "Security monitor interactions are big endian"
+
+endchoice
+
 config IRQ
 	bool "Interrupt controller"
 	help
@@ -273,6 +303,20 @@ config JZ4780_EFUSE
 	help
 	  This selects support for the eFUSE on Ingenic JZ4780 SoCs.
 
+config LS2_SFP
+	bool "Layerscape Security Fuse Processor"
+	depends on FSL_LSCH2 || ARCH_LS1021A
+	depends on MISC
+	imply DM_REGULATOR
+	help
+	  This adds support for the Security Fuse Processor found on Layerscape
+	  SoCs. It contains various fuses related to secure boot, including the
+	  Super Root Key hash, One-Time-Programmable Master Key, Debug
+	  Challenge/Response values, and others. Fuses are numbered according
+	  to their four-byte offset from the start of the bank.
+
+	  If you don't need to read/program fuses, say 'n'.
+
 config MXC_OCOTP
 	bool "Enable MXC OCOTP Driver"
 	depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
@@ -282,15 +326,30 @@ config MXC_OCOTP
 	  Programmable memory pages that are stored on the some
 	  Freescale i.MX processors.
 
+config NPCM_HOST
+	bool "Enable support espi or LPC for Host"
+	depends on REGMAP && SYSCON
+	help
+	  Enable NPCM BMC espi or LPC support for Host reading and writing.
+
 config SPL_MXC_OCOTP
 	bool "Enable MXC OCOTP driver in SPL"
-	depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
+	depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
 	default y
 	help
 	  If you say Y here, you will get support for the One Time
 	  Programmable memory pages, that are stored on some
 	  Freescale i.MX processors, in SPL.
 
+config NPCM_OTP
+	bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
+	depends on (ARM && ARCH_NPCM)
+	default n
+	help
+	  Support NPCM BMC OTP memory (fuse).
+	  To compile this driver as a module, choose M here: the module
+	  will be called npcm_otp.
+
 config NUVOTON_NCT6102D
 	bool "Enable Nuvoton NCT6102D Super I/O driver"
 	help
@@ -314,7 +373,7 @@ config P2SB
 
 config SPL_P2SB
 	bool "Intel Primary to Sideband Bridge in SPL"
-	depends on SPL && (X86 || SANDBOX)
+	depends on SPL_MISC && (X86 || SANDBOX)
 	help
 	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
@@ -324,7 +383,7 @@ config SPL_P2SB
 
 config TPL_P2SB
 	bool "Intel Primary to Sideband Bridge in TPL"
-	depends on TPL && (X86 || SANDBOX)
+	depends on TPL_MISC && (X86 || SANDBOX)
 	help
 	  The Primary to Sideband Bridge is used to access various peripherals
 	  through memory-mapped I/O in a large chunk of PCI space. The space is
@@ -343,7 +402,7 @@ config PWRSEQ
 
 config SPL_PWRSEQ
 	bool "Enable power-sequencing drivers for SPL"
-	depends on PWRSEQ
+	depends on SPL_MISC && PWRSEQ
 	help
 	  Power-sequencing drivers provide support for controlling power for
 	  devices. They are typically referenced by a phandle from another
@@ -460,7 +519,7 @@ config I2C_EEPROM
 
 config SPL_I2C_EEPROM
 	bool "Enable driver for generic I2C-attached EEPROMs for SPL"
-	depends on MISC && SPL && SPL_DM
+	depends on SPL_MISC
 	help
 	  This option is an SPL-variant of the I2C_EEPROM option.
 	  See the help of I2C_EEPROM for details.
@@ -513,6 +572,7 @@ config FS_LOADER
 
 config SPL_FS_LOADER
 	bool "Enable loader driver for file system"
+	depends on SPL
 	help
 	  This is file system generic loader which can be used to load
 	  the file image from the storage into target such as memory.
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b9c54bd..022e54e 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -4,6 +4,7 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-$(CONFIG_$(SPL_TPL_)MISC) += misc-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)NVMEM) += nvmem.o
 
 obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
 obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
@@ -52,8 +53,11 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
+obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o
 obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
+obj-$(CONFIG_NPCM_OTP) += npcm_otp.o
+obj-$(CONFIG_NPCM_HOST) += npcm_host_intf.o
 obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
 obj-$(CONFIG_P2SB) += p2sb-uclass.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
index 89a450d..bdd7e01 100644
--- a/drivers/misc/i2c_eeprom.c
+++ b/drivers/misc/i2c_eeprom.c
@@ -33,7 +33,8 @@ int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size)
 	return ops->read(dev, offset, buf, size);
 }
 
-int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size)
+int i2c_eeprom_write(struct udevice *dev, int offset, const uint8_t *buf,
+		     int size)
 {
 	const struct i2c_eeprom_ops *ops = device_get_ops(dev);
 
@@ -169,13 +170,6 @@ static const struct i2c_eeprom_drv_data eeprom_data = {
 	.offset_len = 1,
 };
 
-static const struct i2c_eeprom_drv_data mc24aa02e48_data = {
-	.size = 256,
-	.pagesize = 8,
-	.addr_offset_mask = 0,
-	.offset_len = 1,
-};
-
 static const struct i2c_eeprom_drv_data atmel24c01a_data = {
 	.size = 128,
 	.pagesize = 8,
@@ -263,7 +257,6 @@ static const struct i2c_eeprom_drv_data atmel24c512_data = {
 
 static const struct udevice_id i2c_eeprom_std_ids[] = {
 	{ .compatible = "i2c-eeprom", (ulong)&eeprom_data },
-	{ .compatible = "microchip,24aa02e48", (ulong)&mc24aa02e48_data },
 	{ .compatible = "atmel,24c01", (ulong)&atmel24c01a_data },
 	{ .compatible = "atmel,24c01a", (ulong)&atmel24c01a_data },
 	{ .compatible = "atmel,24c02", (ulong)&atmel24c02_data },
diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c
index 85b127c..6f32087 100644
--- a/drivers/misc/i2c_eeprom_emul.c
+++ b/drivers/misc/i2c_eeprom_emul.c
@@ -171,11 +171,15 @@ static int sandbox_i2c_eeprom_probe(struct udevice *dev)
 {
 	struct sandbox_i2c_flash_plat_data *plat = dev_get_plat(dev);
 	struct sandbox_i2c_flash *priv = dev_get_priv(dev);
+	/* For eth3 */
+	const u8 mac[] = { 0x02, 0x00, 0x11, 0x22, 0x33, 0x45 };
 
 	priv->data = calloc(1, plat->size);
 	if (!priv->data)
 		return -ENOMEM;
 
+	memcpy(&priv->data[24], mac, sizeof(mac));
+
 	return 0;
 }
 
diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c
new file mode 100644
index 0000000..dd10496
--- /dev/null
+++ b/drivers/misc/ls2_sfp.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
+ *
+ * This driver supports the Security Fuse Processor device found on some
+ * Layerscape processors. At the moment, we only support a few processors.
+ * This driver was written with reference to the Layerscape SDK User
+ * Guide [1] and the ATF SFP driver [2].
+ *
+ * [1] https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-27FC40AD-3321-4A82-B29E-7BB49EE94F23.html
+ * [2] https://source.codeaurora.org/external/qoriq/qoriq-components/atf/tree/drivers/nxp/sfp?h=github.com/master
+ */
+
+#define LOG_CATEGORY UCLASS_MISC
+#include <common.h>
+#include <clk.h>
+#include <fuse.h>
+#include <misc.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/read.h>
+#include <linux/bitfield.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SFP_INGR	0x20
+#define SFP_SVHESR	0x24
+#define SFP_SFPCR	0x28
+
+#define SFP_START	0x200
+#define SFP_END		0x284
+#define SFP_SIZE	(SFP_END - SFP_START + 4)
+
+#define SFP_INGR_ERR	BIT(8)
+#define SFP_INGR_INST	GENMASK(7, 0)
+
+#define SFP_INGR_READFB	0x01
+#define SFP_INGR_PROGFB	0x02
+
+#define SFP_SFPCR_PPW	GENMASK(15, 0)
+
+enum ls2_sfp_ioctl {
+	LS2_SFP_IOCTL_READ,
+	LS2_SFP_IOCTL_PROG,
+};
+
+/**
+ * struct ls2_sfp_priv - private data for LS2 SFP
+ * @base: Base address of SFP
+ * @supply: The (optional) supply for TA_PROG_SFP
+ * @programmed: Whether we've already programmed the fuses since the last
+ *              reset. The SFP has a *very* limited amount of programming
+ *              cycles (two to six, depending on the model), so we try and
+ *              prevent accidentally performing additional programming
+ *              cycles.
+ * @dirty: Whether the mirror registers have been written to (overridden)
+ *         since we've last read the fuses (either as part of the reset
+ *         process or using a READFB instruction). There is a much larger,
+ *         but still finite, limit on the number of SFP read cycles (around
+ *         300,000), so we try and minimize reads as well.
+ */
+struct ls2_sfp_priv {
+	void __iomem *base;
+	struct udevice *supply;
+	bool programmed, dirty;
+};
+
+static u32 ls2_sfp_readl(struct ls2_sfp_priv *priv, ulong off)
+{
+	u32 val = be32_to_cpu(readl(priv->base + off));
+
+	log_debug("%08x = readl(%p)\n", val, priv->base + off);
+	return val;
+}
+
+static void ls2_sfp_writel(struct ls2_sfp_priv *priv, ulong val, ulong off)
+{
+	log_debug("writel(%08lx, %p)\n", val, priv->base + off);
+	writel(cpu_to_be32(val), priv->base + off);
+}
+
+static bool ls2_sfp_validate(struct udevice *dev, int offset, int size)
+{
+	if (offset < 0 || size < 0) {
+		dev_notice(dev, "size and offset must be positive\n");
+		return false;
+	}
+
+	if (offset & 3 || size & 3) {
+		dev_notice(dev, "size and offset must be multiples of 4\n");
+		return false;
+	}
+
+	if (offset + size > SFP_SIZE) {
+		dev_notice(dev, "size + offset must be <= %#x\n", SFP_SIZE);
+		return false;
+	}
+
+	return true;
+}
+
+static int ls2_sfp_read(struct udevice *dev, int offset, void *buf_bytes,
+			int size)
+{
+	int i;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	u32 *buf = buf_bytes;
+
+	if (!ls2_sfp_validate(dev, offset, size))
+		return -EINVAL;
+
+	for (i = 0; i < size; i += 4)
+		buf[i >> 2] = ls2_sfp_readl(priv, SFP_START + offset + i);
+
+	return size;
+}
+
+static int ls2_sfp_write(struct udevice *dev, int offset,
+			 const void *buf_bytes, int size)
+{
+	int i;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	const u32 *buf = buf_bytes;
+
+	if (!ls2_sfp_validate(dev, offset, size))
+		return -EINVAL;
+
+	for (i = 0; i < size; i += 4)
+		ls2_sfp_writel(priv, buf[i >> 2], SFP_START + offset + i);
+
+	priv->dirty = true;
+	return size;
+}
+
+static int ls2_sfp_check_secret(struct udevice *dev)
+{
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	u32 svhesr = ls2_sfp_readl(priv, SFP_SVHESR);
+
+	if (svhesr) {
+		dev_warn(dev, "secret value hamming error not zero: %08x\n",
+			 svhesr);
+		return -EIO;
+	}
+	return 0;
+}
+
+static int ls2_sfp_transaction(struct ls2_sfp_priv *priv, ulong inst)
+{
+	u32 ingr;
+
+	ls2_sfp_writel(priv, inst, SFP_INGR);
+
+	do {
+		ingr = ls2_sfp_readl(priv, SFP_INGR);
+	} while (FIELD_GET(SFP_INGR_INST, ingr));
+
+	return FIELD_GET(SFP_INGR_ERR, ingr) ? -EIO : 0;
+}
+
+static int ls2_sfp_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+	int ret;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+
+	switch (request) {
+	case LS2_SFP_IOCTL_READ:
+		if (!priv->dirty) {
+			dev_dbg(dev, "ignoring read request, since fuses are not dirty\n");
+			return 0;
+		}
+
+		ret = ls2_sfp_transaction(priv, SFP_INGR_READFB);
+		if (ret) {
+			dev_err(dev, "error reading fuses\n");
+			return ret;
+		}
+
+		ls2_sfp_check_secret(dev);
+		priv->dirty = false;
+		return 0;
+	case LS2_SFP_IOCTL_PROG:
+		if (priv->programmed) {
+			dev_warn(dev, "fuses already programmed\n");
+			return -EPERM;
+		}
+
+		ret = ls2_sfp_check_secret(dev);
+		if (ret)
+			return ret;
+
+		if (priv->supply) {
+			ret = regulator_set_enable(priv->supply, true);
+			if (ret)
+				return ret;
+		}
+
+		ret = ls2_sfp_transaction(priv, SFP_INGR_PROGFB);
+		priv->programmed = true;
+		if (priv->supply)
+			regulator_set_enable(priv->supply, false);
+
+		if (ret)
+			dev_err(dev, "error programming fuses\n");
+		return ret;
+	default:
+		dev_dbg(dev, "unknown ioctl %lu\n", request);
+		return -EINVAL;
+	}
+}
+
+static const struct misc_ops ls2_sfp_ops = {
+	.read = ls2_sfp_read,
+	.write = ls2_sfp_write,
+	.ioctl = ls2_sfp_ioctl,
+};
+
+static int ls2_sfp_probe(struct udevice *dev)
+{
+	int ret;
+	struct clk clk;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	ulong rate;
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base) {
+		dev_dbg(dev, "could not read register base\n");
+		return -EINVAL;
+	}
+
+	ret = device_get_supply_regulator(dev, "ta-sfp-prog", &priv->supply);
+	if (ret && ret != -ENODEV && ret != -ENOSYS) {
+		dev_dbg(dev, "problem getting supply (err %d)\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "sfp", &clk);
+	if (ret == -ENOSYS) {
+		rate = gd->bus_clk / 4;
+	} else if (ret) {
+		dev_dbg(dev, "could not get clock (err %d)\n", ret);
+		return ret;
+	} else {
+		ret = clk_enable(&clk);
+		if (ret) {
+			dev_dbg(dev, "could not enable clock (err %d)\n", ret);
+			return ret;
+		}
+
+		rate = clk_get_rate(&clk);
+		clk_free(&clk);
+		if (!rate || IS_ERR_VALUE(rate)) {
+			ret = rate ? rate : -ENOENT;
+			dev_dbg(dev, "could not get clock rate (err %d)\n",
+				ret);
+			return ret;
+		}
+	}
+
+	/* sfp clock in MHz * 12 */
+	ls2_sfp_writel(priv, FIELD_PREP(SFP_SFPCR_PPW, rate * 12 / 1000000),
+		       SFP_SFPCR);
+
+	ls2_sfp_check_secret(dev);
+	return 0;
+}
+
+static const struct udevice_id ls2_sfp_ids[] = {
+	{ .compatible = "fsl,ls1021a-sfp" },
+	{ }
+};
+
+U_BOOT_DRIVER(ls2_sfp) = {
+	.name		= "ls2_sfp",
+	.id		= UCLASS_MISC,
+	.of_match	= ls2_sfp_ids,
+	.probe		= ls2_sfp_probe,
+	.ops		= &ls2_sfp_ops,
+	.priv_auto	= sizeof(struct ls2_sfp_priv),
+};
+
+static int ls2_sfp_device(struct udevice **dev)
+{
+	int ret = uclass_get_device_by_driver(UCLASS_MISC,
+					      DM_DRIVER_GET(ls2_sfp), dev);
+
+	if (ret)
+		log_debug("device not found (err %d)\n", ret);
+	return ret;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_ioctl(dev, LS2_SFP_IOCTL_READ, NULL);
+	if (ret)
+		return ret;
+
+	ret = misc_read(dev, word << 2, val, sizeof(*val));
+	return ret < 0 ? ret : 0;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_read(dev, word << 2, val, sizeof(*val));
+	return ret < 0 ? ret : 0;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_write(dev, word << 2, &val, sizeof(val));
+	if (ret < 0)
+		return ret;
+
+	return misc_ioctl(dev, LS2_SFP_IOCTL_PROG, NULL);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_write(dev, word << 2, &val, sizeof(val));
+	return ret < 0 ? ret : 0;
+}
diff --git a/drivers/misc/misc_sandbox.c b/drivers/misc/misc_sandbox.c
index 0e4292f..31cde2d 100644
--- a/drivers/misc/misc_sandbox.c
+++ b/drivers/misc/misc_sandbox.c
@@ -112,8 +112,11 @@ static const struct misc_ops misc_sandbox_ops = {
 int misc_sandbox_probe(struct udevice *dev)
 {
 	struct misc_sandbox_priv *priv = dev_get_priv(dev);
+	/* For eth5 */
+	const u8 mac[] = { 0x02, 0x00, 0x11, 0x22, 0x33, 0x46 };
 
 	priv->enabled = true;
+	memcpy(&priv->mem[16], mac, sizeof(mac));
 
 	return 0;
 }
diff --git a/drivers/misc/npcm_host_intf.c b/drivers/misc/npcm_host_intf.c
new file mode 100644
index 0000000..0244e40
--- /dev/null
+++ b/drivers/misc/npcm_host_intf.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Host interface (LPC or eSPI) configuration on Nuvoton BMC
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+
+#define SMC_CTL_REG_ADDR	0xc0001001
+#define SMC_CTL_HOSTWAIT	0x80
+
+/* GCR Register Offsets */
+#define HIFCR			0x50
+#define MFSEL1			0x260
+#define MFSEL4			0x26c
+
+/* ESPI Register offsets */
+#define ESPICFG			0x4
+#define ESPIHINDP		0x80
+
+/* MFSEL bit fileds */
+#define MFSEL1_LPCSEL		BIT(26)
+#define MFSEL4_ESPISEL		BIT(8)
+
+/* ESPICFG bit fileds */
+#define CHSUPP_MASK		GENMASK(27, 24)
+#define IOMODE_MASK		GENMASK(9, 8)
+#define IOMODE_SDQ		FIELD_PREP(IOMODE_MASK, 3)
+#define MAXFREQ_MASK		GENMASK(12, 10)
+#define MAXFREQ_33MHZ		FIELD_PREP(MAXFREQ_MASK, 2)
+
+/* ESPIHINDP bit fileds */
+#define AUTO_SBLD		BIT(4)
+#define AUTO_HS1		BIT(8)
+#define AUTO_HS2		BIT(12)
+#define AUTO_HS3		BIT(16)
+
+static int npcm_host_intf_bind(struct udevice *dev)
+{
+	struct regmap *syscon;
+	void __iomem *base;
+	u32 ch_supp, val;
+	u32 ioaddr;
+	const char *type;
+	int ret;
+
+	/* Release host wait */
+	setbits_8(SMC_CTL_REG_ADDR, SMC_CTL_HOSTWAIT);
+
+	syscon = syscon_regmap_lookup_by_phandle(dev, "syscon");
+	if (IS_ERR(syscon)) {
+		dev_err(dev, "%s: unable to get syscon, dev %s\n", __func__, dev->name);
+		return PTR_ERR(syscon);
+	}
+
+	ioaddr  = dev_read_u32_default(dev, "ioaddr", 0);
+	if (ioaddr)
+		regmap_write(syscon, HIFCR, ioaddr);
+
+	type = dev_read_string(dev, "type");
+	if (!type)
+		return -EINVAL;
+
+	if (!strcmp(type, "espi")) {
+		base = dev_read_addr_ptr(dev);
+		if (!base)
+			return -EINVAL;
+
+		ret = dev_read_u32(dev, "channel-support", &ch_supp);
+		if (ret)
+			return ret;
+
+		/* Select eSPI pins function */
+		regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, 0);
+		regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, MFSEL4_ESPISEL);
+
+		val = AUTO_SBLD | AUTO_HS1 | AUTO_HS2 | AUTO_HS3 | ch_supp;
+		writel(val, base + ESPIHINDP);
+
+		val = readl(base + ESPICFG);
+		val &= ~(CHSUPP_MASK | IOMODE_MASK | MAXFREQ_MASK);
+		val |= IOMODE_SDQ | MAXFREQ_33MHZ | FIELD_PREP(CHSUPP_MASK, ch_supp);
+		writel(val, base + ESPICFG);
+	} else if (!strcmp(type, "lpc")) {
+		/* Select LPC pin function */
+		regmap_update_bits(syscon, MFSEL4, MFSEL4_ESPISEL, 0);
+		regmap_update_bits(syscon, MFSEL1, MFSEL1_LPCSEL, MFSEL1_LPCSEL);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id npcm_hostintf_ids[] = {
+	{ .compatible = "nuvoton,npcm750-host-intf" },
+	{ .compatible = "nuvoton,npcm845-host-intf" },
+	{ }
+};
+
+U_BOOT_DRIVER(npcm_host_intf) = {
+	.name	= "npcm_host_intf",
+	.id	= UCLASS_MISC,
+	.of_match = npcm_hostintf_ids,
+	.bind = npcm_host_intf_bind,
+};
diff --git a/drivers/misc/npcm_otp.c b/drivers/misc/npcm_otp.c
new file mode 100644
index 0000000..3049108
--- /dev/null
+++ b/drivers/misc/npcm_otp.c
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fuse.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <asm/arch/otp.h>
+
+struct npcm_otp_priv {
+	struct npcm_otp_regs *regs[2];
+};
+
+static struct npcm_otp_priv *otp_priv;
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_check_inputs                                     */
+/*                                                                            */
+/* Parameters:      arr - fuse array number to check                          */
+/*                  word - fuse word (offset) to check                        */
+/* Returns:         int                                                       */
+/* Side effects:                                                              */
+/* Description:     Checks is arr and word are illegal and do not exceed      */
+/*                  their range. Return 0 if they are legal, -1 if not        */
+/*----------------------------------------------------------------------------*/
+static int npcm_otp_check_inputs(u32 arr, u32 word)
+{
+	if (arr >= NPCM_NUM_OF_SA) {
+		if (IS_ENABLED(CONFIG_ARCH_NPCM8XX))
+			printf("\nError: npcm8XX otp includs only one bank: 0\n");
+		if (IS_ENABLED(CONFIG_ARCH_NPCM7XX))
+			printf("\nError: npcm7XX otp includs only two banks: 0 and 1\n");
+		return -1;
+	}
+
+	if (word >= NPCM_OTP_ARR_BYTE_SIZE) {
+		printf("\nError: npcm otp array comprises only %d bytes, numbered from 0 to %d\n",
+		       NPCM_OTP_ARR_BYTE_SIZE, NPCM_OTP_ARR_BYTE_SIZE - 1);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_wait_for_otp_ready                               */
+/*                                                                            */
+/* Parameters:      array - fuse array to wait for                            */
+/* Returns:         int                                                       */
+/* Side effects:                                                              */
+/* Description:     Initialize the Fuse HW module.                            */
+/*----------------------------------------------------------------------------*/
+static int npcm_otp_wait_for_otp_ready(u32 arr, u32 timeout)
+{
+	struct npcm_otp_regs *regs = otp_priv->regs[arr];
+	u32 time = timeout;
+
+	/*------------------------------------------------------------------------*/
+	/* check parameters validity                                              */
+	/*------------------------------------------------------------------------*/
+	if (arr > NPCM_FUSE_SA)
+		return -EINVAL;
+
+	while (--time > 1) {
+		if (readl(&regs->fst) & FST_RDY) {
+			/* fuse is ready, clear the status. */
+			writel(readl(&regs->fst) | FST_RDST, &regs->fst);
+			return 0;
+		}
+	}
+
+	/* try to clear the status in case it was set */
+	writel(readl(&regs->fst) | FST_RDST, &regs->fst);
+
+	return -EINVAL;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_read_byte                                        */
+/*                                                                            */
+/* Parameters:      arr  - Storage Array type [input].                        */
+/*                  addr - Byte-address to read from [input].                 */
+/*                  data - Pointer to result [output].                        */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     Read 8-bit data from an OTP storage array.                */
+/*----------------------------------------------------------------------------*/
+static void npcm_otp_read_byte(u32 arr, u32 addr, u8 *data)
+{
+	struct npcm_otp_regs *regs = otp_priv->regs[arr];
+
+	/* Wait for the Fuse Box Idle */
+	npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF);
+
+	/* Configure the byte address in the fuse array for read operation */
+	writel(FADDR_VAL(addr, 0), &regs->faddr);
+
+	/* Initiate a read cycle */
+	writel(READ_INIT, &regs->fctl);
+
+	/* Wait for read operation completion */
+	npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF);
+
+	/* Read the result */
+	*data = readl(&regs->fdata) & FDATA_MASK;
+
+	/* Clean FDATA contents to prevent unauthorized software from reading
+	 * sensitive information
+	 */
+	writel(FDATA_CLEAN_VALUE, &regs->fdata);
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_bit_is_programmed                                */
+/*                                                                            */
+/* Parameters:      arr     - Storage Array type [input].                     */
+/*                  byte_offset - Byte offset in array [input].               */
+/*                  bit_offset  - Bit offset in byte [input].                 */
+/* Returns:         Nonzero if bit is programmed, zero otherwise.             */
+/* Side effects:                                                              */
+/* Description:     Check if a bit is programmed in an OTP storage array.     */
+/*----------------------------------------------------------------------------*/
+static bool npcm_otp_bit_is_programmed(u32  arr,
+				       u32 byte_offset, u8 bit_offset)
+{
+	u32 data = 0;
+
+	/* Read the entire byte you wish to program */
+	npcm_otp_read_byte(arr, byte_offset, (u8 *)&data);
+
+	/* Check whether the bit is already programmed */
+	if (data & (1 << bit_offset))
+		return true;
+
+	return false;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_program_bit                                      */
+/*                                                                            */
+/* Parameters:      arr     - Storage Array type [input].                     */
+/*                  byte)offset - Byte offset in array [input].               */
+/*                  bit_offset  - Bit offset in byte [input].                 */
+/* Returns:         int                                                       */
+/* Side effects:                                                              */
+/* Description:     Program (set to 1) a bit in an OTP storage array.         */
+/*----------------------------------------------------------------------------*/
+static int npcm_otp_program_bit(u32 arr, u32 byte_offset,
+				u8 bit_offset)
+{
+	struct npcm_otp_regs *regs = otp_priv->regs[arr];
+	int count;
+	u8 read_data;
+
+	/* Wait for the Fuse Box Idle */
+	npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF);
+
+	/* Make sure the bit is not already programmed */
+	if (npcm_otp_bit_is_programmed(arr, byte_offset, bit_offset))
+		return 0;
+
+	/* Configure the bit address in the fuse array for program operation */
+	writel(FADDR_VAL(byte_offset, bit_offset), &regs->faddr);
+	writel(readl(&regs->faddr) | FADDR_IN_PROG, &regs->faddr);
+
+	// program up to MAX_PROGRAM_PULSES
+	for (count = 1; count <= MAX_PROGRAM_PULSES; count++) {
+		/* Initiate a program cycle */
+		writel(PROGRAM_ARM, &regs->fctl);
+		writel(PROGRAM_INIT, &regs->fctl);
+
+		/* Wait for program operation completion */
+		npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF);
+
+		// after MIN_PROGRAM_PULSES start verifying the result
+		if (count >= MIN_PROGRAM_PULSES) {
+			/* Initiate a read cycle */
+			writel(READ_INIT, &regs->fctl);
+
+			/* Wait for read operation completion */
+			npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF);
+
+			/* Read the result */
+			read_data = readl(&regs->fdata) & FDATA_MASK;
+
+			/* If the bit is set the sequence ended correctly */
+			if (read_data & (1 << bit_offset))
+				break;
+		}
+	}
+
+	// check if programmking failed
+	if (count > MAX_PROGRAM_PULSES) {
+		printf("program fail\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Clean FDATA contents to prevent unauthorized software from reading
+	 * sensitive information
+	 */
+	writel(FDATA_CLEAN_VALUE, &regs->fdata);
+
+	return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_program_byte                                     */
+/*                                                                            */
+/* Parameters:      arr     - Storage Array type [input].                     */
+/*                  byte_offset - Byte offset in array [input].               */
+/*                  value   - Byte to program [input].                        */
+/* Returns:         int                                                       */
+/* Side effects:                                                              */
+/* Description:     Program (set to 1) a given byte's relevant bits in an     */
+/*                  OTP storage array.                                        */
+/*----------------------------------------------------------------------------*/
+static int npcm_otp_program_byte(u32 arr, u32 byte_offset,
+				 u8 value)
+{
+	int status = 0;
+	unsigned int i;
+	u8 data = 0;
+	int rc;
+
+	rc = npcm_otp_check_inputs(arr, byte_offset);
+	if (rc != 0)
+		return rc;
+
+	/* Wait for the Fuse Box Idle */
+	npcm_otp_wait_for_otp_ready(arr, 0xDEADBEEF);
+
+	/* Read the entire byte you wish to program */
+	npcm_otp_read_byte(arr, byte_offset, &data);
+
+	/* In case all relevant bits are already programmed - nothing to do */
+	if ((~data & value) == 0)
+		return status;
+
+	/* Program unprogrammed bits. */
+	for (i = 0; i < 8; i++) {
+		if (value & (1 << i)) {
+			/* Program (set to 1) the relevant bit */
+			int last_status = npcm_otp_program_bit(arr, byte_offset, (u8)i);
+
+			if (last_status != 0)
+				status = last_status;
+		}
+	}
+	return status;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_is_fuse_array_disabled                           */
+/*                                                                            */
+/* Parameters:      arr - Storage Array type [input].                         */
+/* Returns:         bool                                                      */
+/* Side effects:                                                              */
+/* Description:     Return true if access to the first 2048 bits of the       */
+/*                  specified fuse array is disabled, false if not            */
+/*----------------------------------------------------------------------------*/
+bool npcm_otp_is_fuse_array_disabled(u32 arr)
+{
+	struct npcm_otp_regs *regs = otp_priv->regs[arr];
+
+	return (readl(&regs->fcfg) & FCFG_FDIS) != 0;
+}
+
+int npcm_otp_select_key(u8 key_index)
+{
+	struct npcm_otp_regs *regs = otp_priv->regs[NPCM_KEY_SA];
+	u32 idx = 0;
+	u32 time = 0xDAEDBEEF;
+
+	if (key_index >= 4)
+		return -1;
+
+	/* Do not destroy ECCDIS bit */
+	idx = readl(&regs->fustrap_fkeyind);
+
+	/* Configure the key size */
+	idx &= ~FKEYIND_KSIZE_MASK;
+	idx |= FKEYIND_KSIZE_256;
+
+	/* Configure the key index (0 to 3) */
+	idx &= ~FKEYIND_KIND_MASK;
+	idx |= FKEYIND_KIND_KEY(key_index);
+
+	writel(idx, &regs->fustrap_fkeyind);
+
+	/* Wait for selection completetion */
+	while (--time > 1) {
+		if (readl(&regs->fustrap_fkeyind) & FKEYIND_KVAL)
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_nibble_parity_ecc_encode                         */
+/*                                                                            */
+/* Parameters:      datain - pointer to decoded data buffer                   */
+/*                  dataout - pointer to encoded data buffer (buffer size     */
+/*                            should be 2 x dataout)                          */
+/*                  size - size of encoded data (decoded data x 2)            */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     Decodes the data according to nibble parity ECC scheme.   */
+/*                  Size specifies the encoded data size.                     */
+/*                  Decodes whole bytes only                                  */
+/*----------------------------------------------------------------------------*/
+void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size)
+{
+	u32 i, idx;
+	u8 E0, E1, E2, E3;
+
+	for (i = 0; i < (size / 2); i++) {
+		E0 = (datain[i] >> 0) & 0x01;
+		E1 = (datain[i] >> 1) & 0x01;
+		E2 = (datain[i] >> 2) & 0x01;
+		E3 = (datain[i] >> 3) & 0x01;
+
+		idx = i * 2;
+		dataout[idx] = datain[i] & 0x0f;
+		dataout[idx] |= (E0 ^ E1) << 4;
+		dataout[idx] |= (E2 ^ E3) << 5;
+		dataout[idx] |= (E0 ^ E2) << 6;
+		dataout[idx] |= (E1 ^ E3) << 7;
+
+		E0 = (datain[i] >> 4) & 0x01;
+		E1 = (datain[i] >> 5) & 0x01;
+		E2 = (datain[i] >> 6) & 0x01;
+		E3 = (datain[i] >> 7) & 0x01;
+
+		idx = i * 2 + 1;
+		dataout[idx] = (datain[i] & 0xf0) >> 4;
+		dataout[idx] |= (E0 ^ E1) << 4;
+		dataout[idx] |= (E2 ^ E3) << 5;
+		dataout[idx] |= (E0 ^ E2) << 6;
+		dataout[idx] |= (E1 ^ E3) << 7;
+	}
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        npcm_otp_majority_rule_ecc_encode                         */
+/*                                                                            */
+/* Parameters:      datain - pointer to decoded data buffer                   */
+/*                  dataout - pointer to encoded data buffer (buffer size     */
+/*                            should be 3 x dataout)                          */
+/*                  size - size of encoded data (decoded data x 3)            */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     Decodes the data according to Major Rule ECC scheme.      */
+/*                  Size specifies the encoded data size.                     */
+/*                  Decodes whole bytes only                                  */
+/*----------------------------------------------------------------------------*/
+void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size)
+{
+	u32 byte;
+	u32 bit;
+	u8 bit_val;
+	u32 decoded_size = size / 3;
+
+	for (byte = 0; byte < decoded_size; byte++) {
+		for (bit = 0; bit < 8; bit++) {
+			bit_val = (datain[byte] >> bit) & 0x01;
+
+			if (bit_val) {
+				dataout[byte] |= (1 << bit);
+				dataout[decoded_size + byte] |= (1 << bit);
+				dataout[decoded_size * 2 + byte] |= (1 << bit);
+			} else {
+				dataout[byte] &= ~(1 << bit);
+				dataout[decoded_size + byte] &= ~(1 << bit);
+				dataout[decoded_size * 2 + byte] &= ~(1 << bit);
+			}
+		}
+	}
+}
+
+/*----------------------------------------------------------------------------*/
+/* Function:        fuse_program_data                                         */
+/*                                                                            */
+/* Parameters:      bank - Storage Array type [input].                        */
+/*                  word - Byte offset in array [input].                      */
+/*                  data - Pointer to data buffer to program.                 */
+/*                  size - Number of bytes to program.                        */
+/* Returns:         none                                                      */
+/* Side effects:                                                              */
+/* Description:     Programs the given byte array (size bytes) to the given   */
+/*                  OTP storage array, starting from offset word.             */
+/*----------------------------------------------------------------------------*/
+int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size)
+{
+	u32 arr = (u32)bank;
+	u32 byte;
+	int rc;
+
+	rc = npcm_otp_check_inputs(bank, word + size - 1);
+	if (rc != 0)
+		return rc;
+
+	for (byte = 0; byte < size; byte++) {
+		u8 val;
+
+		val = data[byte];
+		if (val == 0) // optimization
+			continue;
+
+		rc = npcm_otp_program_byte(arr, word + byte, data[byte]);
+		if (rc != 0)
+			return rc;
+
+		// verify programming of every '1' bit
+		val = 0;
+		npcm_otp_read_byte((u32)bank, byte, &val);
+		if ((data[byte] & ~val) != 0)
+			return -1;
+	}
+
+	return 0;
+}
+
+int fuse_prog_image(u32 bank, uintptr_t address)
+{
+	return fuse_program_data(bank, 0, (u8 *)address, NPCM_OTP_ARR_BYTE_SIZE);
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	int rc = npcm_otp_check_inputs(bank, word);
+
+	if (rc != 0)
+		return rc;
+
+	*val = 0;
+	npcm_otp_read_byte((u32)bank, word, (u8 *)val);
+
+	return 0;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	/* We do not support overriding */
+	return -EINVAL;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	int rc;
+
+	rc = npcm_otp_check_inputs(bank, word);
+	if (rc != 0)
+		return rc;
+
+	return npcm_otp_program_byte(bank, word, (u8)val);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	/* We do not support overriding */
+	return -EINVAL;
+}
+
+static int npcm_otp_bind(struct udevice *dev)
+{
+	struct npcm_otp_regs *regs;
+
+	otp_priv = calloc(1, sizeof(struct npcm_otp_priv));
+	if (!otp_priv)
+		return -ENOMEM;
+
+	regs = dev_remap_addr_index(dev, 0);
+	if (!regs) {
+		printf("Cannot find reg address (arr #0), binding failed\n");
+		return -EINVAL;
+	}
+	otp_priv->regs[0] = regs;
+
+	if (IS_ENABLED(CONFIG_ARCH_NPCM7xx)) {
+		regs = dev_remap_addr_index(dev, 1);
+		if (!regs) {
+			printf("Cannot find reg address (arr #1), binding failed\n");
+			return -EINVAL;
+		}
+		otp_priv->regs[1] = regs;
+	}
+	printf("OTP: NPCM OTP module bind OK\n");
+
+	return 0;
+}
+
+static const struct udevice_id npcm_otp_ids[] = {
+	{ .compatible = "nuvoton,npcm845-otp" },
+	{ .compatible = "nuvoton,npcm750-otp" },
+	{ }
+};
+
+U_BOOT_DRIVER(npcm_otp) = {
+	.name = "npcm_otp",
+	.id = UCLASS_MISC,
+	.of_match = npcm_otp_ids,
+	.priv_auto = sizeof(struct npcm_otp_priv),
+	.bind = npcm_otp_bind,
+};
diff --git a/drivers/misc/nvmem.c b/drivers/misc/nvmem.c
new file mode 100644
index 0000000..5a2bd1f
--- /dev/null
+++ b/drivers/misc/nvmem.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
+ */
+
+#include <common.h>
+#include <i2c_eeprom.h>
+#include <linker_lists.h>
+#include <misc.h>
+#include <nvmem.h>
+#include <rtc.h>
+#include <dm/device_compat.h>
+#include <dm/ofnode.h>
+#include <dm/read.h>
+#include <dm/uclass.h>
+
+int nvmem_cell_read(struct nvmem_cell *cell, void *buf, size_t size)
+{
+	dev_dbg(cell->nvmem, "%s: off=%u size=%zu\n", __func__, cell->offset, size);
+	if (size != cell->size)
+		return -EINVAL;
+
+	switch (cell->nvmem->driver->id) {
+	case UCLASS_I2C_EEPROM:
+		return i2c_eeprom_read(cell->nvmem, cell->offset, buf, size);
+	case UCLASS_MISC: {
+		int ret = misc_read(cell->nvmem, cell->offset, buf, size);
+
+		if (ret < 0)
+			return ret;
+		if (ret != size)
+			return -EIO;
+		return 0;
+	}
+	case UCLASS_RTC:
+		return dm_rtc_read(cell->nvmem, cell->offset, buf, size);
+	default:
+		return -ENOSYS;
+	}
+}
+
+int nvmem_cell_write(struct nvmem_cell *cell, const void *buf, size_t size)
+{
+	dev_dbg(cell->nvmem, "%s: off=%u size=%zu\n", __func__, cell->offset, size);
+	if (size != cell->size)
+		return -EINVAL;
+
+	switch (cell->nvmem->driver->id) {
+	case UCLASS_I2C_EEPROM:
+		return i2c_eeprom_write(cell->nvmem, cell->offset, buf, size);
+	case UCLASS_MISC: {
+		int ret = misc_write(cell->nvmem, cell->offset, buf, size);
+
+		if (ret < 0)
+			return ret;
+		if (ret != size)
+			return -EIO;
+		return 0;
+	}
+	case UCLASS_RTC:
+		return dm_rtc_write(cell->nvmem, cell->offset, buf, size);
+	default:
+		return -ENOSYS;
+	}
+}
+
+/**
+ * nvmem_get_device() - Get an nvmem device for a cell
+ * @node: ofnode of the nvmem device
+ * @cell: Cell to look up
+ *
+ * Try to find a nvmem-compatible device by going through the nvmem interfaces.
+ *
+ * Return:
+ * * 0 on success
+ * * -ENODEV if we didn't find anything
+ * * A negative error if there was a problem looking up the device
+ */
+static int nvmem_get_device(ofnode node, struct nvmem_cell *cell)
+{
+	int i, ret;
+	enum uclass_id ids[] = {
+		UCLASS_I2C_EEPROM,
+		UCLASS_MISC,
+		UCLASS_RTC,
+	};
+
+	for (i = 0; i < ARRAY_SIZE(ids); i++) {
+		ret = uclass_get_device_by_ofnode(ids[i], node, &cell->nvmem);
+		if (!ret)
+			return 0;
+		if (ret != -ENODEV && ret != -EPFNOSUPPORT)
+			return ret;
+	}
+
+	return -ENODEV;
+}
+
+int nvmem_cell_get_by_index(struct udevice *dev, int index,
+			    struct nvmem_cell *cell)
+{
+	fdt_addr_t offset;
+	fdt_size_t size = FDT_SIZE_T_NONE;
+	int ret;
+	struct ofnode_phandle_args args;
+
+	dev_dbg(dev, "%s: index=%d\n", __func__, index);
+
+	ret = dev_read_phandle_with_args(dev, "nvmem-cells", NULL, 0, index,
+					 &args);
+	if (ret)
+		return ret;
+
+	ret = nvmem_get_device(ofnode_get_parent(args.node), cell);
+	if (ret)
+		return ret;
+
+	offset = ofnode_get_addr_size_index_notrans(args.node, 0, &size);
+	if (offset == FDT_ADDR_T_NONE || size == FDT_SIZE_T_NONE) {
+		dev_dbg(cell->nvmem, "missing address or size for %s\n",
+			ofnode_get_name(args.node));
+		return -EINVAL;
+	}
+
+	cell->offset = offset;
+	cell->size = size;
+	return 0;
+}
+
+int nvmem_cell_get_by_name(struct udevice *dev, const char *name,
+			   struct nvmem_cell *cell)
+{
+	int index;
+
+	dev_dbg(dev, "%s, name=%s\n", __func__, name);
+
+	index = dev_read_stringlist_search(dev, "nvmem-cell-names", name);
+	if (index < 0)
+		return index;
+
+	return nvmem_cell_get_by_index(dev, index, cell);
+}
diff --git a/drivers/misc/qfw_sandbox.c b/drivers/misc/qfw_sandbox.c
index b09974d..1002df7 100644
--- a/drivers/misc/qfw_sandbox.c
+++ b/drivers/misc/qfw_sandbox.c
@@ -48,7 +48,7 @@ static void qfw_sandbox_read_entry_dma(struct udevice *dev, struct qfw_dma *dma)
 {
 	u16 entry;
 	u32 control = be32_to_cpu(dma->control);
-	void *address = (void *)be64_to_cpu(dma->address);
+	void *address = (void *)(uintptr_t)be64_to_cpu(dma->address);
 	u32 length = be32_to_cpu(dma->length);
 	struct qfw_sandbox_plat *plat = dev_get_plat(dev);
 	struct fw_cfg_file *file;
diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c
index f14d6e2..b816503 100644
--- a/drivers/misc/stm32_rcc.c
+++ b/drivers/misc/stm32_rcc.c
@@ -39,6 +39,11 @@ struct stm32_rcc_clk stm32_rcc_clk_mp1 = {
 	.soc = STM32MP1,
 };
 
+struct stm32_rcc_clk stm32_rcc_clk_mp13 = {
+	.drv_name = "stm32mp13_clk",
+	.soc = STM32MP1,
+};
+
 static int stm32_rcc_bind(struct udevice *dev)
 {
 	struct udevice *child;
@@ -79,6 +84,7 @@ static const struct udevice_id stm32_rcc_ids[] = {
 	{.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 },
 	{.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 },
 	{.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 },
+	{.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 },
 	{ }
 };
 
diff --git a/drivers/misc/test_drv.c b/drivers/misc/test_drv.c
index 5d72982..9276182 100644
--- a/drivers/misc/test_drv.c
+++ b/drivers/misc/test_drv.c
@@ -108,8 +108,10 @@ UCLASS_DRIVER(testbus) = {
 	.child_pre_probe = testbus_child_pre_probe_uclass,
 	.child_post_probe = testbus_child_post_probe_uclass,
 
-	/* This is for dtoc testing only */
-	.per_device_plat_auto   = sizeof(struct dm_test_uclass_priv),
+	.per_device_auto   = sizeof(struct dm_test_uclass_priv),
+
+	/* Note: this is for dtoc testing as well as tags*/
+	.per_device_plat_auto   = sizeof(struct dm_test_uclass_plat),
 };
 
 static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5e2921c..6ff00a7 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -123,6 +123,7 @@ config MMC_IO_VOLTAGE
 
 config SPL_MMC_IO_VOLTAGE
 	bool "Support IO voltage configuration in SPL"
+	depends on SPL_MMC
 	help
 	  IO voltage configuration allows selecting the voltage level of the IO
 	  lines (not the level of main supply). This is required for UHS
@@ -153,6 +154,7 @@ config MMC_HS400_ES_SUPPORT
 
 config SPL_MMC_HS400_ES_SUPPORT
 	bool "enable HS400 Enhanced Strobe support in SPL"
+	depends on SPL_MMC
 	help
 	  The HS400 Enhanced Strobe mode is support by some eMMC. The bus
 	  frequency is up to 200MHz. This mode does not tune the IO.
@@ -166,6 +168,7 @@ config MMC_HS400_SUPPORT
 
 config SPL_MMC_HS400_SUPPORT
 	bool "enable HS400 support in SPL"
+	depends on SPL_MMC
 	select SPL_MMC_HS200_SUPPORT
 	help
 	  The HS400 mode is support by some eMMC. The bus frequency is up to
@@ -179,6 +182,7 @@ config MMC_HS200_SUPPORT
 
 config SPL_MMC_HS200_SUPPORT
 	bool "enable HS200 support in SPL"
+	depends on SPL_MMC
 	help
 	  The HS200 mode is support by some eMMC. The bus frequency is up to
 	  200MHz. This mode requires tuning the IO.
@@ -342,14 +346,6 @@ config MVEBU_MMC
 
 	  If unsure, say N.
 
-config PXA_MMC_GENERIC
-	bool "Support for MMC controllers on PXA"
-	help
-	  This selects MMC controllers on PXA.
-	  If you are on a PXA architecture, say Y here.
-
-	  If unsure, say N.
-
 config MMC_OMAP_HS
 	bool "TI OMAP High Speed Multimedia Card Interface support"
 	select DM_REGULATOR_PBIAS if DM_MMC && DM_REGULATOR
@@ -478,17 +474,31 @@ config MMC_SDHCI_ADMA
 
 config SPL_MMC_SDHCI_ADMA
 	bool "Support SDHCI ADMA2 in SPL"
-	depends on MMC_SDHCI
+	depends on SPL_MMC && MMC_SDHCI
 	select MMC_SDHCI_ADMA_HELPERS
 	help
 	  This enables support for the ADMA (Advanced DMA) defined
 	  in the SD Host Controller Standard Specification Version 3.00 in SPL.
 
+config FIXED_SDHCI_ALIGNED_BUFFER
+	hex "SDRAM address for fixed buffer"
+	depends on SPL && MVEBU_SPL_BOOT_DEVICE_MMC
+	default 0x00180000
+	help
+	  On the Marvell Armada 38x when the SPL runs it located in internal
+	  SRAM which is the L2 cache locked to memory. When the MMC buffers
+	  are located on the stack (or bss), the SDIO controller (SDHCI) can't
+	  write into this L2 cache memory.
+
+	  This specifies the address of a fixed buffer located in SDRAM that
+	  will be used for all SDHCI transfers in the SPL.
+
 config MMC_SDHCI_ASPEED
 	bool "Aspeed SDHCI controller"
 	depends on ARCH_ASPEED
 	depends on DM_MMC
 	depends on MMC_SDHCI
+	select MISC
 	help
 	  Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
 	  SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
@@ -826,6 +836,15 @@ config FSL_ESDHC_VS33_NOT_SUPPORT
 	  For eSDHC, power supply is through peripheral circuit. 3.3V support is
 	  common. Select this if 3.3V power supply not supported.
 
+config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH
+	int
+	depends on FSL_ESDHC
+	default 1
+
+config ESDHC_DETECT_QUIRK
+	bool "QIXIS-based eSDHC quirk detection"
+	depends on FSL_ESDHC && FSL_QIXIS
+
 config FSL_ESDHC_IMX
 	bool "Freescale/NXP i.MX eSDHC controller support"
 	help
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 9627509..7c42432 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_MMC_MXS)			+= mxsmmc.o
 obj-$(CONFIG_MMC_OCTEONTX)		+= octeontx_hsmmc.o
 obj-$(CONFIG_MMC_OWL)			+= owl_mmc.o
 obj-$(CONFIG_MMC_PCI)			+= pci_mmc.o
-obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
 obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o
 obj-$(CONFIG_MMC_SANDBOX)		+= sandbox_mmc.o
 obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 4305967..42a6134 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -670,6 +670,10 @@ static const struct udevice_id am654_sdhci_ids[] = {
 		.compatible = "ti,am64-sdhci-4bit",
 		.data = (ulong)&sdhci_am64_4bit_drvdata,
 	},
+	{
+		.compatible = "ti,am62-sdhci",
+		.data = (ulong)&sdhci_am64_4bit_drvdata,
+	},
 	{ }
 };
 
diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
index 4537315..9d79bf5 100644
--- a/drivers/mmc/aspeed_sdhci.c
+++ b/drivers/mmc/aspeed_sdhci.c
@@ -10,6 +10,7 @@
 #include <malloc.h>
 #include <sdhci.h>
 #include <linux/err.h>
+#include <dm/lists.h>
 
 struct aspeed_sdhci_plat {
 	struct mmc_config cfg;
@@ -26,12 +27,16 @@ static int aspeed_sdhci_probe(struct udevice *dev)
 	int ret;
 
 	ret = clk_get_by_index(dev, 0, &clk);
-	if (ret)
+	if (ret) {
+		debug("%s: clock get failed %d\n", __func__, ret);
 		return ret;
+	}
 
 	ret = clk_enable(&clk);
-	if (ret)
+	if (ret) {
+		debug("%s: clock enable failed %d\n", __func__, ret);
 		goto free;
+	}
 
 	host->name = dev->name;
 	host->ioaddr = dev_read_addr_ptr(dev);
@@ -39,6 +44,7 @@ static int aspeed_sdhci_probe(struct udevice *dev)
 	max_clk = clk_get_rate(&clk);
 	if (IS_ERR_VALUE(max_clk)) {
 		ret = max_clk;
+		debug("%s: clock rate get failed %d\n", __func__, ret);
 		goto err;
 	}
 
@@ -89,3 +95,38 @@ U_BOOT_DRIVER(aspeed_sdhci_drv) = {
 	.priv_auto	= sizeof(struct sdhci_host),
 	.plat_auto	= sizeof(struct aspeed_sdhci_plat),
 };
+
+
+static int aspeed_sdc_probe(struct udevice *parent)
+{
+	struct clk clk;
+	int ret;
+
+	ret = clk_get_by_index(parent, 0, &clk);
+	if (ret) {
+		debug("%s: clock get failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = clk_enable(&clk);
+	if (ret) {
+		debug("%s: clock enable failed %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id aspeed_sdc_ids[] = {
+	{ .compatible = "aspeed,ast2400-sd-controller" },
+	{ .compatible = "aspeed,ast2500-sd-controller" },
+	{ .compatible = "aspeed,ast2600-sd-controller" },
+	{ }
+};
+
+U_BOOT_DRIVER(aspeed_sdc_drv) = {
+	.name		= "aspeed_sdc",
+	.id		= UCLASS_MISC,
+	.of_match	= aspeed_sdc_ids,
+	.probe		= aspeed_sdc_probe,
+};
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index fdf2cc2..b49a7b4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -30,6 +30,7 @@
 #include <linux/iopoll.h>
 #include <linux/dma-mapping.h>
 #include <sdhci.h>
+#include "../../board/freescale/common/qixis.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -773,7 +774,7 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
 	struct fsl_esdhc *regs = priv->esdhc_regs;
 
 #ifdef CONFIG_ESDHC_DETECT_QUIRK
-	if (CONFIG_ESDHC_DETECT_QUIRK)
+	if (qixis_esdhc_detect_quirk())
 		return 1;
 #endif
 	if (esdhc_read32(&regs->prsstat) & PRSSTAT_CINS)
@@ -946,9 +947,8 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
 	} else if (cfg->max_bus_width == 1) {
 		mmc_cfg->host_caps |= MMC_MODE_1BIT;
 	} else {
-		mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
-				      MMC_MODE_8BIT;
-		printf("No max bus width provided. Assume 8-bit supported.\n");
+		mmc_cfg->host_caps |= MMC_MODE_1BIT;
+		printf("No max bus width provided. Fallback to 1-bit mode.\n");
 	}
 
 	if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
@@ -972,6 +972,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis)
 
 	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+	cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH;
 	/* Prefer peripheral clock which provides higher frequency. */
 	if (gd->arch.sdhc_per_clk)
 		cfg->sdhc_clk = gd->arch.sdhc_per_clk;
diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c
deleted file mode 100644
index 2b45549..0000000
--- a/drivers/mmc/pxa_mmc_gen.c
+++ /dev/null
@@ -1,536 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- *
- * Modified to add driver model (DM) support
- * Copyright (C) 2019 Marcel Ziswiler <marcel@ziswiler.com>
- *
- * Loosely based on the old code and Linux's PXA MMC driver
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <dm.h>
-#include <dm/platform_data/pxa_mmc_gen.h>
-#include <malloc.h>
-#include <mmc.h>
-
-/* PXAMMC Generic default config for various CPUs */
-#if defined(CONFIG_CPU_PXA25X)
-#define PXAMMC_FIFO_SIZE	1
-#define PXAMMC_MIN_SPEED	312500
-#define PXAMMC_MAX_SPEED	20000000
-#define PXAMMC_HOST_CAPS	(0)
-#elif defined(CONFIG_CPU_PXA27X)
-#define PXAMMC_CRC_SKIP
-#define PXAMMC_FIFO_SIZE	32
-#define PXAMMC_MIN_SPEED	304000
-#define PXAMMC_MAX_SPEED	19500000
-#define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT)
-#elif defined(CONFIG_CPU_MONAHANS)
-#define PXAMMC_FIFO_SIZE	32
-#define PXAMMC_MIN_SPEED	304000
-#define PXAMMC_MAX_SPEED	26000000
-#define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT | MMC_MODE_HS)
-#else
-#error "This CPU isn't supported by PXA MMC!"
-#endif
-
-#define MMC_STAT_ERRORS							\
-	(MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN |	\
-	MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE |		\
-	MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
-
-/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
-#define PXA_MMC_TIMEOUT	100
-
-struct pxa_mmc_priv {
-	struct pxa_mmc_regs *regs;
-};
-
-/* Wait for bit to be set */
-static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-	struct pxa_mmc_regs *regs = priv->regs;
-	unsigned int timeout = PXA_MMC_TIMEOUT;
-
-	/* Wait for bit to be set */
-	while (--timeout) {
-		if (readl(&regs->stat) & mask)
-			break;
-		udelay(10);
-	}
-
-	if (!timeout)
-		return -ETIMEDOUT;
-
-	return 0;
-}
-
-static int pxa_mmc_stop_clock(struct mmc *mmc)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-	struct pxa_mmc_regs *regs = priv->regs;
-	unsigned int timeout = PXA_MMC_TIMEOUT;
-
-	/* If the clock aren't running, exit */
-	if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
-		return 0;
-
-	/* Tell the controller to turn off the clock */
-	writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);
-
-	/* Wait until the clock are off */
-	while (--timeout) {
-		if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
-			break;
-		udelay(10);
-	}
-
-	/* The clock refused to stop, scream and die a painful death */
-	if (!timeout)
-		return -ETIMEDOUT;
-
-	/* The clock stopped correctly */
-	return 0;
-}
-
-static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
-			     uint32_t cmdat)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-	struct pxa_mmc_regs *regs = priv->regs;
-	int ret;
-
-	/* The card can send a "busy" response */
-	if (cmd->resp_type & MMC_RSP_BUSY)
-		cmdat |= MMC_CMDAT_BUSY;
-
-	/* Inform the controller about response type */
-	switch (cmd->resp_type) {
-	case MMC_RSP_R1:
-	case MMC_RSP_R1b:
-		cmdat |= MMC_CMDAT_R1;
-		break;
-	case MMC_RSP_R2:
-		cmdat |= MMC_CMDAT_R2;
-		break;
-	case MMC_RSP_R3:
-		cmdat |= MMC_CMDAT_R3;
-		break;
-	default:
-		break;
-	}
-
-	/* Load command and it's arguments into the controller */
-	writel(cmd->cmdidx, &regs->cmd);
-	writel(cmd->cmdarg >> 16, &regs->argh);
-	writel(cmd->cmdarg & 0xffff, &regs->argl);
-	writel(cmdat, &regs->cmdat);
-
-	/* Start the controller clock and wait until they are started */
-	writel(MMC_STRPCL_START_CLK, &regs->strpcl);
-
-	ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
-	if (ret)
-		return ret;
-
-	/* Correct and happy end */
-	return 0;
-}
-
-static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-	struct pxa_mmc_regs *regs = priv->regs;
-	u32 a, b, c;
-	int i;
-	int stat;
-
-	/* Read the controller status */
-	stat = readl(&regs->stat);
-
-	/*
-	 * Linux says:
-	 * Did I mention this is Sick. We always need to
-	 * discard the upper 8 bits of the first 16-bit word.
-	 */
-	a = readl(&regs->res) & 0xffff;
-	for (i = 0; i < 4; i++) {
-		b = readl(&regs->res) & 0xffff;
-		c = readl(&regs->res) & 0xffff;
-		cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
-		a = c;
-	}
-
-	/* The command response didn't arrive */
-	if (stat & MMC_STAT_TIME_OUT_RESPONSE) {
-		return -ETIMEDOUT;
-	} else if (stat & MMC_STAT_RES_CRC_ERROR &&
-		   cmd->resp_type & MMC_RSP_CRC) {
-#ifdef PXAMMC_CRC_SKIP
-		if (cmd->resp_type & MMC_RSP_136 &&
-		    cmd->response[0] & (1 << 31))
-			printf("Ignoring CRC, this may be dangerous!\n");
-		else
-#endif
-		return -EILSEQ;
-	}
-
-	/* The command response was successfully read */
-	return 0;
-}
-
-static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-	struct pxa_mmc_regs *regs = priv->regs;
-	u32 len;
-	u32 *buf = (uint32_t *)data->dest;
-	int size;
-	int ret;
-
-	len = data->blocks * data->blocksize;
-
-	while (len) {
-		/* The controller has data ready */
-		if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
-			size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
-			len -= size;
-			size /= 4;
-
-			/* Read data into the buffer */
-			while (size--)
-				*buf++ = readl(&regs->rxfifo);
-		}
-
-		if (readl(&regs->stat) & MMC_STAT_ERRORS)
-			return -EIO;
-	}
-
-	/* Wait for the transmission-done interrupt */
-	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-	struct pxa_mmc_regs *regs = priv->regs;
-	u32 len;
-	u32 *buf = (uint32_t *)data->src;
-	int size;
-	int ret;
-
-	len = data->blocks * data->blocksize;
-
-	while (len) {
-		/* The controller is ready to receive data */
-		if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
-			size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
-			len -= size;
-			size /= 4;
-
-			while (size--)
-				writel(*buf++, &regs->txfifo);
-
-			if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
-				writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
-		}
-
-		if (readl(&regs->stat) & MMC_STAT_ERRORS)
-			return -EIO;
-	}
-
-	/* Wait for the transmission-done interrupt */
-	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
-	if (ret)
-		return ret;
-
-	/* Wait until the data are really written to the card */
-	ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static int pxa_mmc_send_cmd_common(struct pxa_mmc_priv *priv, struct mmc *mmc,
-				   struct mmc_cmd *cmd, struct mmc_data *data)
-{
-	struct pxa_mmc_regs *regs = priv->regs;
-	u32 cmdat = 0;
-	int ret;
-
-	/* Stop the controller */
-	ret = pxa_mmc_stop_clock(mmc);
-	if (ret)
-		return ret;
-
-	/* If we're doing data transfer, configure the controller accordingly */
-	if (data) {
-		writel(data->blocks, &regs->nob);
-		writel(data->blocksize, &regs->blklen);
-		/* This delay can be optimized, but stick with max value */
-		writel(0xffff, &regs->rdto);
-		cmdat |= MMC_CMDAT_DATA_EN;
-		if (data->flags & MMC_DATA_WRITE)
-			cmdat |= MMC_CMDAT_WRITE;
-	}
-
-	/* Run in 4bit mode if the card can do it */
-	if (mmc->bus_width == 4)
-		cmdat |= MMC_CMDAT_SD_4DAT;
-
-	/* Execute the command */
-	ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
-	if (ret)
-		return ret;
-
-	/* Wait until the command completes */
-	ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
-	if (ret)
-		return ret;
-
-	/* Read back the result */
-	ret = pxa_mmc_cmd_done(mmc, cmd);
-	if (ret)
-		return ret;
-
-	/* In case there was a data transfer scheduled, do it */
-	if (data) {
-		if (data->flags & MMC_DATA_WRITE)
-			pxa_mmc_do_write_xfer(mmc, data);
-		else
-			pxa_mmc_do_read_xfer(mmc, data);
-	}
-
-	return 0;
-}
-
-static int pxa_mmc_set_ios_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
-{
-	struct pxa_mmc_regs *regs = priv->regs;
-	u32 tmp;
-	u32 pxa_mmc_clock;
-
-	if (!mmc->clock) {
-		pxa_mmc_stop_clock(mmc);
-		return 0;
-	}
-
-	/* PXA3xx can do 26MHz with special settings. */
-	if (mmc->clock == 26000000) {
-		writel(0x7, &regs->clkrt);
-		return 0;
-	}
-
-	/* Set clock to the card the usual way. */
-	pxa_mmc_clock = 0;
-	tmp = mmc->cfg->f_max / mmc->clock;
-	tmp += tmp % 2;
-
-	while (tmp > 1) {
-		pxa_mmc_clock++;
-		tmp >>= 1;
-	}
-
-	writel(pxa_mmc_clock, &regs->clkrt);
-
-	return 0;
-}
-
-static int pxa_mmc_init_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
-{
-	struct pxa_mmc_regs *regs = priv->regs;
-
-	/* Make sure the clock are stopped */
-	pxa_mmc_stop_clock(mmc);
-
-	/* Turn off SPI mode */
-	writel(0, &regs->spi);
-
-	/* Set up maximum timeout to wait for command response */
-	writel(MMC_RES_TO_MAX_MASK, &regs->resto);
-
-	/* Mask all interrupts */
-	writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
-	       &regs->i_mask);
-
-	return 0;
-}
-
-#if !CONFIG_IS_ENABLED(DM_MMC)
-static int pxa_mmc_init(struct mmc *mmc)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-
-	return pxa_mmc_init_common(priv, mmc);
-}
-
-static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
-			   struct mmc_data *data)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-
-	return pxa_mmc_send_cmd_common(priv, mmc, cmd, data);
-}
-
-static int pxa_mmc_set_ios(struct mmc *mmc)
-{
-	struct pxa_mmc_priv *priv = mmc->priv;
-
-	return pxa_mmc_set_ios_common(priv, mmc);
-}
-
-static const struct mmc_ops pxa_mmc_ops = {
-	.send_cmd	= pxa_mmc_request,
-	.set_ios	= pxa_mmc_set_ios,
-	.init		= pxa_mmc_init,
-};
-
-static struct mmc_config pxa_mmc_cfg = {
-	.name		= "PXA MMC",
-	.ops		= &pxa_mmc_ops,
-	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
-	.f_max		= PXAMMC_MAX_SPEED,
-	.f_min		= PXAMMC_MIN_SPEED,
-	.host_caps	= PXAMMC_HOST_CAPS,
-	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-int pxa_mmc_register(int card_index)
-{
-	struct mmc *mmc;
-	struct pxa_mmc_priv *priv;
-	u32 reg;
-	int ret = -ENOMEM;
-
-	priv = malloc(sizeof(struct pxa_mmc_priv));
-	if (!priv)
-		goto err0;
-
-	memset(priv, 0, sizeof(*priv));
-
-	switch (card_index) {
-	case 0:
-		priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
-		break;
-	case 1:
-		priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
-		break;
-	default:
-		ret = -EINVAL;
-		printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
-		       card_index);
-		goto err1;
-	}
-
-#ifndef	CONFIG_CPU_MONAHANS	/* PXA2xx */
-	reg = readl(CKEN);
-	reg |= CKEN12_MMC;
-	writel(reg, CKEN);
-#else				/* PXA3xx */
-	reg = readl(CKENA);
-	reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
-	writel(reg, CKENA);
-#endif
-
-	mmc = mmc_create(&pxa_mmc_cfg, priv);
-	if (!mmc)
-		goto err1;
-
-	return 0;
-
-err1:
-	free(priv);
-err0:
-	return ret;
-}
-#else /* !CONFIG_IS_ENABLED(DM_MMC) */
-static int pxa_mmc_probe(struct udevice *dev)
-{
-	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-	struct pxa_mmc_plat *plat = dev_get_plat(dev);
-	struct mmc_config *cfg = &plat->cfg;
-	struct mmc *mmc = &plat->mmc;
-	struct pxa_mmc_priv *priv = dev_get_priv(dev);
-	u32 reg;
-
-	upriv->mmc = mmc;
-
-	cfg->b_max	= CONFIG_SYS_MMC_MAX_BLK_COUNT;
-	cfg->f_max	= PXAMMC_MAX_SPEED;
-	cfg->f_min	= PXAMMC_MIN_SPEED;
-	cfg->host_caps	= PXAMMC_HOST_CAPS;
-	cfg->name	= dev->name;
-	cfg->voltages	= MMC_VDD_32_33 | MMC_VDD_33_34;
-
-	mmc->priv = priv;
-
-	priv->regs = plat->base;
-
-#ifndef	CONFIG_CPU_MONAHANS	/* PXA2xx */
-	reg = readl(CKEN);
-	reg |= CKEN12_MMC;
-	writel(reg, CKEN);
-#else				/* PXA3xx */
-	reg = readl(CKENA);
-	reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
-	writel(reg, CKENA);
-#endif
-
-	return pxa_mmc_init_common(priv, mmc);
-}
-
-static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
-			    struct mmc_data *data)
-{
-	struct pxa_mmc_plat *plat = dev_get_plat(dev);
-	struct pxa_mmc_priv *priv = dev_get_priv(dev);
-
-	return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
-}
-
-static int pxa_mmc_set_ios(struct udevice *dev)
-{
-	struct pxa_mmc_plat *plat = dev_get_plat(dev);
-	struct pxa_mmc_priv *priv = dev_get_priv(dev);
-
-	return pxa_mmc_set_ios_common(priv, &plat->mmc);
-}
-
-static const struct dm_mmc_ops pxa_mmc_ops = {
-	.get_cd			= NULL,
-	.send_cmd		= pxa_mmc_send_cmd,
-	.set_ios		= pxa_mmc_set_ios,
-};
-
-#if CONFIG_IS_ENABLED(BLK)
-static int pxa_mmc_bind(struct udevice *dev)
-{
-	struct pxa_mmc_plat *plat = dev_get_plat(dev);
-
-	return mmc_bind(dev, &plat->mmc, &plat->cfg);
-}
-#endif
-
-U_BOOT_DRIVER(pxa_mmc) = {
-#if CONFIG_IS_ENABLED(BLK)
-	.bind	= pxa_mmc_bind,
-#endif
-	.id	= UCLASS_MMC,
-	.name	= "pxa_mmc",
-	.ops	= &pxa_mmc_ops,
-	.priv_auto	= sizeof(struct pxa_mmc_priv),
-	.probe	= pxa_mmc_probe,
-};
-#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c
index 44bfc91..81b0760 100644
--- a/drivers/mmc/stm32_sdmmc2.c
+++ b/drivers/mmc/stm32_sdmmc2.c
@@ -514,10 +514,12 @@ retry_cmd:
  */
 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
 {
-	/* Reset */
-	reset_assert(&priv->reset_ctl);
-	udelay(2);
-	reset_deassert(&priv->reset_ctl);
+	if (reset_valid(&priv->reset_ctl)) {
+		/* Reset */
+		reset_assert(&priv->reset_ctl);
+		udelay(2);
+		reset_deassert(&priv->reset_ctl);
+	}
 
 	/* init the needed SDMMC register after reset */
 	writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
@@ -735,7 +737,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
 
 	ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 	if (ret)
-		goto clk_disable;
+		dev_dbg(dev, "No reset provided\n");
 
 	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 			     GPIOD_IS_IN);
@@ -755,8 +757,6 @@ static int stm32_sdmmc2_probe(struct udevice *dev)
 	stm32_sdmmc2_reset(priv);
 	return 0;
 
-clk_disable:
-	clk_disable(&priv->clk);
 clk_free:
 	clk_free(&priv->clk);
 
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 4088267..3d1f6e4 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -48,6 +48,35 @@ config FLASH_CFI_DRIVER
 	  option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
 	  for more information on CFI.
 
+choice
+	prompt "Data-width of the flash device"
+	depends on FLASH_CFI_DRIVER
+	default SYS_FLASH_CFI_WIDTH_8BIT
+
+config SYS_FLASH_CFI_WIDTH_8BIT
+	bool "Data-width of the device is 8-bit"
+
+config SYS_FLASH_CFI_WIDTH_16BIT
+	bool "Data-width of the device is 16-bit"
+
+config SYS_FLASH_CFI_WIDTH_32BIT
+	bool "Data-width of the device is 32-bit"
+
+config SYS_FLASH_CFI_WIDTH_64BIT
+	bool "Data-width of the device is 64-bit"
+
+endchoice
+
+config SYS_FLASH_CFI_WIDTH
+	hex
+	depends on FLASH_CFI_DRIVER
+	default 0x1 if SYS_FLASH_CFI_WIDTH_8BIT
+	default 0x2 if SYS_FLASH_CFI_WIDTH_16BIT
+	default 0x4 if SYS_FLASH_CFI_WIDTH_32BIT
+	default 0x8 if SYS_FLASH_CFI_WIDTH_64BIT
+	help
+	  This must be kept in sync with the table in include/flash.h
+
 config CFI_FLASH
 	bool "Enable Driver Model for CFI Flash driver"
 	depends on DM_MTD
@@ -67,6 +96,10 @@ config CFI_FLASH_USE_WEAK_ACCESSORS
 	  Enable this option to allow for the flash_{read,write}{8,16,32,64}
 	  functions to be overridden by the platform.
 
+config SYS_CFI_FLASH_STATUS_POLL
+	bool "Poll status on AMD flash chips"
+	depends on FLASH_CFI_DRIVER
+
 config SYS_FLASH_USE_BUFFER_WRITE
 	bool "Enable buffered writes to flash"
 	depends on FLASH_CFI_DRIVER
@@ -135,6 +168,9 @@ config STM32_FLASH
 	 This is the driver of embedded flash for some STMicroelectronics
 	 STM32 MCU.
 
+config SAMSUNG_ONENAND
+	bool "Samsung OneNAND driver support"
+
 config USE_SYS_MAX_FLASH_BANKS
 	bool "Enable Max number of Flash memory banks"
 	help
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index aae3ea0..4950410 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -68,13 +68,6 @@ static uint flash_verbose = 1;
 
 flash_info_t flash_info[CFI_MAX_FLASH_BANKS];	/* FLASH chips info */
 
-/*
- * Check if chip width is defined. If not, start detecting with 8bit.
- */
-#ifndef CONFIG_SYS_FLASH_CFI_WIDTH
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#endif
-
 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 #define __maybe_weak __weak
 #else
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index d077897..56aa58b 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -902,7 +902,8 @@ int add_mtd_partitions_of(struct mtd_info *master)
 	ofnode_for_each_subnode(child, parts) {
 		struct mtd_partition part = { 0 };
 		struct mtd_info *slave;
-		fdt_addr_t offset, size;
+		fdt_addr_t offset;
+		fdt_size_t size;
 
 		if (!ofnode_is_available(child))
 			continue;
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index d75f371..190300f 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -23,6 +23,9 @@ config TPL_SYS_NAND_SELF_INIT
 	  This option, if enabled, provides more flexible and linux-like
 	  NAND initialization process, in SPL.
 
+config TPL_NAND_INIT
+	bool
+
 config SYS_NAND_DRIVER_ECC_LAYOUT
 	bool "Omit standard ECC layouts to save space"
 	help
@@ -70,6 +73,7 @@ config PMECC_SECTOR_SIZE
 
 config SPL_GENERATE_ATMEL_PMECC_HEADER
 	bool "Atmel PMECC Header Generation"
+	depends on SPL
 	select ATMEL_NAND_HWECC
 	select ATMEL_NAND_HW_PMECC
 	help
@@ -165,6 +169,7 @@ config NAND_FSL_ELBC_DT
 config NAND_FSL_IFC
 	bool "Support Freescale Integrated Flash Controller NAND driver"
 	select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
+	select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
 	select SPL_SYS_NAND_SELF_INIT
 	select SYS_NAND_SELF_INIT
 	select FSL_IFC
@@ -643,7 +648,7 @@ config SYS_NAND_U_BOOT_OFFS_REDUND
 
 config SPL_NAND_AM33XX_BCH
 	bool "Enables SPL-NAND driver which supports ELM based"
-	depends on NAND_OMAP_GPMC && !OMAP34XX
+	depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
 	default y
         help
 	  Hardware ECC correction. This is useful for platforms which have ELM
@@ -654,6 +659,7 @@ config SPL_NAND_AM33XX_BCH
 
 config SPL_NAND_DENALI
 	bool "Support Denali NAND controller for SPL"
+	depends on SPL_NAND_SUPPORT
 	help
 	  This is a small implementation of the Denali NAND controller
 	  for use on SPL.
@@ -669,7 +675,7 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES
 
 config SPL_NAND_SIMPLE
 	bool "Use simple SPL NAND driver"
-	depends on !SPL_NAND_AM33XX_BCH
+	depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
 	help
 	  Support for NAND boot using simple NAND drivers that
 	  expose the cmd_ctrl() interface.
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 6ec3581..e3f6b90 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
 obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
 obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o
 obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o
-obj-$(CONFIG_SPL_NAND_INIT) += nand.o
+obj-$(CONFIG_TPL_NAND_INIT) += nand.o
 ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
 obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
 endif
diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index e734139..48a3687 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -668,7 +668,7 @@ static void fsl_elbc_ctrl_init(void)
 	elbc_ctrl->addr = NULL;
 }
 
-static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node)
+static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev)
 {
 	struct mtd_info *mtd;
 	struct nand_chip *nand;
@@ -716,7 +716,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node)
 	elbc_ctrl->chips[priv->bank] = priv;
 
 	/* fill in nand_chip structure */
-	nand->flash_node = flash_node;
+	mtd->dev = dev;
+	nand->flash_node = dev ? dev_ofnode(dev) : ofnode_null();
 
 	/* set up function call table */
 	nand->read_byte = fsl_elbc_read_byte;
@@ -744,7 +745,11 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node)
 		return ret;
 
 	/* If nand_scan_ident() has not selected ecc.mode, do it now */
-	if (nand->ecc.mode == NAND_ECC_NONE) {
+	if (nand->ecc.mode == 0
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	    && !ofnode_read_string(nand->flash_node, "nand-ecc-mode")
+#endif
+	   ) {
 		/* If CS Base Register selects full hardware ECC then use it */
 		if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 			nand->ecc.mode = NAND_ECC_HW;
@@ -827,14 +832,14 @@ void board_nand_init(void)
 	int i;
 
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		fsl_elbc_chip_init(i, (u8 *)base_address[i], ofnode_null());
+		fsl_elbc_chip_init(i, (u8 *)base_address[i], NULL);
 }
 
 #else
 
 static int fsl_elbc_nand_probe(struct udevice *dev)
 {
-	return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev_ofnode(dev));
+	return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev);
 }
 
 static const struct udevice_id fsl_elbc_nand_dt_ids[] = {
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index b7e3741..4d11922 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -297,7 +297,7 @@ void nand_boot(void)
 	uboot();
 }
 
-#ifndef CONFIG_SPL_NAND_INIT
+#ifndef CONFIG_TPL_NAND_INIT
 void nand_init(void)
 {
 }
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 5d197ce..a92c625 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2010
- * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  *
  * (C) Copyright 2012
- * Amit Virdi, ST Microelectronics, amit.virdi@st.com.
+ * Amit Virdi, STMicroelectronics, amit.virdi@st.com.
  */
 
 #include <common.h>
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 6f81257..e8ece0a 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -974,6 +974,22 @@ static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
 	return ret;
 }
 
+static int nand_onfi_set_timings(struct mtd_info *mtd, struct nand_chip *chip)
+{
+	if (!chip->onfi_version ||
+	    !(le16_to_cpu(chip->onfi_params.opt_cmd)
+	      & ONFI_OPT_CMD_SET_GET_FEATURES))
+		return 0;
+
+	u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
+		chip->onfi_timing_mode_default,
+	};
+
+	return chip->onfi_set_features(mtd, chip,
+				       ONFI_FEATURE_ADDR_TIMING_MODE,
+				       tmode_param);
+}
+
 /**
  * nand_setup_data_interface - Setup the best data interface and timings
  * @chip: The NAND chip
@@ -999,17 +1015,9 @@ static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
 	 * Ensure the timing mode has been changed on the chip side
 	 * before changing timings on the controller side.
 	 */
-	if (chip->onfi_version) {
-		u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
-			chip->onfi_timing_mode_default,
-		};
-
-		ret = chip->onfi_set_features(mtd, chip,
-				ONFI_FEATURE_ADDR_TIMING_MODE,
-				tmode_param);
-		if (ret)
-			goto err;
-	}
+	ret = nand_onfi_set_timings(mtd, chip);
+	if (ret)
+		goto err;
 
 	ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
 err:
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index f350c7e..f83876c 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -248,7 +248,7 @@ config SPI_FLASH_MTD
 
 config SPL_SPI_FLASH_MTD
 	bool "SPI flash MTD support for SPL"
-	depends on SPI_FLASH
+	depends on SPI_FLASH && SPL
 	help
           Enable the MTD support for the SPI flash layer in SPL.
 
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7050ddc..67278c4 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = {
 	/* EON -- en25xxx */
 	{ INFO("en25q32b",   0x1c3016, 0, 64 * 1024,   64, 0) },
 	{ INFO("en25q64",    0x1c3017, 0, 64 * 1024,  128, SECT_4K) },
+	{ INFO("en25q128b",  0x1c3018, 0, 64 * 1024,  256, 0) },
 	{ INFO("en25qh128",  0x1c7018, 0, 64 * 1024,  256, 0) },
 	{ INFO("en25s64",    0x1c3817, 0, 64 * 1024,  128, SECT_4K) },
 #endif
@@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = {
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
+	{
+		INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
+		     SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
+	},
 #endif
 #ifdef CONFIG_SPI_FLASH_ISSI		/* ISSI */
 	/* ISSI */
 	{ INFO("is25lq040b", 0x9d4013, 0, 64 * 1024,   8,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25lp008", 0x9d6014, 0, 64 * 1024,  16, SPI_NOR_QUAD_READ) },
+	{ INFO("is25lp016", 0x9d6015, 0, 64 * 1024,  32, SPI_NOR_QUAD_READ) },
 	{ INFO("is25lp032",	0x9d6016, 0, 64 * 1024,  64, 0) },
 	{ INFO("is25lp064",	0x9d6017, 0, 64 * 1024, 128, 0) },
 	{ INFO("is25lp128",  0x9d6018, 0, 64 * 1024, 256,
@@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = {
 			SECT_4K | SPI_NOR_DUAL_READ) },
 	{ INFO("is25lp512",  0x9d601a, 0, 64 * 1024, 1024,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25lp01g",  0x9d601b, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25wp008", 0x9d7014, 0, 64 * 1024,  16, SPI_NOR_QUAD_READ) },
+	{ INFO("is25wp016", 0x9d7015, 0, 64 * 1024,  32, SPI_NOR_QUAD_READ) },
 	{ INFO("is25wp032",  0x9d7016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("is25wp064",  0x9d7017, 0, 64 * 1024, 128,
@@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = {
 			SPI_NOR_4B_OPCODES) },
 	{ INFO("is25wp512",  0x9d701a, 0, 64 * 1024, 1024,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25wp01g",  0x9d701b, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("is25wx256",  0x9d5b19, 0, 128 * 1024, 256,
+			SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
 	/* Macronix */
@@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
 	{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66u1g45g",  0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx66u2g45g",  0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("mx66l2g45g",  0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
 	{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
 	{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
@@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25ql02g",   0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
 #ifdef CONFIG_SPI_FLASH_MT35XU
+	{ INFO("mt35xl512aba", 0x2c5a1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
 	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
 #endif /* CONFIG_SPI_FLASH_MT35XU */
+	{ INFO6("mt35xu01g",  0x2c5b1b, 0x104100, 128 * 1024,  1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 #endif
 #ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
@@ -225,6 +245,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("s25fl512s_256k",  0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ INFO("s25fl512s_64k",  0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+	{ INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024,  64, 0) },
 	{ INFO("s25sl12801", 0x012018, 0x0301,  64 * 1024, 256, 0) },
 	{ INFO6("s25fl128s",  0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
@@ -275,12 +296,13 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("sst25wf040",  0xbf2504, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
 	{ INFO("sst25wf080",  0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
 	{ INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024,  32, SECT_4K) },
 	{ INFO("sst26wf016",  0xbf2651, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
 	{ INFO("sst26wf032",  0xbf2622, 0, 64 * 1024,  64, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
 	{ INFO("sst26wf064",  0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) },
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
-	/* ST Microelectronics -- newer production may have feature updates */
+	/* STMicroelectronics -- newer production may have feature updates */
 	{ INFO("m25p10",  0x202011,  0,  32 * 1024,   4, 0) },
 	{ INFO("m25p20",  0x202012,  0,  64 * 1024,   4, 0) },
 	{ INFO("m25p40",  0x202013,  0,  64 * 1024,   8, 0) },
@@ -312,11 +334,19 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("w25q20ew", 0xef6012, 0, 64 * 1024,  4, SECT_4K) },
 	{ INFO("w25q32", 0xef4016, 0, 64 * 1024,  64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{
+		INFO("w25q16dw", 0xef6015, 0, 64 * 1024,  32,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+	},
+	{
 		INFO("w25q32dw", 0xef6016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
+		INFO("w25q16jv", 0xef7015, 0, 64 * 1024,  32,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+	},
+	{
 		INFO("w25q32jv", 0xef7016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -363,6 +393,11 @@ const struct flash_info spi_nor_ids[] = {
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
+		INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
+	{
 		INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -370,6 +405,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("w25q80", 0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("w25q32bv", 0xef4016, 0, 64 * 1024,  64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("w25q64cv", 0xef4017, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("w25q128", 0xef4018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
@@ -378,6 +414,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 #endif
 #ifdef CONFIG_SPI_FLASH_XMC
 	/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 84d859c..b671e72 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -239,6 +239,10 @@ config E1000
 
 	  <http://support.intel.com/support/network/adapter/pro100/21397.htm>
 
+config E1000_NO_NVM
+	bool "Intel PRO/1000 has no NVMEM / EEPROM"
+	depends on E1000
+
 config E1000_SPI_GENERIC
 	bool "Allow access to the Intel 8257x SPI bus"
 	depends on E1000
@@ -308,6 +312,7 @@ config ETH_DESIGNWARE_MESON8B
 config ETH_DESIGNWARE_SOCFPGA
 	select REGMAP
 	select SYSCON
+	select DW_ALTDESCRIPTOR
 	bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC"
 	depends on DM_ETH && ETH_DESIGNWARE
 	help
@@ -322,6 +327,10 @@ config ETH_DESIGNWARE_S700
 	  This provides glue layer to use Synopsys Designware Ethernet MAC
 	  present on Actions S700 SoC.
 
+config DW_ALTDESCRIPTOR
+	bool "Designware Ethernet MAC uses alternate (enhanced) descriptors"
+	depends on ETH_DESIGNWARE
+
 config ETHOC
 	bool "OpenCores 10/100 Mbps Ethernet MAC"
 	help
@@ -391,19 +400,27 @@ config FTGMAC100
 	  offers high-priority transmit queue for QoS and CoS
 	  applications.
 
+config SYS_DISCOVER_PHY
+	bool
 
 config MCFFEC
 	bool "ColdFire Ethernet Support"
 	depends on DM_ETH
 	select PHYLIB
+	select SYS_DISCOVER_PHY
 	help
 	  This driver supports the network interface units in the
 	  ColdFire family.
 
+config SYS_UNIFY_CACHE
+	depends on MCFFEC
+	bool "Invalidate icache during ethernet operations"
+
 config FSLDMAFEC
         bool "ColdFire DMA Ethernet Support"
 	depends on DM_ETH
 	select PHYLIB
+	select SYS_DISCOVER_PHY
 	help
 	  This driver supports the network interface units in the
 	  ColdFire family.
@@ -719,6 +736,7 @@ config MPC8XX_FEC
 	bool "Fast Ethernet Controller on MPC8XX"
 	depends on MPC8xx
 	select MII
+	select SYS_DISCOVER_PHY
 	help
 	  This driver implements support for the Fast Ethernet Controller
 	  on MPC8XX
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 1584b9e..0e63f70 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2010
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  */
 
 /*
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index a82afb9..3793d55 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2010
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  */
 
 #ifndef _DW_ETH_H
@@ -85,10 +85,8 @@ struct eth_dma_regs {
 
 #define DW_DMA_BASE_OFFSET	(0x1000)
 
-/* Default DMA Burst length */
-#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
-#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
-#endif
+/* DMA Burst length */
+#define GMAC_DEFAULT_DMA_PBL	8
 
 /* Bus mode register definitions */
 #define FIXEDBURST		(1 << 16)
@@ -96,7 +94,7 @@ struct eth_dma_regs {
 #define PRIORXTX_31		(2 << 14)
 #define PRIORXTX_21		(1 << 14)
 #define PRIORXTX_11		(0 << 14)
-#define DMA_PBL			(CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
+#define DMA_PBL			(GMAC_DEFAULT_DMA_PBL << 8)
 #define RXHIGHPRIO		(1 << 1)
 #define DMAMAC_SRST		(1 << 0)
 
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index e103f79..6825f9e 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -243,16 +243,8 @@ static int fec_init(struct udevice *dev)
 	fecpin_setclear(info, 1);
 	fec_halt(dev);
 
-#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
-	defined (CONFIG_SYS_DISCOVER_PHY)
-
 	mii_init();
 	set_fec_duplex_speed(fecp, info->dup_spd);
-#else
-#ifndef CONFIG_SYS_DISCOVER_PHY
-	set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
-#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
-#endif				/* CONFIG_CMD_MII || CONFIG_MII */
 
 	/* We use strictly polling mode only */
 	fecp->eimr = 0;
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index cef9eec..4dd8489 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -278,17 +278,9 @@ int mcffec_init(struct udevice *dev)
 	fecpin_setclear(info, 1);
 	fec_reset(info);
 
-#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
-	defined (CONFIG_SYS_DISCOVER_PHY)
-
 	mii_init();
 
 	set_fec_duplex_speed(fecp, info->dup_spd);
-#else
-#ifndef CONFIG_SYS_DISCOVER_PHY
-	set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
-#endif	/* ifndef CONFIG_SYS_DISCOVER_PHY */
-#endif	/* CONFIG_CMD_MII || CONFIG_MII */
 
 	/* We use strictly polling mode only */
 	fecp->eimr = 0;
diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c
index 37459df..13022ad 100644
--- a/drivers/net/sandbox.c
+++ b/drivers/net/sandbox.c
@@ -395,9 +395,11 @@ static void sb_eth_stop(struct udevice *dev)
 static int sb_eth_write_hwaddr(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
+	struct eth_sandbox_priv *priv = dev_get_priv(dev);
 
 	debug("eth_sandbox %s: Write HW ADDR - %pM\n", dev->name,
 	      pdata->enetaddr);
+	memcpy(priv->fake_host_hwaddr, pdata->enetaddr, ARP_HLEN);
 	return 0;
 }
 
@@ -419,16 +421,8 @@ static int sb_eth_of_to_plat(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
 	struct eth_sandbox_priv *priv = dev_get_priv(dev);
-	const u8 *mac;
 
 	pdata->iobase = dev_read_addr(dev);
-
-	mac = dev_read_u8_array_ptr(dev, "fake-host-hwaddr", ARP_HLEN);
-	if (!mac) {
-		printf("'fake-host-hwaddr' is missing from the DT\n");
-		return -EINVAL;
-	}
-	memcpy(priv->fake_host_hwaddr, mac, ARP_HLEN);
 	priv->disabled = false;
 	priv->tx_handler = sb_default_handler;
 
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index db324c1..f2ba344 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -66,155 +66,7 @@ struct smc91111_priv{
 
 #define	SMC_IO_EXTENT	16
 
-#ifdef CONFIG_CPU_PXA25X
-
-#ifdef CONFIG_XSENGINE
-#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+((r)<<1))))
-#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+((r)<<1))))
-#define SMC_inb(a,p)  ({ \
-	unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
-	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
-	if (__p & 2) __v >>= 8; \
-	else __v &= 0xff; \
-	__v; })
-#else
-#define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+(r))))
-#define	SMC_inw(a,r)	(*((volatile word *)((a)->iobase+(r))))
-#define SMC_inb(a,p)	({ \
-	unsigned int __p = (unsigned int)((a)->iobase + (p)); \
-	unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
-	if (__p & 1) __v >>= 8; \
-	else __v &= 0xff; \
-	__v; })
-#endif
-
-#ifdef CONFIG_XSENGINE
-#define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r<<1))) = d)
-#define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r<<1))) = d)
-#else
-#define	SMC_outl(a,d,r)	(*((volatile dword *)((a)->iobase+(r))) = d)
-#define	SMC_outw(a,d,r)	(*((volatile word *)((a)->iobase+(r))) = d)
-#endif
-
-#define	SMC_outb(a,d,r)	({	word __d = (byte)(d);  \
-				word __w = SMC_inw((a),(r)&~1);  \
-				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
-				__w |= ((r)&1) ? __d<<8 : __d;  \
-				SMC_outw((a),__w,(r)&~1);  \
-			})
-
-#define SMC_outsl(a,r,b,l)	({	int __i; \
-					dword *__b2; \
-					__b2 = (dword *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outl((a), *(__b2 + __i), r); \
-					} \
-				})
-
-#define SMC_outsw(a,r,b,l)	({	int __i; \
-					word *__b2; \
-					__b2 = (word *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outw((a), *(__b2 + __i), r); \
-					} \
-				})
-
-#define SMC_insl(a,r,b,l)	({	int __i ;  \
-					dword *__b2;  \
-					__b2 = (dword *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inl((a),(r));  \
-					  SMC_inl((a),0);  \
-					};  \
-				})
-
-#define SMC_insw(a,r,b,l)		({	int __i ;  \
-					word *__b2;  \
-					__b2 = (word *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inw((a),(r));  \
-					  SMC_inw((a),0);  \
-					};  \
-				})
-
-#define SMC_insb(a,r,b,l)	({	int __i ;  \
-					byte *__b2;  \
-					__b2 = (byte *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inb((a),(r));  \
-					  SMC_inb((a),0);  \
-					};  \
-				})
-
-#elif defined(CONFIG_LEON)	/* if not CONFIG_CPU_PXA25X */
-
-#define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
-
-#define SMC_LEON_SWAP32(_x_)			\
-    ({ dword _x = (_x_);			\
-       ((_x << 24) |				\
-       ((0x0000FF00UL & _x) <<  8) |		\
-       ((0x00FF0000UL & _x) >>  8) |		\
-       (_x  >> 24)); })
-
-#define	SMC_inl(a,r)	(SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
-#define	SMC_inl_nosw(a,r)	((*(volatile dword *)((a)->iobase+((r)<<0))))
-#define	SMC_inw(a,r)	(SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
-#define	SMC_inw_nosw(a,r)	((*(volatile word *)((a)->iobase+((r)<<0))))
-#define SMC_inb(a,p)	({ \
-	word ___v = SMC_inw((a),(p) & ~1); \
-	if ((p) & 1) ___v >>= 8; \
-	else ___v &= 0xff; \
-	___v; })
-
-#define	SMC_outl(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
-#define	SMC_outl_nosw(a,d,r)	(*(volatile dword *)((a)->iobase+((r)<<0))=(d))
-#define	SMC_outw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
-#define	SMC_outw_nosw(a,d,r)	(*(volatile word *)((a)->iobase+((r)<<0))=(d))
-#define	SMC_outb(a,d,r)	do{	word __d = (byte)(d);  \
-				word __w = SMC_inw((a),(r)&~1);  \
-				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
-				__w |= ((r)&1) ? __d<<8 : __d;  \
-				SMC_outw((a),__w,(r)&~1);  \
-			}while(0)
-#define SMC_outsl(a,r,b,l)	do{	int __i; \
-					dword *__b2; \
-					__b2 = (dword *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outl_nosw((a), *(__b2 + __i), r); \
-					} \
-				}while(0)
-#define SMC_outsw(a,r,b,l)	do{	int __i; \
-					word *__b2; \
-					__b2 = (word *) b; \
-					for (__i = 0; __i < l; __i++) { \
-					    SMC_outw_nosw((a), *(__b2 + __i), r); \
-					} \
-				}while(0)
-#define SMC_insl(a,r,b,l)	do{	int __i ;  \
-					dword *__b2;  \
-					__b2 = (dword *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inl_nosw((a),(r));  \
-					};  \
-				}while(0)
-
-#define SMC_insw(a,r,b,l)		do{	int __i ;  \
-					word *__b2;  \
-					__b2 = (word *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inw_nosw((a),(r));  \
-					};  \
-				}while(0)
-
-#define SMC_insb(a,r,b,l)		do{	int __i ;  \
-					byte *__b2;  \
-					__b2 = (byte *) b;  \
-					for (__i = 0; __i < l; __i++) {  \
-					  *(__b2 + __i) = SMC_inb((a),(r));  \
-					};  \
-				}while(0)
-#elif defined(CONFIG_MS7206SE)
+#if defined(CONFIG_MS7206SE)
 #define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); })
 #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r)))
 #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01))))
@@ -244,7 +96,7 @@ struct smc91111_priv{
 			__b2++; \
 		} \
 	} while (0)
-#else			/* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */
+#else
 
 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
 /*
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index a471573..04277b1 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -19,6 +19,7 @@
 #include <miiphy.h>
 #include <wait_bit.h>
 #include <linux/delay.h>
+#include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -295,6 +296,9 @@ static int axiemac_phy_init(struct udevice *dev)
 	/* Set default MDIO divisor */
 	writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		priv->phyaddr = eth_phy_get_addr(dev);
+
 	if (priv->phyaddr == -1) {
 		/* Detect the PHY address */
 		for (i = 31; i >= 0; i--) {
@@ -778,18 +782,29 @@ static int axi_emac_probe(struct udevice *dev)
 		priv->phy_of_handle = plat->phy_of_handle;
 		priv->interface = pdata->phy_interface;
 
-		priv->bus = mdio_alloc();
-		priv->bus->read = axiemac_miiphy_read;
-		priv->bus->write = axiemac_miiphy_write;
-		priv->bus->priv = priv;
+		if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+			priv->bus = eth_phy_get_mdio_bus(dev);
 
-		ret = mdio_register_seq(priv->bus, dev_seq(dev));
-		if (ret)
-			return ret;
+		if (!priv->bus) {
+			priv->bus = mdio_alloc();
+			priv->bus->read = axiemac_miiphy_read;
+			priv->bus->write = axiemac_miiphy_write;
+			priv->bus->priv = priv;
+
+			ret = mdio_register_seq(priv->bus, dev_seq(dev));
+			if (ret)
+				return ret;
+		}
+
+		if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+			eth_phy_set_mdio_bus(dev, priv->bus);
 
 		axiemac_phy_init(dev);
 	}
 
+	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
+	       priv->phyaddr, phy_string_for_interface(pdata->phy_interface));
+
 	return 0;
 }
 
@@ -844,8 +859,10 @@ static int axi_emac_of_to_plat(struct udevice *dev)
 		offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 					       "phy-handle");
 		if (offset > 0) {
-			plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
-						       "reg", -1);
+			if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
+				plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
+							       offset,
+							       "reg", -1);
 			plat->phy_of_handle = offset;
 		}
 
@@ -857,9 +874,6 @@ static int axi_emac_of_to_plat(struct udevice *dev)
 						     "xlnx,eth-hasnobuf");
 	}
 
-	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
-	       plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
-
 	return 0;
 }
 
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 43fc36d..6c9f1f7 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <asm/io.h>
+#include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -564,14 +565,27 @@ static int emaclite_probe(struct udevice *dev)
 	struct xemaclite *emaclite = dev_get_priv(dev);
 	int ret;
 
-	emaclite->bus = mdio_alloc();
-	emaclite->bus->read = emaclite_miiphy_read;
-	emaclite->bus->write = emaclite_miiphy_write;
-	emaclite->bus->priv = emaclite;
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		emaclite->bus = eth_phy_get_mdio_bus(dev);
 
-	ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
-	if (ret)
-		return ret;
+	if (!emaclite->bus) {
+		emaclite->bus = mdio_alloc();
+		emaclite->bus->read = emaclite_miiphy_read;
+		emaclite->bus->write = emaclite_miiphy_write;
+		emaclite->bus->priv = emaclite;
+
+		ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
+		if (ret)
+			return ret;
+	}
+
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
+		eth_phy_set_mdio_bus(dev, emaclite->bus);
+		emaclite->phyaddr = eth_phy_get_addr(dev);
+	}
+
+	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
+	       emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
 
 	return 0;
 }
@@ -606,20 +620,19 @@ static int emaclite_of_to_plat(struct udevice *dev)
 
 	emaclite->phyaddr = -1;
 
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
-				      "phy-handle");
-	if (offset > 0)
-		emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
-						   "reg", -1);
+	if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) {
+		offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
+					       "phy-handle");
+		if (offset > 0)
+			emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob,
+							   offset, "reg", -1);
+	}
 
 	emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					"xlnx,tx-ping-pong", 0);
 	emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 					"xlnx,rx-ping-pong", 0);
 
-	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
-	       emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
-
 	return 0;
 }
 
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index fd22034..436acca 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -48,6 +48,10 @@ config PCI_REGION_MULTI_ENTRY
 	  region type. This helps to add support for SoC's like OcteonTX/TX2
 	  where every peripheral is on the PCI bus.
 
+config PCI_CONFIG_HOST_BRIDGE
+	bool "Configure PCI host bridges"
+	default y if X86
+
 config PCI_MAP_SYSTEM_MEMORY
 	bool "Map local system memory from a virtual base address"
 	depends on MIPS
@@ -81,6 +85,10 @@ config PCI_ARID
           support on PCI devices. This helps to skip some devices in BDF
           scan that are not present.
 
+config PCI_SCAN_SHOW
+	bool "Show PCI devices during startup"
+	depends on PCIE_IMX
+
 config PCIE_ECAM_GENERIC
 	bool "Generic ECAM-based PCI host controller support"
 	help
@@ -97,6 +105,10 @@ config PCIE_ECAM_SYNQUACER
 	  Note that this must be configured when boot because Linux driver
 	  expects the PCIe RC has been configured in the bootloader.
 
+config PCI_GT64120
+	bool "GT64120 PCI support"
+	depends on MIPS
+
 config PCI_PHYTIUM
 	bool "Phytium PCIe support"
 	help
@@ -121,8 +133,12 @@ config PCIE_DW_SIFIVE
 	  Say Y here if you want to enable PCIe controller support on
 	  FU740.
 
+config SYS_FSL_PCI_VER_3_X
+	bool
+
 config PCIE_FSL
 	bool "FSL PowerPC PCIe support"
+	select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240
 	help
 	  Say Y here if you want to enable PCIe controller support on FSL
 	  PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs.
@@ -134,6 +150,10 @@ config PCI_MPC85XX
 	  Say Y here if you want to enable PCI controller support on FSL
 	  PowerPC MPC85xx SoC.
 
+config PCI_MSC01
+	bool "MSC01 PCI support"
+	depends on TARGET_MALTA
+
 config PCI_RCAR_GEN2
 	bool "Renesas RCar Gen2 PCIe driver"
 	depends on RCAR_32
@@ -159,6 +179,12 @@ config PCI_SANDBOX
 	  the device tree but the normal PCI scan technique is used to find
 	  then.
 
+config SH7751_PCI
+	bool "SH7751 PCI controller support"
+	depends on SH
+	help
+	  SuperH PCI Bridge Configuration
+
 config PCI_TEGRA
 	bool "Tegra PCI support"
 	depends on ARCH_TEGRA
@@ -254,6 +280,10 @@ config FSL_PCIE_EP_COMPAT
 	  This compatible is used to find pci controller ep node in Kernel DT
 	  to complete fixup.
 
+config PCIE_IMX
+	bool "i.MX PCIe support"
+	depends on ARCH_MX6
+
 config PCIE_INTEL_FPGA
 	bool "Intel FPGA PCIe support"
 	help
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 04f6236..cfcd6fd 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
 obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o
-obj-$(CONFIG_SH4_PCI) += pci_sh4.o
 obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
 obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 970ee1a..2c85e78 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -954,7 +954,7 @@ int pci_bind_bus_devices(struct udevice *bus)
 	return 0;
 }
 
-static void decode_regions(struct pci_controller *hose, ofnode parent_node,
+static int decode_regions(struct pci_controller *hose, ofnode parent_node,
 			   ofnode node)
 {
 	int pci_addr_cells, addr_cells, size_cells;
@@ -968,7 +968,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
 	prop = ofnode_get_property(node, "ranges", &len);
 	if (!prop) {
 		debug("%s: Cannot decode regions\n", __func__);
-		return;
+		return -EINVAL;
 	}
 
 	pci_addr_cells = ofnode_read_simple_addr_cells(node);
@@ -986,6 +986,8 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
 	max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
 	hose->regions = (struct pci_region *)
 		calloc(1, max_regions * sizeof(struct pci_region));
+	if (!hose->regions)
+		return -ENOMEM;
 
 	for (i = 0; i < max_regions; i++, len -= cells_per_record) {
 		u64 pci_addr, addr, size;
@@ -1053,7 +1055,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
 	/* Add a region for our local memory */
 	bd = gd->bd;
 	if (!bd)
-		return;
+		return 0;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
 		if (bd->bi_dram[i].size) {
@@ -1068,7 +1070,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
 		}
 	}
 
-	return;
+	return 0;
 }
 
 static int pci_uclass_pre_probe(struct udevice *bus)
@@ -1097,7 +1099,10 @@ static int pci_uclass_pre_probe(struct udevice *bus)
 	/* For bridges, use the top-level PCI controller */
 	if (!device_is_on_pci_bus(bus)) {
 		hose->ctlr = bus;
-		decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
+		ret = decode_regions(hose, dev_ofnode(bus->parent),
+				     dev_ofnode(bus));
+		if (ret)
+			return ret;
 	} else {
 		struct pci_controller *parent_hose;
 
diff --git a/drivers/pci/pci_sh4.c b/drivers/pci/pci_sh4.c
deleted file mode 100644
index aac9be0..0000000
--- a/drivers/pci/pci_sh4.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SH4 PCI Controller (PCIC) for U-Boot.
- * (C) Dustin McIntire (dustin@sensoria.com)
- * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
- *
- * u-boot/arch/sh/cpu/sh4/pci-sh4.c
- */
-
-#include <common.h>
-#include <linux/delay.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <pci.h>
-
-int pci_sh4_init(struct pci_controller *hose)
-{
-	hose->first_busno = 0;
-	hose->region_count = 0;
-	hose->last_busno = 0xff;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		CONFIG_PCI_MEM_BUS,
-		CONFIG_PCI_MEM_PHYS,
-		CONFIG_PCI_MEM_SIZE,
-		PCI_REGION_MEM);
-	hose->region_count++;
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		CONFIG_PCI_IO_BUS,
-		CONFIG_PCI_IO_PHYS,
-		CONFIG_PCI_IO_SIZE,
-		PCI_REGION_IO);
-	hose->region_count++;
-
-#if defined(CONFIG_PCI_SYS_BUS)
-	/* PCI System Memory space */
-	pci_set_region(hose->regions + 2,
-		CONFIG_PCI_SYS_BUS,
-		CONFIG_PCI_SYS_PHYS,
-		CONFIG_PCI_SYS_SIZE,
-		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-	hose->region_count++;
-#endif
-
-	udelay(1000);
-
-	pci_set_ops(hose,
-		    pci_hose_read_config_byte_via_dword,
-		    pci_hose_read_config_word_via_dword,
-		    pci_sh4_read_config_dword,
-		    pci_hose_write_config_byte_via_dword,
-		    pci_hose_write_config_word_via_dword,
-		    pci_sh4_write_config_dword);
-
-	pci_register_hose(hose);
-
-	udelay(1000);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-	hose->last_busno = pci_hose_scan(hose);
-	return 0;
-}
-
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
-{
-	return 0;
-}
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
-{
-	return 1;
-}
-#endif /* CONFIG_PCI_SCAN_SHOW */
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c01d9e0..4a3856d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -274,6 +274,13 @@ config PHY_MTK_TPHY
 	  multi-ports is first version, otherwise is second veriosn,
 	  so you can easily distinguish them by banks layout.
 
+config PHY_NPCM_USB
+	bool "Nuvoton NPCM USB PHY support"
+	depends on PHY
+	depends on ARCH_NPCM
+	help
+	  Support the USB PHY in NPCM SoCs
+
 config PHY_IMX8MQ_USB
 	bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver"
 	depends on PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bf9b409..d95439c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
 obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
 obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
+obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
 obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
 obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
 obj-y += cadence/
diff --git a/drivers/phy/phy-npcm-usb.c b/drivers/phy/phy-npcm-usb.c
new file mode 100644
index 0000000..24eba66
--- /dev/null
+++ b/drivers/phy/phy-npcm-usb.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2021 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+
+/* GCR Register Offsets */
+#define GCR_INTCR3	0x9C
+#define GCR_USB1PHYCTL	0x140
+#define GCR_USB2PHYCTL	0x144
+#define GCR_USB3PHYCTL	0x148
+
+/* USBnPHYCTL bit fields */
+#define PHYCTL_RS	BIT(28)
+
+#define USBPHY2SW	GENMASK(13, 12)
+#define USBPHY3SW	GENMASK(15, 14)
+
+#define USBPHY2SW_DEV9_PHY1	FIELD_PREP(USBPHY2SW, 0)
+#define USBPHY2SW_HOST1		FIELD_PREP(USBPHY2SW, 1)
+#define USBPHY2SW_DEV9_PHY2	FIELD_PREP(USBPHY2SW, 3)
+#define USBPHY3SW_DEV8_PHY1	FIELD_PREP(USBPHY3SW, 0)
+#define USBPHY3SW_HOST2		FIELD_PREP(USBPHY3SW, 1)
+#define USBPHY3SW_DEV8_PHY3	FIELD_PREP(USBPHY3SW, 3)
+
+enum controller_id {
+	UDC0_7,
+	UDC8,
+	UDC9,
+	USBH1,
+	USBH2,
+};
+
+enum phy_id {
+	PHY1 = 1,
+	PHY2,
+	PHY3,
+};
+
+/* Phy Switch Settings */
+#define USBDPHY1	((PHY1 << 8) | UDC0_7)	/* Connect UDC0~7 to PHY1 */
+#define USBD8PHY1	((PHY1 << 8) | UDC8)	/* Connect UDC8 to PHY1 */
+#define USBD9PHY1	((PHY1 << 8) | UDC9)	/* Connect UDC9 to PHY1 */
+#define USBD9PHY2	((PHY2 << 8) | UDC9)	/* Connect UDC9 to PHY2 */
+#define USBH1PHY2	((PHY2 << 8) | USBH1)	/* Connect USBH1 to PHY2 */
+#define USBD8PHY3	((PHY3 << 8) | UDC8)	/* Connect UDC8 to PHY3 */
+#define USBH2PHY3	((PHY3 << 8) | USBH2)	/* Connect USBH2 to PHY3 */
+
+struct npcm_usbphy {
+	struct regmap *syscon;
+	u8 id;
+	u16 phy_switch;	/* (phy_id << 8) | controller_id */
+};
+
+static int npcm_usb_phy_init(struct phy *phy)
+{
+	struct npcm_usbphy *priv = dev_get_priv(phy->dev);
+	struct reset_ctl reset;
+	int ret;
+
+	ret = reset_get_by_index(phy->dev, 0, &reset);
+	if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
+		dev_err(phy->dev, "can't get phy reset ctrl (err %d)", ret);
+		return ret;
+	}
+
+	/* setup PHY switch */
+	switch (priv->phy_switch) {
+	case USBD8PHY1:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_DEV8_PHY1);
+		break;
+	case USBD8PHY3:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_DEV8_PHY3);
+		break;
+	case USBD9PHY1:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_DEV9_PHY1);
+		break;
+	case USBD9PHY2:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_DEV9_PHY2);
+		break;
+	case USBH1PHY2:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_HOST1);
+		break;
+	case USBH2PHY3:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_HOST2);
+		break;
+	default:
+		break;
+	}
+	/* reset phy */
+	if (reset_valid(&reset))
+		reset_assert(&reset);
+
+	/* Wait for PHY clocks to stablize for 50us or more */
+	udelay(100);
+
+	/* release phy from reset */
+	if (reset_valid(&reset))
+		reset_deassert(&reset);
+
+	/* PHY RS bit should be set after reset */
+	switch (priv->id) {
+	case PHY1:
+		regmap_update_bits(priv->syscon, GCR_USB1PHYCTL, PHYCTL_RS, PHYCTL_RS);
+		break;
+	case PHY2:
+		regmap_update_bits(priv->syscon, GCR_USB2PHYCTL, PHYCTL_RS, PHYCTL_RS);
+		break;
+	case PHY3:
+		regmap_update_bits(priv->syscon, GCR_USB3PHYCTL, PHYCTL_RS, PHYCTL_RS);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int npcm_usb_phy_exit(struct phy *phy)
+{
+	struct npcm_usbphy *priv = dev_get_priv(phy->dev);
+
+	/* set PHY switch to default state */
+	switch (priv->phy_switch) {
+	case USBD8PHY1:
+	case USBD8PHY3:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY3SW,
+				   USBPHY3SW_HOST2);
+		break;
+	case USBD9PHY1:
+	case USBD9PHY2:
+		regmap_update_bits(priv->syscon, GCR_INTCR3, USBPHY2SW,
+				   USBPHY2SW_HOST1);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static int  npcm_usb_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
+{
+	struct npcm_usbphy *priv = dev_get_priv(phy->dev);
+	u16 phy_switch;
+
+	if (args->args_count < 1 || args->args[0] > USBH2)
+		return -EINVAL;
+
+	phy_switch = (priv->id << 8) | args->args[0];
+	switch (phy_switch) {
+	case USBD9PHY1:
+	case USBH2PHY3:
+	case USBD8PHY3:
+		if (!IS_ENABLED(CONFIG_ARCH_NPCM8XX))
+			return -EINVAL;
+	case USBDPHY1:
+	case USBD8PHY1:
+	case USBD9PHY2:
+	case USBH1PHY2:
+		priv->phy_switch = phy_switch;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int npcm_usb_phy_probe(struct udevice *dev)
+{
+	struct npcm_usbphy *priv = dev_get_priv(dev);
+
+	priv->syscon = syscon_regmap_lookup_by_phandle(dev->parent, "syscon");
+	if (IS_ERR(priv->syscon)) {
+		dev_err(dev, "%s: unable to get syscon\n", __func__);
+		return PTR_ERR(priv->syscon);
+	}
+	priv->id = dev_read_u32_default(dev, "reg", -1);
+
+	return 0;
+}
+
+static const struct udevice_id npcm_phy_ids[] = {
+	{ .compatible = "nuvoton,npcm845-usb-phy",},
+	{ .compatible = "nuvoton,npcm750-usb-phy",},
+	{ }
+};
+
+static struct phy_ops npcm_phy_ops = {
+	.init = npcm_usb_phy_init,
+	.exit = npcm_usb_phy_exit,
+	.of_xlate = npcm_usb_phy_xlate,
+};
+
+U_BOOT_DRIVER(npcm_phy) = {
+	.name	= "npcm-usb-phy",
+	.id	= UCLASS_PHY,
+	.of_match = npcm_phy_ids,
+	.ops = &npcm_phy_ops,
+	.probe		= npcm_usb_phy_probe,
+	.priv_auto	= sizeof(struct npcm_usbphy),
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 563d96d..b6ef2ac 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -272,7 +272,7 @@ config PINCTRL_STI
 	depends on DM && ARCH_STI
 	default y
 	help
-	  Support pin multiplexing control on STMicrolectronics STi SoCs.
+	  Support pin multiplexing control on STMicroelectronics STi SoCs.
 
 	  The driver is controlled by a device tree node which contains both
 	  the GPIO definitions and pin control functions for each available
@@ -353,6 +353,7 @@ source "drivers/pinctrl/mscc/Kconfig"
 source "drivers/pinctrl/mtmips/Kconfig"
 source "drivers/pinctrl/mvebu/Kconfig"
 source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
 source "drivers/pinctrl/nxp/Kconfig"
 source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 9b49782..3b167d0 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
 obj-$(CONFIG_ARCH_ATH79) += ath79/
 obj-$(CONFIG_PINCTRL_INTEL) += intel/
 obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM)         += nuvoton/
 obj-$(CONFIG_ARCH_RMOBILE) += renesas/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 obj-$(CONFIG_PINCTRL_SUNXI)	+= sunxi/
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 0000000..07f65f7
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config PINCTRL_NPCM7XX
+	bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX"
+	depends on DM && PINCTRL_GENERIC && ARCH_NPCM7xx
+	help
+	  Say Y here to enable pin controller and GPIO support
+	  for Nuvoton NPCM750/730/715/705 SoCs.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 0000000..886d007
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+# Nuvoton pinctrl support
+
+obj-$(CONFIG_PINCTRL_NPCM7XX)	+= pinctrl-npcm7xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
new file mode 100644
index 0000000..f6e2041
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -0,0 +1,1607 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Nuvoton Technology Corp.
+ * Author: Joseph Liu <kwliu@nuvoton.com>
+ * Author: Tomer Maimon <tomer.maimon@nuvoton.com>
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+
+/* GCR registers */
+#define NPCM7XX_GCR_PDID		0x00
+#define NPCM7XX_GCR_MFSEL1		0x0C
+#define NPCM7XX_GCR_MFSEL2		0x10
+#define NPCM7XX_GCR_MFSEL3		0x64
+#define NPCM7XX_GCR_MFSEL4		0xb0
+#define NPCM7XX_GCR_CPCTL		0xD0
+#define NPCM7XX_GCR_CP2BST		0xD4
+#define NPCM7XX_GCR_B2CPNT		0xD8
+#define NPCM7XX_GCR_I2CSEGSEL		0xE0
+#define NPCM7XX_GCR_I2CSEGCTL		0xE4
+#define NPCM7XX_GCR_INTCR2		0x60
+#define NPCM7XX_GCR_SRCNT		0x68
+#define NPCM7XX_GCR_RESSR		0x6C
+#define NPCM7XX_GCR_FLOCKR1		0x74
+#define NPCM7XX_GCR_DSCNT		0x78
+
+#define SRCNT_ESPI			BIT(3)
+
+/* reset registers */
+#define NPCM7XX_RST_WD0RCR		0x38
+#define NPCM7XX_RST_WD1RCR		0x3C
+#define NPCM7XX_RST_WD2RCR		0x40
+#define NPCM7XX_RST_SWRSTC1		0x44
+#define NPCM7XX_RST_SWRSTC2		0x48
+#define NPCM7XX_RST_SWRSTC3		0x4C
+#define NPCM7XX_RST_SWRSTC4		0x50
+#define NPCM7XX_RST_CORSTC		0x5C
+
+#define PORST				BIT(31)
+#define CORST				BIT(30)
+#define WD0RST				BIT(29)
+#define WD1RST				BIT(24)
+#define WD2RST				BIT(23)
+
+#define GPIOX_MODULE_RESET		16
+#define CA9C_RESET			BIT(0)
+
+/* GPIO registers */
+#define NPCM7XX_GP_N_TLOCK1	0x00
+#define NPCM7XX_GP_N_DIN	0x04 /* Data IN */
+#define NPCM7XX_GP_N_POL	0x08 /* Polarity */
+#define NPCM7XX_GP_N_DOUT	0x0c /* Data OUT */
+#define NPCM7XX_GP_N_OE		0x10 /* Output Enable */
+#define NPCM7XX_GP_N_OTYP	0x14
+#define NPCM7XX_GP_N_MP		0x18
+#define NPCM7XX_GP_N_PU		0x1c /* Pull-up */
+#define NPCM7XX_GP_N_PD		0x20 /* Pull-down */
+#define NPCM7XX_GP_N_DBNC	0x24 /* Debounce */
+#define NPCM7XX_GP_N_EVTYP	0x28 /* Event Type */
+#define NPCM7XX_GP_N_EVBE	0x2c /* Event Both Edge */
+#define NPCM7XX_GP_N_OBL0	0x30
+#define NPCM7XX_GP_N_OBL1	0x34
+#define NPCM7XX_GP_N_OBL2	0x38
+#define NPCM7XX_GP_N_OBL3	0x3c
+#define NPCM7XX_GP_N_EVEN	0x40 /* Event Enable */
+#define NPCM7XX_GP_N_EVENS	0x44 /* Event Set (enable) */
+#define NPCM7XX_GP_N_EVENC	0x48 /* Event Clear (disable) */
+#define NPCM7XX_GP_N_EVST	0x4c /* Event Status */
+#define NPCM7XX_GP_N_SPLCK	0x50
+#define NPCM7XX_GP_N_MPLCK	0x54
+#define NPCM7XX_GP_N_IEM	0x58 /* Input Enable */
+#define NPCM7XX_GP_N_OSRC	0x5c
+#define NPCM7XX_GP_N_ODSC	0x60
+#define NPCM7XX_GP_N_DOS	0x68 /* Data OUT Set */
+#define NPCM7XX_GP_N_DOC	0x6c /* Data OUT Clear */
+#define NPCM7XX_GP_N_OES	0x70 /* Output Enable Set */
+#define NPCM7XX_GP_N_OEC	0x74 /* Output Enable Clear */
+#define NPCM7XX_GP_N_TLOCK2	0x7c
+
+#define NPCM7XX_GPIO_BANK_OFFSET 0x1000
+#define NPCM7XX_GPIO_PER_BITS	32
+#define NPCM7XX_GPIO_PER_BANK	32
+#define NPCM7XX_GPIO_BANK_NUM	8
+#define NPCM7XX_GCR_NONE	0
+
+/* pinmux handing in the pinctrl driver*/
+static const int smb0_pins[]  = { 115, 114 };
+static const int smb0b_pins[] = { 195, 194 };
+static const int smb0c_pins[] = { 202, 196 };
+static const int smb0d_pins[] = { 198, 199 };
+static const int smb0den_pins[] = { 197 };
+
+static const int smb1_pins[]  = { 117, 116 };
+static const int smb1b_pins[] = { 126, 127 };
+static const int smb1c_pins[] = { 124, 125 };
+static const int smb1d_pins[] = { 4, 5 };
+
+static const int smb2_pins[]  = { 119, 118 };
+static const int smb2b_pins[] = { 122, 123 };
+static const int smb2c_pins[] = { 120, 121 };
+static const int smb2d_pins[] = { 6, 7 };
+
+static const int smb3_pins[]  = { 30, 31 };
+static const int smb3b_pins[] = { 39, 40 };
+static const int smb3c_pins[] = { 37, 38 };
+static const int smb3d_pins[] = { 59, 60 };
+
+static const int smb4_pins[]  = { 28, 29 };
+static const int smb4b_pins[] = { 18, 19 };
+static const int smb4c_pins[] = { 20, 21 };
+static const int smb4d_pins[] = { 22, 23 };
+static const int smb4den_pins[] = { 17 };
+
+static const int smb5_pins[]  = { 26, 27 };
+static const int smb5b_pins[] = { 13, 12 };
+static const int smb5c_pins[] = { 15, 14 };
+static const int smb5d_pins[] = { 94, 93 };
+static const int ga20kbc_pins[] = { 94, 93 };
+
+static const int smb6_pins[]  = { 172, 171 };
+static const int smb7_pins[]  = { 174, 173 };
+static const int smb8_pins[]  = { 129, 128 };
+static const int smb9_pins[]  = { 131, 130 };
+static const int smb10_pins[] = { 133, 132 };
+static const int smb11_pins[] = { 135, 134 };
+static const int smb12_pins[] = { 221, 220 };
+static const int smb13_pins[] = { 223, 222 };
+static const int smb14_pins[] = { 22, 23 };
+static const int smb15_pins[] = { 20, 21 };
+
+static const int fanin0_pins[] = { 64 };
+static const int fanin1_pins[] = { 65 };
+static const int fanin2_pins[] = { 66 };
+static const int fanin3_pins[] = { 67 };
+static const int fanin4_pins[] = { 68 };
+static const int fanin5_pins[] = { 69 };
+static const int fanin6_pins[] = { 70 };
+static const int fanin7_pins[] = { 71 };
+static const int fanin8_pins[] = { 72 };
+static const int fanin9_pins[] = { 73 };
+static const int fanin10_pins[] = { 74 };
+static const int fanin11_pins[] = { 75 };
+static const int fanin12_pins[] = { 76 };
+static const int fanin13_pins[] = { 77 };
+static const int fanin14_pins[] = { 78 };
+static const int fanin15_pins[] = { 79 };
+static const int faninx_pins[] = { 175, 176, 177, 203 };
+
+static const int pwm0_pins[] = { 80 };
+static const int pwm1_pins[] = { 81 };
+static const int pwm2_pins[] = { 82 };
+static const int pwm3_pins[] = { 83 };
+static const int pwm4_pins[] = { 144 };
+static const int pwm5_pins[] = { 145 };
+static const int pwm6_pins[] = { 146 };
+static const int pwm7_pins[] = { 147 };
+
+static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
+static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
+
+/* RGMII 1 pin group */
+static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
+	106, 107 };
+/* RGMII 1 MD interface pin group */
+static const int rg1mdio_pins[] = { 108, 109 };
+
+/* RGMII 2 pin group */
+static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
+	213, 214, 215 };
+/* RGMII 2 MD interface pin group */
+static const int rg2mdio_pins[] = { 216, 217 };
+
+static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
+	213, 214, 215, 216, 217 };
+/* Serial I/O Expander 1 */
+static const int iox1_pins[] = { 0, 1, 2, 3 };
+/* Serial I/O Expander 2 */
+static const int iox2_pins[] = { 4, 5, 6, 7 };
+/* Host Serial I/O Expander 2 */
+static const int ioxh_pins[] = { 10, 11, 24, 25 };
+
+static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
+static const int mmcwp_pins[] = { 153 };
+static const int mmccd_pins[] = { 155 };
+static const int mmcrst_pins[] = { 155 };
+static const int mmc8_pins[] = { 148, 149, 150, 151 };
+
+/* RMII 1 pin groups */
+static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
+static const int r1err_pins[] = { 56 };
+static const int r1md_pins[] = { 57, 58 };
+
+/* RMII 2 pin groups */
+static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
+static const int r2err_pins[] = { 90 };
+static const int r2md_pins[] = { 91, 92 };
+
+static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
+static const int sd1pwr_pins[] = { 143 };
+
+static const int wdog1_pins[] = { 218 };
+static const int wdog2_pins[] = { 219 };
+
+/* BMC serial port 0 */
+static const int bmcuart0a_pins[] = { 41, 42 };
+static const int bmcuart0b_pins[] = { 48, 49 };
+
+static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
+
+/* System Control Interrupt and Power Management Event pin group */
+static const int scipme_pins[] = { 169 };
+/* System Management Interrupt pin group */
+static const int sci_pins[] = { 170 };
+/* Serial Interrupt Line pin group */
+static const int serirq_pins[] = { 162 };
+
+static const int clkout_pins[] = { 160 };
+static const int clkreq_pins[] = { 231 };
+
+static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
+/* Graphics SPI Clock pin group */
+static const int gspi_pins[] = { 12, 13, 14, 15 };
+
+static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
+static const int spixcs1_pins[] = { 228 };
+
+static const int pspi1_pins[] = { 175, 176, 177 };
+static const int pspi2_pins[] = { 17, 18, 19 };
+
+static const int spi0cs1_pins[] = { 32 };
+
+static const int spi3_pins[] = { 183, 184, 185, 186 };
+static const int spi3cs1_pins[] = { 187 };
+static const int spi3quad_pins[] = { 188, 189 };
+static const int spi3cs2_pins[] = { 188 };
+static const int spi3cs3_pins[] = { 189 };
+
+static const int ddc_pins[] = { 204, 205, 206, 207 };
+
+static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
+static const int lpcclk_pins[] = { 168 };
+static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
+
+static const int lkgpo0_pins[] = { 16 };
+static const int lkgpo1_pins[] = { 8 };
+static const int lkgpo2_pins[] = { 9 };
+
+static const int nprd_smi_pins[] = { 190 };
+
+static const int hgpio0_pins[] = { 20 };
+static const int hgpio1_pins[] = { 21 };
+static const int hgpio2_pins[] = { 22 };
+static const int hgpio3_pins[] = { 23 };
+static const int hgpio4_pins[] = { 24 };
+static const int hgpio5_pins[] = { 25 };
+static const int hgpio6_pins[] = { 59 };
+static const int hgpio7_pins[] = { 60 };
+
+/*
+ * pin:	     name, number
+ * group:    name, npins,   pins
+ * function: name, ngroups, groups
+ */
+struct npcm7xx_group {
+	const char *name;
+	const int *pins;
+	int npins;
+};
+
+#define NPCM7XX_GRPS \
+	NPCM7XX_GRP(smb0), \
+	NPCM7XX_GRP(smb0b), \
+	NPCM7XX_GRP(smb0c), \
+	NPCM7XX_GRP(smb0d), \
+	NPCM7XX_GRP(smb0den), \
+	NPCM7XX_GRP(smb1), \
+	NPCM7XX_GRP(smb1b), \
+	NPCM7XX_GRP(smb1c), \
+	NPCM7XX_GRP(smb1d), \
+	NPCM7XX_GRP(smb2), \
+	NPCM7XX_GRP(smb2b), \
+	NPCM7XX_GRP(smb2c), \
+	NPCM7XX_GRP(smb2d), \
+	NPCM7XX_GRP(smb3), \
+	NPCM7XX_GRP(smb3b), \
+	NPCM7XX_GRP(smb3c), \
+	NPCM7XX_GRP(smb3d), \
+	NPCM7XX_GRP(smb4), \
+	NPCM7XX_GRP(smb4b), \
+	NPCM7XX_GRP(smb4c), \
+	NPCM7XX_GRP(smb4d), \
+	NPCM7XX_GRP(smb4den), \
+	NPCM7XX_GRP(smb5), \
+	NPCM7XX_GRP(smb5b), \
+	NPCM7XX_GRP(smb5c), \
+	NPCM7XX_GRP(smb5d), \
+	NPCM7XX_GRP(ga20kbc), \
+	NPCM7XX_GRP(smb6), \
+	NPCM7XX_GRP(smb7), \
+	NPCM7XX_GRP(smb8), \
+	NPCM7XX_GRP(smb9), \
+	NPCM7XX_GRP(smb10), \
+	NPCM7XX_GRP(smb11), \
+	NPCM7XX_GRP(smb12), \
+	NPCM7XX_GRP(smb13), \
+	NPCM7XX_GRP(smb14), \
+	NPCM7XX_GRP(smb15), \
+	NPCM7XX_GRP(fanin0), \
+	NPCM7XX_GRP(fanin1), \
+	NPCM7XX_GRP(fanin2), \
+	NPCM7XX_GRP(fanin3), \
+	NPCM7XX_GRP(fanin4), \
+	NPCM7XX_GRP(fanin5), \
+	NPCM7XX_GRP(fanin6), \
+	NPCM7XX_GRP(fanin7), \
+	NPCM7XX_GRP(fanin8), \
+	NPCM7XX_GRP(fanin9), \
+	NPCM7XX_GRP(fanin10), \
+	NPCM7XX_GRP(fanin11), \
+	NPCM7XX_GRP(fanin12), \
+	NPCM7XX_GRP(fanin13), \
+	NPCM7XX_GRP(fanin14), \
+	NPCM7XX_GRP(fanin15), \
+	NPCM7XX_GRP(faninx), \
+	NPCM7XX_GRP(pwm0), \
+	NPCM7XX_GRP(pwm1), \
+	NPCM7XX_GRP(pwm2), \
+	NPCM7XX_GRP(pwm3), \
+	NPCM7XX_GRP(pwm4), \
+	NPCM7XX_GRP(pwm5), \
+	NPCM7XX_GRP(pwm6), \
+	NPCM7XX_GRP(pwm7), \
+	NPCM7XX_GRP(rg1), \
+	NPCM7XX_GRP(rg1mdio), \
+	NPCM7XX_GRP(rg2), \
+	NPCM7XX_GRP(rg2mdio), \
+	NPCM7XX_GRP(ddr), \
+	NPCM7XX_GRP(uart1), \
+	NPCM7XX_GRP(uart2), \
+	NPCM7XX_GRP(bmcuart0a), \
+	NPCM7XX_GRP(bmcuart0b), \
+	NPCM7XX_GRP(bmcuart1), \
+	NPCM7XX_GRP(iox1), \
+	NPCM7XX_GRP(iox2), \
+	NPCM7XX_GRP(ioxh), \
+	NPCM7XX_GRP(gspi), \
+	NPCM7XX_GRP(mmc), \
+	NPCM7XX_GRP(mmcwp), \
+	NPCM7XX_GRP(mmccd), \
+	NPCM7XX_GRP(mmcrst), \
+	NPCM7XX_GRP(mmc8), \
+	NPCM7XX_GRP(r1), \
+	NPCM7XX_GRP(r1err), \
+	NPCM7XX_GRP(r1md), \
+	NPCM7XX_GRP(r2), \
+	NPCM7XX_GRP(r2err), \
+	NPCM7XX_GRP(r2md), \
+	NPCM7XX_GRP(sd1), \
+	NPCM7XX_GRP(sd1pwr), \
+	NPCM7XX_GRP(wdog1), \
+	NPCM7XX_GRP(wdog2), \
+	NPCM7XX_GRP(scipme), \
+	NPCM7XX_GRP(sci), \
+	NPCM7XX_GRP(serirq), \
+	NPCM7XX_GRP(jtag2), \
+	NPCM7XX_GRP(spix), \
+	NPCM7XX_GRP(spixcs1), \
+	NPCM7XX_GRP(pspi1), \
+	NPCM7XX_GRP(pspi2), \
+	NPCM7XX_GRP(ddc), \
+	NPCM7XX_GRP(clkreq), \
+	NPCM7XX_GRP(clkout), \
+	NPCM7XX_GRP(spi3), \
+	NPCM7XX_GRP(spi3cs1), \
+	NPCM7XX_GRP(spi3quad), \
+	NPCM7XX_GRP(spi3cs2), \
+	NPCM7XX_GRP(spi3cs3), \
+	NPCM7XX_GRP(spi0cs1), \
+	NPCM7XX_GRP(lpc), \
+	NPCM7XX_GRP(lpcclk), \
+	NPCM7XX_GRP(espi), \
+	NPCM7XX_GRP(lkgpo0), \
+	NPCM7XX_GRP(lkgpo1), \
+	NPCM7XX_GRP(lkgpo2), \
+	NPCM7XX_GRP(nprd_smi), \
+	NPCM7XX_GRP(hgpio0), \
+	NPCM7XX_GRP(hgpio1), \
+	NPCM7XX_GRP(hgpio2), \
+	NPCM7XX_GRP(hgpio3), \
+	NPCM7XX_GRP(hgpio4), \
+	NPCM7XX_GRP(hgpio5), \
+	NPCM7XX_GRP(hgpio6), \
+	NPCM7XX_GRP(hgpio7), \
+	\
+
+enum {
+#define NPCM7XX_GRP(x) fn_ ## x
+	NPCM7XX_GRPS
+	/* add placeholder for none/gpio */
+	NPCM7XX_GRP(none),
+	NPCM7XX_GRP(gpio),
+#undef NPCM7XX_GRP
+};
+
+static struct npcm7xx_group npcm7xx_groups[] = {
+#define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
+			.npins = ARRAY_SIZE(x ## _pins) }
+	NPCM7XX_GRPS
+#undef NPCM7XX_GRP
+};
+
+#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
+#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
+#define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
+			.groups = nm ## _grp }
+struct npcm7xx_func {
+	const char *name;
+	const unsigned int ngroups;
+	const char *const *groups;
+};
+
+NPCM7XX_SFUNC(smb0);
+NPCM7XX_SFUNC(smb0b);
+NPCM7XX_SFUNC(smb0c);
+NPCM7XX_SFUNC(smb0d);
+NPCM7XX_SFUNC(smb0den);
+NPCM7XX_SFUNC(smb1);
+NPCM7XX_SFUNC(smb1b);
+NPCM7XX_SFUNC(smb1c);
+NPCM7XX_SFUNC(smb1d);
+NPCM7XX_SFUNC(smb2);
+NPCM7XX_SFUNC(smb2b);
+NPCM7XX_SFUNC(smb2c);
+NPCM7XX_SFUNC(smb2d);
+NPCM7XX_SFUNC(smb3);
+NPCM7XX_SFUNC(smb3b);
+NPCM7XX_SFUNC(smb3c);
+NPCM7XX_SFUNC(smb3d);
+NPCM7XX_SFUNC(smb4);
+NPCM7XX_SFUNC(smb4b);
+NPCM7XX_SFUNC(smb4c);
+NPCM7XX_SFUNC(smb4d);
+NPCM7XX_SFUNC(smb4den);
+NPCM7XX_SFUNC(smb5);
+NPCM7XX_SFUNC(smb5b);
+NPCM7XX_SFUNC(smb5c);
+NPCM7XX_SFUNC(smb5d);
+NPCM7XX_SFUNC(ga20kbc);
+NPCM7XX_SFUNC(smb6);
+NPCM7XX_SFUNC(smb7);
+NPCM7XX_SFUNC(smb8);
+NPCM7XX_SFUNC(smb9);
+NPCM7XX_SFUNC(smb10);
+NPCM7XX_SFUNC(smb11);
+NPCM7XX_SFUNC(smb12);
+NPCM7XX_SFUNC(smb13);
+NPCM7XX_SFUNC(smb14);
+NPCM7XX_SFUNC(smb15);
+NPCM7XX_SFUNC(fanin0);
+NPCM7XX_SFUNC(fanin1);
+NPCM7XX_SFUNC(fanin2);
+NPCM7XX_SFUNC(fanin3);
+NPCM7XX_SFUNC(fanin4);
+NPCM7XX_SFUNC(fanin5);
+NPCM7XX_SFUNC(fanin6);
+NPCM7XX_SFUNC(fanin7);
+NPCM7XX_SFUNC(fanin8);
+NPCM7XX_SFUNC(fanin9);
+NPCM7XX_SFUNC(fanin10);
+NPCM7XX_SFUNC(fanin11);
+NPCM7XX_SFUNC(fanin12);
+NPCM7XX_SFUNC(fanin13);
+NPCM7XX_SFUNC(fanin14);
+NPCM7XX_SFUNC(fanin15);
+NPCM7XX_SFUNC(faninx);
+NPCM7XX_SFUNC(pwm0);
+NPCM7XX_SFUNC(pwm1);
+NPCM7XX_SFUNC(pwm2);
+NPCM7XX_SFUNC(pwm3);
+NPCM7XX_SFUNC(pwm4);
+NPCM7XX_SFUNC(pwm5);
+NPCM7XX_SFUNC(pwm6);
+NPCM7XX_SFUNC(pwm7);
+NPCM7XX_SFUNC(rg1);
+NPCM7XX_SFUNC(rg1mdio);
+NPCM7XX_SFUNC(rg2);
+NPCM7XX_SFUNC(rg2mdio);
+NPCM7XX_SFUNC(ddr);
+NPCM7XX_SFUNC(uart1);
+NPCM7XX_SFUNC(uart2);
+NPCM7XX_SFUNC(bmcuart0a);
+NPCM7XX_SFUNC(bmcuart0b);
+NPCM7XX_SFUNC(bmcuart1);
+NPCM7XX_SFUNC(iox1);
+NPCM7XX_SFUNC(iox2);
+NPCM7XX_SFUNC(ioxh);
+NPCM7XX_SFUNC(gspi);
+NPCM7XX_SFUNC(mmc);
+NPCM7XX_SFUNC(mmcwp);
+NPCM7XX_SFUNC(mmccd);
+NPCM7XX_SFUNC(mmcrst);
+NPCM7XX_SFUNC(mmc8);
+NPCM7XX_SFUNC(r1);
+NPCM7XX_SFUNC(r1err);
+NPCM7XX_SFUNC(r1md);
+NPCM7XX_SFUNC(r2);
+NPCM7XX_SFUNC(r2err);
+NPCM7XX_SFUNC(r2md);
+NPCM7XX_SFUNC(sd1);
+NPCM7XX_SFUNC(sd1pwr);
+NPCM7XX_SFUNC(wdog1);
+NPCM7XX_SFUNC(wdog2);
+NPCM7XX_SFUNC(scipme);
+NPCM7XX_SFUNC(sci);
+NPCM7XX_SFUNC(serirq);
+NPCM7XX_SFUNC(jtag2);
+NPCM7XX_SFUNC(spix);
+NPCM7XX_SFUNC(spixcs1);
+NPCM7XX_SFUNC(pspi1);
+NPCM7XX_SFUNC(pspi2);
+NPCM7XX_SFUNC(ddc);
+NPCM7XX_SFUNC(clkreq);
+NPCM7XX_SFUNC(clkout);
+NPCM7XX_SFUNC(spi3);
+NPCM7XX_SFUNC(spi3cs1);
+NPCM7XX_SFUNC(spi3quad);
+NPCM7XX_SFUNC(spi3cs2);
+NPCM7XX_SFUNC(spi3cs3);
+NPCM7XX_SFUNC(spi0cs1);
+NPCM7XX_SFUNC(lpc);
+NPCM7XX_SFUNC(lpcclk);
+NPCM7XX_SFUNC(espi);
+NPCM7XX_SFUNC(lkgpo0);
+NPCM7XX_SFUNC(lkgpo1);
+NPCM7XX_SFUNC(lkgpo2);
+NPCM7XX_SFUNC(nprd_smi);
+NPCM7XX_SFUNC(hgpio0);
+NPCM7XX_SFUNC(hgpio1);
+NPCM7XX_SFUNC(hgpio2);
+NPCM7XX_SFUNC(hgpio3);
+NPCM7XX_SFUNC(hgpio4);
+NPCM7XX_SFUNC(hgpio5);
+NPCM7XX_SFUNC(hgpio6);
+NPCM7XX_SFUNC(hgpio7);
+
+/* Function names */
+static struct npcm7xx_func npcm7xx_funcs[] = {
+	NPCM7XX_MKFUNC(smb0),
+	NPCM7XX_MKFUNC(smb0b),
+	NPCM7XX_MKFUNC(smb0c),
+	NPCM7XX_MKFUNC(smb0d),
+	NPCM7XX_MKFUNC(smb0den),
+	NPCM7XX_MKFUNC(smb1),
+	NPCM7XX_MKFUNC(smb1b),
+	NPCM7XX_MKFUNC(smb1c),
+	NPCM7XX_MKFUNC(smb1d),
+	NPCM7XX_MKFUNC(smb2),
+	NPCM7XX_MKFUNC(smb2b),
+	NPCM7XX_MKFUNC(smb2c),
+	NPCM7XX_MKFUNC(smb2d),
+	NPCM7XX_MKFUNC(smb3),
+	NPCM7XX_MKFUNC(smb3b),
+	NPCM7XX_MKFUNC(smb3c),
+	NPCM7XX_MKFUNC(smb3d),
+	NPCM7XX_MKFUNC(smb4),
+	NPCM7XX_MKFUNC(smb4b),
+	NPCM7XX_MKFUNC(smb4c),
+	NPCM7XX_MKFUNC(smb4d),
+	NPCM7XX_MKFUNC(smb4den),
+	NPCM7XX_MKFUNC(smb5),
+	NPCM7XX_MKFUNC(smb5b),
+	NPCM7XX_MKFUNC(smb5c),
+	NPCM7XX_MKFUNC(smb5d),
+	NPCM7XX_MKFUNC(ga20kbc),
+	NPCM7XX_MKFUNC(smb6),
+	NPCM7XX_MKFUNC(smb7),
+	NPCM7XX_MKFUNC(smb8),
+	NPCM7XX_MKFUNC(smb9),
+	NPCM7XX_MKFUNC(smb10),
+	NPCM7XX_MKFUNC(smb11),
+	NPCM7XX_MKFUNC(smb12),
+	NPCM7XX_MKFUNC(smb13),
+	NPCM7XX_MKFUNC(smb14),
+	NPCM7XX_MKFUNC(smb15),
+	NPCM7XX_MKFUNC(fanin0),
+	NPCM7XX_MKFUNC(fanin1),
+	NPCM7XX_MKFUNC(fanin2),
+	NPCM7XX_MKFUNC(fanin3),
+	NPCM7XX_MKFUNC(fanin4),
+	NPCM7XX_MKFUNC(fanin5),
+	NPCM7XX_MKFUNC(fanin6),
+	NPCM7XX_MKFUNC(fanin7),
+	NPCM7XX_MKFUNC(fanin8),
+	NPCM7XX_MKFUNC(fanin9),
+	NPCM7XX_MKFUNC(fanin10),
+	NPCM7XX_MKFUNC(fanin11),
+	NPCM7XX_MKFUNC(fanin12),
+	NPCM7XX_MKFUNC(fanin13),
+	NPCM7XX_MKFUNC(fanin14),
+	NPCM7XX_MKFUNC(fanin15),
+	NPCM7XX_MKFUNC(faninx),
+	NPCM7XX_MKFUNC(pwm0),
+	NPCM7XX_MKFUNC(pwm1),
+	NPCM7XX_MKFUNC(pwm2),
+	NPCM7XX_MKFUNC(pwm3),
+	NPCM7XX_MKFUNC(pwm4),
+	NPCM7XX_MKFUNC(pwm5),
+	NPCM7XX_MKFUNC(pwm6),
+	NPCM7XX_MKFUNC(pwm7),
+	NPCM7XX_MKFUNC(rg1),
+	NPCM7XX_MKFUNC(rg1mdio),
+	NPCM7XX_MKFUNC(rg2),
+	NPCM7XX_MKFUNC(rg2mdio),
+	NPCM7XX_MKFUNC(ddr),
+	NPCM7XX_MKFUNC(uart1),
+	NPCM7XX_MKFUNC(uart2),
+	NPCM7XX_MKFUNC(bmcuart0a),
+	NPCM7XX_MKFUNC(bmcuart0b),
+	NPCM7XX_MKFUNC(bmcuart1),
+	NPCM7XX_MKFUNC(iox1),
+	NPCM7XX_MKFUNC(iox2),
+	NPCM7XX_MKFUNC(ioxh),
+	NPCM7XX_MKFUNC(gspi),
+	NPCM7XX_MKFUNC(mmc),
+	NPCM7XX_MKFUNC(mmcwp),
+	NPCM7XX_MKFUNC(mmccd),
+	NPCM7XX_MKFUNC(mmcrst),
+	NPCM7XX_MKFUNC(mmc8),
+	NPCM7XX_MKFUNC(r1),
+	NPCM7XX_MKFUNC(r1err),
+	NPCM7XX_MKFUNC(r1md),
+	NPCM7XX_MKFUNC(r2),
+	NPCM7XX_MKFUNC(r2err),
+	NPCM7XX_MKFUNC(r2md),
+	NPCM7XX_MKFUNC(sd1),
+	NPCM7XX_MKFUNC(sd1pwr),
+	NPCM7XX_MKFUNC(wdog1),
+	NPCM7XX_MKFUNC(wdog2),
+	NPCM7XX_MKFUNC(scipme),
+	NPCM7XX_MKFUNC(sci),
+	NPCM7XX_MKFUNC(serirq),
+	NPCM7XX_MKFUNC(jtag2),
+	NPCM7XX_MKFUNC(spix),
+	NPCM7XX_MKFUNC(spixcs1),
+	NPCM7XX_MKFUNC(pspi1),
+	NPCM7XX_MKFUNC(pspi2),
+	NPCM7XX_MKFUNC(ddc),
+	NPCM7XX_MKFUNC(clkreq),
+	NPCM7XX_MKFUNC(clkout),
+	NPCM7XX_MKFUNC(spi3),
+	NPCM7XX_MKFUNC(spi3cs1),
+	NPCM7XX_MKFUNC(spi3quad),
+	NPCM7XX_MKFUNC(spi3cs2),
+	NPCM7XX_MKFUNC(spi3cs3),
+	NPCM7XX_MKFUNC(spi0cs1),
+	NPCM7XX_MKFUNC(lpc),
+	NPCM7XX_MKFUNC(lpcclk),
+	NPCM7XX_MKFUNC(espi),
+	NPCM7XX_MKFUNC(lkgpo0),
+	NPCM7XX_MKFUNC(lkgpo1),
+	NPCM7XX_MKFUNC(lkgpo2),
+	NPCM7XX_MKFUNC(nprd_smi),
+	NPCM7XX_MKFUNC(hgpio0),
+	NPCM7XX_MKFUNC(hgpio1),
+	NPCM7XX_MKFUNC(hgpio2),
+	NPCM7XX_MKFUNC(hgpio3),
+	NPCM7XX_MKFUNC(hgpio4),
+	NPCM7XX_MKFUNC(hgpio5),
+	NPCM7XX_MKFUNC(hgpio6),
+	NPCM7XX_MKFUNC(hgpio7),
+};
+
+#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
+	[a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
+			.fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
+			.fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
+			.flag = k }
+
+/* Drive strength controlled by NPCM7XX_GP_N_ODSC */
+#define DRIVE_STRENGTH_LO_SHIFT		8
+#define DRIVE_STRENGTH_HI_SHIFT		12
+#define DRIVE_STRENGTH_MASK		0x0000FF00
+
+#define DS(lo, hi)	(((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
+			 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
+#define DSLO(x)		(((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
+#define DSHI(x)		(((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
+
+#define GPI		0x1 /* Not GPO */
+#define GPO		0x2 /* Not GPI */
+#define SLEW		0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
+#define SLEWLPC		0x8 /* Has Slew Control, SRCNT.3 */
+
+struct npcm7xx_pincfg {
+	int flag;
+	int fn0, reg0, bit0;
+	int fn1, reg1, bit1;
+	int fn2, reg2, bit2;
+};
+
+static const struct npcm7xx_pincfg pincfgs[] = {
+	/*	PIN	  FUNCTION 1		   FUNCTION 2		  FUNCTION 3	    FLAGS */
+	NPCM7XX_PINCFG(0,	 iox1, MFSEL1, 30,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(1,	 iox1, MFSEL1, 30,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(2,	 iox1, MFSEL1, 30,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(3,	 iox1, MFSEL1, 30,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(4,	 iox2, MFSEL3, 14,	 smb1d, I2CSEGSEL, 7,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(5,	 iox2, MFSEL3, 14,	 smb1d, I2CSEGSEL, 7,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(6,	 iox2, MFSEL3, 14,	 smb2d, I2CSEGSEL, 10,  none, NONE, 0,       SLEW),
+	NPCM7XX_PINCFG(7,	 iox2, MFSEL3, 14,	 smb2d, I2CSEGSEL, 10,  none, NONE, 0,       SLEW),
+	NPCM7XX_PINCFG(8,      lkgpo1, FLOCKR1, 4,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(9,      lkgpo2, FLOCKR1, 8,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(10,	 ioxh, MFSEL3, 18,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(11,	 ioxh, MFSEL3, 18,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(12,	 gspi, MFSEL1, 24,	 smb5b, I2CSEGSEL, 19,  none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(13,	 gspi, MFSEL1, 24,	 smb5b, I2CSEGSEL, 19,  none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(14,	 gspi, MFSEL1, 24,	 smb5c, I2CSEGSEL, 20,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(15,	 gspi, MFSEL1, 24,	 smb5c, I2CSEGSEL, 20,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(16,     lkgpo0, FLOCKR1, 0,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(17,      pspi2, MFSEL3, 13,     smb4den, I2CSEGSEL, 23,  none, NONE, 0,       DS(8, 12)),
+	NPCM7XX_PINCFG(18,      pspi2, MFSEL3, 13,	 smb4b, I2CSEGSEL, 14,  none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(19,      pspi2, MFSEL3, 13,	 smb4b, I2CSEGSEL, 14,  none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(20,	hgpio0, MFSEL2, 24,      smb15, MFSEL3, 8,      smb4c, I2CSEGSEL, 15,	     0),
+	NPCM7XX_PINCFG(21,	hgpio1, MFSEL2, 25,      smb15, MFSEL3, 8,      smb4c, I2CSEGSEL, 15,	     0),
+	NPCM7XX_PINCFG(22,      hgpio2, MFSEL2, 26,	 smb14, MFSEL3, 7,      smb4d, I2CSEGSEL, 16,	     0),
+	NPCM7XX_PINCFG(23,      hgpio3, MFSEL2, 27,	 smb14, MFSEL3, 7,      smb4d, I2CSEGSEL, 16,	     0),
+	NPCM7XX_PINCFG(24,	 hgpio4, MFSEL2, 28,	ioxh, MFSEL3, 18,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(25,	 hgpio5, MFSEL2, 29,	ioxh, MFSEL3, 18,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(26,	 smb5, MFSEL1, 2,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(27,	 smb5, MFSEL1, 2,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(28,	 smb4, MFSEL1, 1,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(29,	 smb4, MFSEL1, 1,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(30,	 smb3, MFSEL1, 0,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(31,	 smb3, MFSEL1, 0,	  none, NONE, 0,	none, NONE, 0,	     0),
+
+	NPCM7XX_PINCFG(32,    spi0cs1, MFSEL1, 3,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(33,   none, NONE, 0,     none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(34,   none, NONE, 0,     none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(37,	smb3c, I2CSEGSEL, 12,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(38,	smb3c, I2CSEGSEL, 12,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(39,	smb3b, I2CSEGSEL, 11,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(40,	smb3b, I2CSEGSEL, 11,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(41,  bmcuart0a, MFSEL1, 9,         none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(42,  bmcuart0a, MFSEL1, 9,         none, NONE, 0,	none, NONE, 0,	     DS(2, 4) | GPO),
+	NPCM7XX_PINCFG(43,      uart1, MFSEL1, 10,	 jtag2, MFSEL4, 0,  bmcuart1, MFSEL3, 24,    0),
+	NPCM7XX_PINCFG(44,      uart1, MFSEL1, 10,	 jtag2, MFSEL4, 0,  bmcuart1, MFSEL3, 24,    0),
+	NPCM7XX_PINCFG(45,      uart1, MFSEL1, 10,	 jtag2, MFSEL4, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(46,      uart1, MFSEL1, 10,	 jtag2, MFSEL4, 0,	none, NONE, 0,	     DS(2, 8)),
+	NPCM7XX_PINCFG(47,      uart1, MFSEL1, 10,	 jtag2, MFSEL4, 0,	none, NONE, 0,	     DS(2, 8)),
+	NPCM7XX_PINCFG(48,	uart2, MFSEL1, 11,   bmcuart0b, MFSEL4, 1,      none, NONE, 0,	     GPO),
+	NPCM7XX_PINCFG(49,	uart2, MFSEL1, 11,   bmcuart0b, MFSEL4, 1,      none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(50,	uart2, MFSEL1, 11,	  none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(51,	uart2, MFSEL1, 11,	  none, NONE, 0,        none, NONE, 0,	     GPO),
+	NPCM7XX_PINCFG(52,	uart2, MFSEL1, 11,	  none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(53,	uart2, MFSEL1, 11,	  none, NONE, 0,        none, NONE, 0,	     GPO),
+	NPCM7XX_PINCFG(54,	uart2, MFSEL1, 11,	  none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(55,	uart2, MFSEL1, 11,	  none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(56,	r1err, MFSEL1, 12,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(57,       r1md, MFSEL1, 13,        none, NONE, 0,        none, NONE, 0,       DS(2, 4)),
+	NPCM7XX_PINCFG(58,       r1md, MFSEL1, 13,        none, NONE, 0,	none, NONE, 0,	     DS(2, 4)),
+	NPCM7XX_PINCFG(59,	hgpio6, MFSEL2, 30,	  smb3d, I2CSEGSEL, 13,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(60,	hgpio7, MFSEL2, 31,	  smb3d, I2CSEGSEL, 13,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(61,      uart1, MFSEL1, 10,	  none, NONE, 0,	none, NONE, 0,     GPO),
+	NPCM7XX_PINCFG(62,      uart1, MFSEL1, 10,    bmcuart1, MFSEL3, 24,	none, NONE, 0,     GPO),
+	NPCM7XX_PINCFG(63,      uart1, MFSEL1, 10,    bmcuart1, MFSEL3, 24,	none, NONE, 0,     GPO),
+
+	NPCM7XX_PINCFG(64,    fanin0, MFSEL2, 0,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(65,    fanin1, MFSEL2, 1,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(66,    fanin2, MFSEL2, 2,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(67,    fanin3, MFSEL2, 3,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(68,    fanin4, MFSEL2, 4,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(69,    fanin5, MFSEL2, 5,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(70,    fanin6, MFSEL2, 6,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(71,    fanin7, MFSEL2, 7,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(72,    fanin8, MFSEL2, 8,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(73,    fanin9, MFSEL2, 9,          none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(74,    fanin10, MFSEL2, 10,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(75,    fanin11, MFSEL2, 11,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(76,    fanin12, MFSEL2, 12,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(77,    fanin13, MFSEL2, 13,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(78,    fanin14, MFSEL2, 14,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(79,    fanin15, MFSEL2, 15,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(80,	 pwm0, MFSEL2, 16,        none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(81,	 pwm1, MFSEL2, 17,        none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(82,	 pwm2, MFSEL2, 18,        none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(83,	 pwm3, MFSEL2, 19,        none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(84,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(85,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(86,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(87,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(88,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(89,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(90,      r2err, MFSEL1, 15,        none, NONE, 0,        none, NONE, 0,       0),
+	NPCM7XX_PINCFG(91,       r2md, MFSEL1, 16,	  none, NONE, 0,        none, NONE, 0,	     DS(2, 4)),
+	NPCM7XX_PINCFG(92,       r2md, MFSEL1, 16,	  none, NONE, 0,        none, NONE, 0,	     DS(2, 4)),
+	NPCM7XX_PINCFG(93,    ga20kbc, MFSEL1, 17,	 smb5d, I2CSEGSEL, 21,  none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(94,    ga20kbc, MFSEL1, 17,	 smb5d, I2CSEGSEL, 21,  none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(95,	  lpc, NONE, 0,		  espi, MFSEL4, 8,      gpio, MFSEL1, 26,    0),
+
+	NPCM7XX_PINCFG(96,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(97,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(98,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(99,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(100,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(101,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(102,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(103,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(104,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(105,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(106,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(107,	  rg1, MFSEL4, 22,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(108,   rg1mdio, MFSEL4, 21,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(109,   rg1mdio, MFSEL4, 21,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(110,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(111,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(112,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(113,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(114,	 smb0, MFSEL1, 6,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(115,	 smb0, MFSEL1, 6,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(116,	 smb1, MFSEL1, 7,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(117,	 smb1, MFSEL1, 7,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(118,	 smb2, MFSEL1, 8,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(119,	 smb2, MFSEL1, 8,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(120,	smb2c, I2CSEGSEL, 9,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(121,	smb2c, I2CSEGSEL, 9,      none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(122,	smb2b, I2CSEGSEL, 8,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(123,	smb2b, I2CSEGSEL, 8,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(124,	smb1c, I2CSEGSEL, 6,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(125,	smb1c, I2CSEGSEL, 6,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(126,	smb1b, I2CSEGSEL, 5,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(127,	smb1b, I2CSEGSEL, 5,	  none, NONE, 0,	none, NONE, 0,	     SLEW),
+
+	NPCM7XX_PINCFG(128,	 smb8, MFSEL4, 11,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(129,	 smb8, MFSEL4, 11,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(130,	 smb9, MFSEL4, 12,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(131,	 smb9, MFSEL4, 12,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(132,	smb10, MFSEL4, 13,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(133,	smb10, MFSEL4, 13,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(134,	smb11, MFSEL4, 14,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(135,	smb11, MFSEL4, 14,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(136,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(137,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(138,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(139,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(140,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(141,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(142,	  sd1, MFSEL3, 12,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(143,       sd1, MFSEL3, 12,      sd1pwr, MFSEL4, 5,      none, NONE, 0,       0),
+	NPCM7XX_PINCFG(144,	 pwm4, MFSEL2, 20,	  none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(145,	 pwm5, MFSEL2, 21,	  none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(146,	 pwm6, MFSEL2, 22,	  none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(147,	 pwm7, MFSEL2, 23,	  none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(148,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(149,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(150,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(151,	 mmc8, MFSEL3, 11,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(152,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(153,     mmcwp, FLOCKR1, 24,       none, NONE, 0,	none, NONE, 0,	     0),  /* Z1/A1 */
+	NPCM7XX_PINCFG(154,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(155,     mmccd, MFSEL3, 25,      mmcrst, MFSEL4, 6,      none, NONE, 0,       0),  /* Z1/A1 */
+	NPCM7XX_PINCFG(156,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(157,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(158,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(159,	  mmc, MFSEL3, 10,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+
+	NPCM7XX_PINCFG(160,    clkout, MFSEL1, 21,        none, NONE, 0,        none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(161,	  lpc, NONE, 0,		  espi, MFSEL4, 8,      gpio, MFSEL1, 26,    DS(8, 12)),
+	NPCM7XX_PINCFG(162,    serirq, NONE, 0,           gpio, MFSEL1, 31,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(163,	  lpc, NONE, 0,		  espi, MFSEL4, 8,      gpio, MFSEL1, 26,    0),
+	NPCM7XX_PINCFG(164,	  lpc, NONE, 0,		  espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
+	NPCM7XX_PINCFG(165,	  lpc, NONE, 0,		  espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
+	NPCM7XX_PINCFG(166,	  lpc, NONE, 0,		  espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
+	NPCM7XX_PINCFG(167,	  lpc, NONE, 0,		  espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
+	NPCM7XX_PINCFG(168,    lpcclk, NONE, 0,           espi, MFSEL4, 8,      gpio, MFSEL3, 16,    0),
+	NPCM7XX_PINCFG(169,    scipme, MFSEL3, 0,         none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(170,	  sci, MFSEL1, 22,        none, NONE, 0,        none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(171,	 smb6, MFSEL3, 1,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(172,	 smb6, MFSEL3, 1,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(173,	 smb7, MFSEL3, 2,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(174,	 smb7, MFSEL3, 2,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(175,	pspi1, MFSEL3, 4,       faninx, MFSEL3, 3,      none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(176,     pspi1, MFSEL3, 4,       faninx, MFSEL3, 3,      none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(177,     pspi1, MFSEL3, 4,       faninx, MFSEL3, 3,      none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(178,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(179,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(180,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(181,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(182,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(183,     spi3, MFSEL4, 16,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(184,     spi3, MFSEL4, 16,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW | GPO),
+	NPCM7XX_PINCFG(185,     spi3, MFSEL4, 16,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW | GPO),
+	NPCM7XX_PINCFG(186,     spi3, MFSEL4, 16,	  none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(187,   spi3cs1, MFSEL4, 17,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(188,  spi3quad, MFSEL4, 20,     spi3cs2, MFSEL4, 18,     none, NONE, 0,    DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(189,  spi3quad, MFSEL4, 20,     spi3cs3, MFSEL4, 19,     none, NONE, 0,    DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(190,      gpio, FLOCKR1, 20,   nprd_smi, NONE, 0,	none, NONE, 0,	     DS(2, 4)),
+	NPCM7XX_PINCFG(191,	 none, NONE, 0,		  none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),  /* XX */
+
+	NPCM7XX_PINCFG(192,	 none, NONE, 0,		  none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),  /* XX */
+	NPCM7XX_PINCFG(193,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(194,	smb0b, I2CSEGSEL, 0,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(195,	smb0b, I2CSEGSEL, 0,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(196,	smb0c, I2CSEGSEL, 1,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(197,   smb0den, I2CSEGSEL, 22,     none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(198,	smb0d, I2CSEGSEL, 2,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(199,	smb0d, I2CSEGSEL, 2,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(200,        r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       0),
+	NPCM7XX_PINCFG(201,	   r1, MFSEL3, 9,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(202,	smb0c, I2CSEGSEL, 1,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(203,    faninx, MFSEL3, 3,         none, NONE, 0,	none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(204,	  ddc, NONE, 0,           gpio, MFSEL3, 22,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(205,	  ddc, NONE, 0,           gpio, MFSEL3, 22,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(206,	  ddc, NONE, 0,           gpio, MFSEL3, 22,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(207,	  ddc, NONE, 0,           gpio, MFSEL3, 22,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(208,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(209,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(210,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(211,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(212,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(213,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(214,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(215,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(216,   rg2mdio, MFSEL4, 23,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(217,   rg2mdio, MFSEL4, 23,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
+	NPCM7XX_PINCFG(218,     wdog1, MFSEL3, 19,        none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(219,     wdog2, MFSEL3, 20,        none, NONE, 0,	none, NONE, 0,	     DS(4, 8)),
+	NPCM7XX_PINCFG(220,	smb12, MFSEL3, 5,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(221,	smb12, MFSEL3, 5,	  none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(222,     smb13, MFSEL3, 6,         none, NONE, 0,	none, NONE, 0,	     0),
+	NPCM7XX_PINCFG(223,     smb13, MFSEL3, 6,         none, NONE, 0,	none, NONE, 0,	     0),
+
+	NPCM7XX_PINCFG(224,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     SLEW),
+	NPCM7XX_PINCFG(225,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW | GPO),
+	NPCM7XX_PINCFG(226,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW | GPO),
+	NPCM7XX_PINCFG(227,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(228,   spixcs1, MFSEL4, 28,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(229,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(230,	 spix, MFSEL4, 27,        none, NONE, 0,	none, NONE, 0,	     DS(8, 12) | SLEW),
+	NPCM7XX_PINCFG(231,    clkreq, MFSEL4, 9,         none, NONE, 0,        none, NONE, 0,	     DS(8, 12)),
+	NPCM7XX_PINCFG(253,	 none, NONE, 0,		  none, NONE, 0,	none, NONE, 0,	     GPI), /* SDHC1 power */
+	NPCM7XX_PINCFG(254,	 none, NONE, 0,		  none, NONE, 0,	none, NONE, 0,	     GPI), /* SDHC2 power */
+	NPCM7XX_PINCFG(255,	 none, NONE, 0,		  none, NONE, 0,	none, NONE, 0,	     GPI), /* DACOSEL */
+};
+
+#define NPCM7XX_PIN(a, b) { .number = a, .name = b }
+struct npcm7xx_pin_desc {
+	unsigned int number;
+	const char *name;
+};
+
+/* number, name, drv_data */
+static const struct npcm7xx_pin_desc npcm7xx_pins[] = {
+	NPCM7XX_PIN(0,	"GPIO0/IOX1DI"),
+	NPCM7XX_PIN(1,	"GPIO1/IOX1LD"),
+	NPCM7XX_PIN(2,	"GPIO2/IOX1CK"),
+	NPCM7XX_PIN(3,	"GPIO3/IOX1D0"),
+	NPCM7XX_PIN(4,	"GPIO4/IOX2DI/SMB1DSDA"),
+	NPCM7XX_PIN(5,	"GPIO5/IOX2LD/SMB1DSCL"),
+	NPCM7XX_PIN(6,	"GPIO6/IOX2CK/SMB2DSDA"),
+	NPCM7XX_PIN(7,	"GPIO7/IOX2D0/SMB2DSCL"),
+	NPCM7XX_PIN(8,	"GPIO8/LKGPO1"),
+	NPCM7XX_PIN(9,	"GPIO9/LKGPO2"),
+	NPCM7XX_PIN(10, "GPIO10/IOXHLD"),
+	NPCM7XX_PIN(11, "GPIO11/IOXHCK"),
+	NPCM7XX_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
+	NPCM7XX_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
+	NPCM7XX_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
+	NPCM7XX_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
+	NPCM7XX_PIN(16, "GPIO16/LKGPO0"),
+	NPCM7XX_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
+	NPCM7XX_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
+	NPCM7XX_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
+	NPCM7XX_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
+	NPCM7XX_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
+	NPCM7XX_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
+	NPCM7XX_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
+	NPCM7XX_PIN(24, "GPIO24/IOXHDO"),
+	NPCM7XX_PIN(25, "GPIO25/IOXHDI"),
+	NPCM7XX_PIN(26, "GPIO26/SMB5SDA"),
+	NPCM7XX_PIN(27, "GPIO27/SMB5SCL"),
+	NPCM7XX_PIN(28, "GPIO28/SMB4SDA"),
+	NPCM7XX_PIN(29, "GPIO29/SMB4SCL"),
+	NPCM7XX_PIN(30, "GPIO30/SMB3SDA"),
+	NPCM7XX_PIN(31, "GPIO31/SMB3SCL"),
+
+	NPCM7XX_PIN(32, "GPIO32/nSPI0CS1"),
+	NPCM7XX_PIN(33, "SPI0D2"),
+	NPCM7XX_PIN(34, "SPI0D3"),
+	NPCM7XX_PIN(35, "NA"),
+	NPCM7XX_PIN(36, "NA"),
+	NPCM7XX_PIN(37, "GPIO37/SMB3CSDA"),
+	NPCM7XX_PIN(38, "GPIO38/SMB3CSCL"),
+	NPCM7XX_PIN(39, "GPIO39/SMB3BSDA"),
+	NPCM7XX_PIN(40, "GPIO40/SMB3BSCL"),
+	NPCM7XX_PIN(41, "GPIO41/BSPRXD"),
+	NPCM7XX_PIN(42, "GPO42/BSPTXD/STRAP11"),
+	NPCM7XX_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
+	NPCM7XX_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
+	NPCM7XX_PIN(45, "GPIO45/nDCD1/JTDO2"),
+	NPCM7XX_PIN(46, "GPIO46/nDSR1/JTCK2"),
+	NPCM7XX_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
+	NPCM7XX_PIN(48, "GPIO48/TXD2/BSPTXD"),
+	NPCM7XX_PIN(49, "GPIO49/RXD2/BSPRXD"),
+	NPCM7XX_PIN(50, "GPIO50/nCTS2"),
+	NPCM7XX_PIN(51, "GPO51/nRTS2/STRAP2"),
+	NPCM7XX_PIN(52, "GPIO52/nDCD2"),
+	NPCM7XX_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
+	NPCM7XX_PIN(54, "GPIO54/nDSR2"),
+	NPCM7XX_PIN(55, "GPIO55/nRI2"),
+	NPCM7XX_PIN(56, "GPIO56/R1RXERR"),
+	NPCM7XX_PIN(57, "GPIO57/R1MDC"),
+	NPCM7XX_PIN(58, "GPIO58/R1MDIO"),
+	NPCM7XX_PIN(59, "GPIO59/SMB3DSDA"),
+	NPCM7XX_PIN(60, "GPIO60/SMB3DSCL"),
+	NPCM7XX_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
+	NPCM7XX_PIN(62, "GPO62/nRTST1/STRAP5"),
+	NPCM7XX_PIN(63, "GPO63/TXD1/STRAP4"),
+
+	NPCM7XX_PIN(64, "GPIO64/FANIN0"),
+	NPCM7XX_PIN(65, "GPIO65/FANIN1"),
+	NPCM7XX_PIN(66, "GPIO66/FANIN2"),
+	NPCM7XX_PIN(67, "GPIO67/FANIN3"),
+	NPCM7XX_PIN(68, "GPIO68/FANIN4"),
+	NPCM7XX_PIN(69, "GPIO69/FANIN5"),
+	NPCM7XX_PIN(70, "GPIO70/FANIN6"),
+	NPCM7XX_PIN(71, "GPIO71/FANIN7"),
+	NPCM7XX_PIN(72, "GPIO72/FANIN8"),
+	NPCM7XX_PIN(73, "GPIO73/FANIN9"),
+	NPCM7XX_PIN(74, "GPIO74/FANIN10"),
+	NPCM7XX_PIN(75, "GPIO75/FANIN11"),
+	NPCM7XX_PIN(76, "GPIO76/FANIN12"),
+	NPCM7XX_PIN(77, "GPIO77/FANIN13"),
+	NPCM7XX_PIN(78, "GPIO78/FANIN14"),
+	NPCM7XX_PIN(79, "GPIO79/FANIN15"),
+	NPCM7XX_PIN(80, "GPIO80/PWM0"),
+	NPCM7XX_PIN(81, "GPIO81/PWM1"),
+	NPCM7XX_PIN(82, "GPIO82/PWM2"),
+	NPCM7XX_PIN(83, "GPIO83/PWM3"),
+	NPCM7XX_PIN(84, "GPIO84/R2TXD0"),
+	NPCM7XX_PIN(85, "GPIO85/R2TXD1"),
+	NPCM7XX_PIN(86, "GPIO86/R2TXEN"),
+	NPCM7XX_PIN(87, "GPIO87/R2RXD0"),
+	NPCM7XX_PIN(88, "GPIO88/R2RXD1"),
+	NPCM7XX_PIN(89, "GPIO89/R2CRSDV"),
+	NPCM7XX_PIN(90, "GPIO90/R2RXERR"),
+	NPCM7XX_PIN(91, "GPIO91/R2MDC"),
+	NPCM7XX_PIN(92, "GPIO92/R2MDIO"),
+	NPCM7XX_PIN(93, "GPIO93/GA20/SMB5DSCL"),
+	NPCM7XX_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
+	NPCM7XX_PIN(95, "GPIO95/nLRESET/nESPIRST"),
+
+	NPCM7XX_PIN(96, "GPIO96/RG1TXD0"),
+	NPCM7XX_PIN(97, "GPIO97/RG1TXD1"),
+	NPCM7XX_PIN(98, "GPIO98/RG1TXD2"),
+	NPCM7XX_PIN(99, "GPIO99/RG1TXD3"),
+	NPCM7XX_PIN(100, "GPIO100/RG1TXC"),
+	NPCM7XX_PIN(101, "GPIO101/RG1TXCTL"),
+	NPCM7XX_PIN(102, "GPIO102/RG1RXD0"),
+	NPCM7XX_PIN(103, "GPIO103/RG1RXD1"),
+	NPCM7XX_PIN(104, "GPIO104/RG1RXD2"),
+	NPCM7XX_PIN(105, "GPIO105/RG1RXD3"),
+	NPCM7XX_PIN(106, "GPIO106/RG1RXC"),
+	NPCM7XX_PIN(107, "GPIO107/RG1RXCTL"),
+	NPCM7XX_PIN(108, "GPIO108/RG1MDC"),
+	NPCM7XX_PIN(109, "GPIO109/RG1MDIO"),
+	NPCM7XX_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
+	NPCM7XX_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
+	NPCM7XX_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
+	NPCM7XX_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
+	NPCM7XX_PIN(114, "GPIO114/SMB0SCL"),
+	NPCM7XX_PIN(115, "GPIO115/SMB0SDA"),
+	NPCM7XX_PIN(116, "GPIO116/SMB1SCL"),
+	NPCM7XX_PIN(117, "GPIO117/SMB1SDA"),
+	NPCM7XX_PIN(118, "GPIO118/SMB2SCL"),
+	NPCM7XX_PIN(119, "GPIO119/SMB2SDA"),
+	NPCM7XX_PIN(120, "GPIO120/SMB2CSDA"),
+	NPCM7XX_PIN(121, "GPIO121/SMB2CSCL"),
+	NPCM7XX_PIN(122, "GPIO122/SMB2BSDA"),
+	NPCM7XX_PIN(123, "GPIO123/SMB2BSCL"),
+	NPCM7XX_PIN(124, "GPIO124/SMB1CSDA"),
+	NPCM7XX_PIN(125, "GPIO125/SMB1CSCL"),
+	NPCM7XX_PIN(126, "GPIO126/SMB1BSDA"),
+	NPCM7XX_PIN(127, "GPIO127/SMB1BSCL"),
+
+	NPCM7XX_PIN(128, "GPIO128/SMB8SCL"),
+	NPCM7XX_PIN(129, "GPIO129/SMB8SDA"),
+	NPCM7XX_PIN(130, "GPIO130/SMB9SCL"),
+	NPCM7XX_PIN(131, "GPIO131/SMB9SDA"),
+	NPCM7XX_PIN(132, "GPIO132/SMB10SCL"),
+	NPCM7XX_PIN(133, "GPIO133/SMB10SDA"),
+	NPCM7XX_PIN(134, "GPIO134/SMB11SCL"),
+	NPCM7XX_PIN(135, "GPIO135/SMB11SDA"),
+	NPCM7XX_PIN(136, "GPIO136/SD1DT0"),
+	NPCM7XX_PIN(137, "GPIO137/SD1DT1"),
+	NPCM7XX_PIN(138, "GPIO138/SD1DT2"),
+	NPCM7XX_PIN(139, "GPIO139/SD1DT3"),
+	NPCM7XX_PIN(140, "GPIO140/SD1CLK"),
+	NPCM7XX_PIN(141, "GPIO141/SD1WP"),
+	NPCM7XX_PIN(142, "GPIO142/SD1CMD"),
+	NPCM7XX_PIN(143, "GPIO143/SD1CD/SD1PWR"),
+	NPCM7XX_PIN(144, "GPIO144/PWM4"),
+	NPCM7XX_PIN(145, "GPIO145/PWM5"),
+	NPCM7XX_PIN(146, "GPIO146/PWM6"),
+	NPCM7XX_PIN(147, "GPIO147/PWM7"),
+	NPCM7XX_PIN(148, "GPIO148/MMCDT4"),
+	NPCM7XX_PIN(149, "GPIO149/MMCDT5"),
+	NPCM7XX_PIN(150, "GPIO150/MMCDT6"),
+	NPCM7XX_PIN(151, "GPIO151/MMCDT7"),
+	NPCM7XX_PIN(152, "GPIO152/MMCCLK"),
+	NPCM7XX_PIN(153, "GPIO153/MMCWP"),
+	NPCM7XX_PIN(154, "GPIO154/MMCCMD"),
+	NPCM7XX_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
+	NPCM7XX_PIN(156, "GPIO156/MMCDT0"),
+	NPCM7XX_PIN(157, "GPIO157/MMCDT1"),
+	NPCM7XX_PIN(158, "GPIO158/MMCDT2"),
+	NPCM7XX_PIN(159, "GPIO159/MMCDT3"),
+
+	NPCM7XX_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
+	NPCM7XX_PIN(161, "GPIO161/nLFRAME/nESPICS"),
+	NPCM7XX_PIN(162, "GPIO162/SERIRQ"),
+	NPCM7XX_PIN(163, "GPIO163/LCLK/ESPICLK"),
+	NPCM7XX_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
+	NPCM7XX_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
+	NPCM7XX_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
+	NPCM7XX_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
+	NPCM7XX_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
+	NPCM7XX_PIN(169, "GPIO169/nSCIPME"),
+	NPCM7XX_PIN(170, "GPIO170/nSMI"),
+	NPCM7XX_PIN(171, "GPIO171/SMB6SCL"),
+	NPCM7XX_PIN(172, "GPIO172/SMB6SDA"),
+	NPCM7XX_PIN(173, "GPIO173/SMB7SCL"),
+	NPCM7XX_PIN(174, "GPIO174/SMB7SDA"),
+	NPCM7XX_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
+	NPCM7XX_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
+	NPCM7XX_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
+	NPCM7XX_PIN(178, "GPIO178/R1TXD0"),
+	NPCM7XX_PIN(179, "GPIO179/R1TXD1"),
+	NPCM7XX_PIN(180, "GPIO180/R1TXEN"),
+	NPCM7XX_PIN(181, "GPIO181/R1RXD0"),
+	NPCM7XX_PIN(182, "GPIO182/R1RXD1"),
+	NPCM7XX_PIN(183, "GPIO183/SPI3CK"),
+	NPCM7XX_PIN(184, "GPO184/SPI3D0/STRAP9"),
+	NPCM7XX_PIN(185, "GPO185/SPI3D1/STRAP10"),
+	NPCM7XX_PIN(186, "GPIO186/nSPI3CS0"),
+	NPCM7XX_PIN(187, "GPIO187/nSPI3CS1"),
+	NPCM7XX_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
+	NPCM7XX_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
+	NPCM7XX_PIN(190, "GPIO190/nPRD_SMI"),
+	NPCM7XX_PIN(191, "GPIO191"),
+
+	NPCM7XX_PIN(192, "GPIO192"),
+	NPCM7XX_PIN(193, "GPIO193/R1CRSDV"),
+	NPCM7XX_PIN(194, "GPIO194/SMB0BSCL"),
+	NPCM7XX_PIN(195, "GPIO195/SMB0BSDA"),
+	NPCM7XX_PIN(196, "GPIO196/SMB0CSCL"),
+	NPCM7XX_PIN(197, "GPIO197/SMB0DEN"),
+	NPCM7XX_PIN(198, "GPIO198/SMB0DSDA"),
+	NPCM7XX_PIN(199, "GPIO199/SMB0DSCL"),
+	NPCM7XX_PIN(200, "GPIO200/R2CK"),
+	NPCM7XX_PIN(201, "GPIO201/R1CK"),
+	NPCM7XX_PIN(202, "GPIO202/SMB0CSDA"),
+	NPCM7XX_PIN(203, "GPIO203/FANIN16"),
+	NPCM7XX_PIN(204, "GPIO204/DDC2SCL"),
+	NPCM7XX_PIN(205, "GPIO205/DDC2SDA"),
+	NPCM7XX_PIN(206, "GPIO206/HSYNC2"),
+	NPCM7XX_PIN(207, "GPIO207/VSYNC2"),
+	NPCM7XX_PIN(208, "GPIO208/RG2TXC/DVCK"),
+	NPCM7XX_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
+	NPCM7XX_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
+	NPCM7XX_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
+	NPCM7XX_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
+	NPCM7XX_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
+	NPCM7XX_PIN(214, "GPIO214/RG2RXC/DDRV9"),
+	NPCM7XX_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
+	NPCM7XX_PIN(216, "GPIO216/RG2MDC/DDRV11"),
+	NPCM7XX_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
+	NPCM7XX_PIN(218, "GPIO218/nWDO1"),
+	NPCM7XX_PIN(219, "GPIO219/nWDO2"),
+	NPCM7XX_PIN(220, "GPIO220/SMB12SCL"),
+	NPCM7XX_PIN(221, "GPIO221/SMB12SDA"),
+	NPCM7XX_PIN(222, "GPIO222/SMB13SCL"),
+	NPCM7XX_PIN(223, "GPIO223/SMB13SDA"),
+	NPCM7XX_PIN(224, "GPIO224/SPIXCK"),
+	NPCM7XX_PIN(225, "GPO225/SPIXD0/STRAP12"),
+	NPCM7XX_PIN(226, "GPO226/SPIXD1/STRAP13"),
+	NPCM7XX_PIN(227, "GPIO227/nSPIXCS0"),
+	NPCM7XX_PIN(228, "GPIO228/nSPIXCS1"),
+	NPCM7XX_PIN(229, "GPO229/SPIXD2/STRAP3"),
+	NPCM7XX_PIN(230, "GPIO230/SPIXD3"),
+	NPCM7XX_PIN(231, "GPIO231/nCLKREQ"),
+	NPCM7XX_PIN(232, "NA"),
+	NPCM7XX_PIN(233, "NA"),
+	NPCM7XX_PIN(234, "NA"),
+	NPCM7XX_PIN(235, "NA"),
+	NPCM7XX_PIN(236, "NA"),
+	NPCM7XX_PIN(237, "NA"),
+	NPCM7XX_PIN(238, "NA"),
+	NPCM7XX_PIN(239, "NA"),
+	NPCM7XX_PIN(240, "NA"),
+	NPCM7XX_PIN(241, "NA"),
+	NPCM7XX_PIN(242, "NA"),
+	NPCM7XX_PIN(243, "NA"),
+	NPCM7XX_PIN(244, "NA"),
+	NPCM7XX_PIN(245, "NA"),
+	NPCM7XX_PIN(246, "NA"),
+	NPCM7XX_PIN(247, "NA"),
+	NPCM7XX_PIN(248, "NA"),
+	NPCM7XX_PIN(249, "NA"),
+	NPCM7XX_PIN(250, "NA"),
+	NPCM7XX_PIN(251, "NA"),
+	NPCM7XX_PIN(252, "NA"),
+	NPCM7XX_PIN(253, "NA"),
+	NPCM7XX_PIN(254, "NA"),
+	NPCM7XX_PIN(255, "GPI255/DACOSEL"),
+};
+
+struct npcm7xx_pinctrl_priv {
+	void __iomem *gpio_base;
+	struct regmap *gcr_regmap;
+	struct regmap *rst_regmap;
+};
+
+static int npcm7xx_pinctrl_probe(struct udevice *dev)
+{
+	struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
+
+	priv->gpio_base = dev_read_addr_ptr(dev);
+	if (!priv->gpio_base)
+		return -EINVAL;
+
+	priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr");
+	if (IS_ERR(priv->gcr_regmap))
+		return -EINVAL;
+
+	priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst");
+	if (IS_ERR(priv->rst_regmap))
+		return -EINVAL;
+
+	return 0;
+}
+
+/* Enable mode in pin group */
+static void npcm7xx_setfunc(struct udevice *dev, const int *pin,
+			    int pin_number, int mode)
+{
+	struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct npcm7xx_pincfg *cfg;
+	int i;
+
+	for (i = 0 ; i < pin_number ; i++) {
+		cfg = &pincfgs[pin[i]];
+		if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
+			if (cfg->reg0) {
+				if (cfg->fn0 == mode)
+					regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), BIT(cfg->bit0));
+				else
+					regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), 0);
+			}
+			if (cfg->reg1) {
+				if (cfg->fn1 == mode)
+					regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), BIT(cfg->bit1));
+				else
+					regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), 0);
+			}
+			if (cfg->reg2) {
+				if (cfg->fn2 == mode)
+					regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), BIT(cfg->bit2));
+				else
+					regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), 0);
+			}
+		}
+	}
+}
+
+static int npcm7xx_get_pins_count(struct udevice *dev)
+{
+	return ARRAY_SIZE(npcm7xx_pins);
+}
+
+static const char *npcm7xx_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	return npcm7xx_pins[selector].name;
+}
+
+static int npcm7xx_get_groups_count(struct udevice *dev)
+{
+	return ARRAY_SIZE(npcm7xx_groups);
+}
+
+static const char *npcm7xx_get_group_name(struct udevice *dev,
+					  unsigned int selector)
+{
+	return npcm7xx_groups[selector].name;
+}
+
+static int npcm7xx_get_functions_count(struct udevice *dev)
+{
+	return ARRAY_SIZE(npcm7xx_funcs);
+}
+
+static const char *npcm7xx_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return npcm7xx_funcs[selector].name;
+}
+
+static int npcm7xx_pinmux_set(struct udevice *dev,
+			unsigned int group,
+			unsigned int function)
+{
+	dev_dbg(dev, "set_mux: %d, %d[%s]\n", function, group,
+		npcm7xx_groups[group].name);
+
+	npcm7xx_setfunc(dev, npcm7xx_groups[group].pins,
+			npcm7xx_groups[group].npins, group);
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(PINCONF)
+
+#define PIN_CONFIG_PERSIST_STATE (PIN_CONFIG_END + 1)
+#define PIN_CONFIG_POLARITY_STATE (PIN_CONFIG_END + 2)
+#define PIN_CONFIG_EVENT_CLEAR (PIN_CONFIG_END + 3)
+
+static const struct pinconf_param npcm7xx_conf_params[] = {
+	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+	{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+	{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
+	{ "output-high", PIN_CONFIG_OUTPUT, 1, },
+	{ "output-low", PIN_CONFIG_OUTPUT, 0, },
+	{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 1 },
+	{ "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 1 },
+	{ "persist-enable", PIN_CONFIG_PERSIST_STATE, 1 },
+	{ "persist-disable", PIN_CONFIG_PERSIST_STATE, 0 },
+	{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
+	{ "active-high", PIN_CONFIG_POLARITY_STATE, 0 },
+	{ "active-low", PIN_CONFIG_POLARITY_STATE, 1 },
+	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+	{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
+	{ "event-clear", PIN_CONFIG_EVENT_CLEAR, 0},
+};
+
+static bool is_gpio_persist(struct udevice *dev, u8 bank)
+{
+	struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
+	u32 value, tmp;
+
+	u8 offset = bank + GPIOX_MODULE_RESET;
+	u32 mask = 1 << offset;
+
+	regmap_read(priv->gcr_regmap, NPCM7XX_GCR_RESSR, &value);
+	if (value == 0) {
+		regmap_read(priv->gcr_regmap, NPCM7XX_GCR_INTCR2, &tmp);
+		value = ~tmp;
+	}
+
+	dev_dbg(dev, "reboot reason: 0x%x\n", value);
+
+	if (value & CORST)
+		regmap_read(priv->rst_regmap, NPCM7XX_RST_CORSTC, &tmp);
+	else if (value & WD0RST)
+		regmap_read(priv->rst_regmap, NPCM7XX_RST_WD0RCR, &tmp);
+	else if (value & WD1RST)
+		regmap_read(priv->rst_regmap, NPCM7XX_RST_WD1RCR, &tmp);
+	else if (value & WD2RST)
+		regmap_read(priv->rst_regmap, NPCM7XX_RST_WD2RCR, &tmp);
+	else
+		return false;
+
+	return !((tmp & mask) >> offset);
+}
+
+static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum, int enable)
+{
+	struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
+	u32 num = GPIOX_MODULE_RESET + banknum;
+
+	dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", banknum, enable);
+
+	if (enable) {
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, 0);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, 0);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, 0);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, 0);
+	} else {
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
+		regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
+	}
+
+	return 0;
+}
+
+/* Set drive strength for a pin, if supported */
+static int npcm7xx_set_drive_strength(struct udevice *dev,
+				      unsigned int pin, int nval)
+{
+	struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
+	int bank = pin / NPCM7XX_GPIO_PER_BANK;
+	int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
+	void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank);
+	int v;
+
+	v = (pincfgs[pin].flag & DRIVE_STRENGTH_MASK);
+	if (!nval || !v)
+		return -ENOTSUPP;
+
+	if (DSLO(v) == nval) {
+		dev_dbg(dev,
+			"setting pin %d to low strength [%d]\n", pin, nval);
+		clrbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio));
+		return 0;
+	} else if (DSHI(v) == nval) {
+		dev_dbg(dev,
+			"setting pin %d to high strength [%d]\n", pin, nval);
+		setbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio));
+		return 0;
+	}
+
+	return -ENOTSUPP;
+}
+
+/* Set slew rate of pin (high/low) */
+static int npcm7xx_set_slew_rate(struct udevice *dev, unsigned int pin,
+				 int arg)
+{
+	struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
+	int bank = pin / NPCM7XX_GPIO_PER_BANK;
+	int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
+	void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank);
+
+	if (pincfgs[pin].flag & SLEW) {
+		switch (arg) {
+		case 0:
+			dev_dbg(dev,
+				"setting pin %d slew rate to low\n", pin);
+			clrbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio));
+			return 0;
+		case 1:
+			dev_dbg(dev,
+				"setting pin %d slew rate to high\n", pin);
+			setbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio));
+			return 0;
+		default:
+			return -ENOTSUPP;
+		}
+	}
+
+	/* LPC Slew rate in SRCNT register */
+	if (pincfgs[pin].flag & SLEWLPC) {
+		switch (arg) {
+		case 0:
+			dev_dbg(dev,
+				"setting LPC/ESPI(%d) slew rate to low\n", pin);
+			regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, 0);
+			return 0;
+		case 1:
+			dev_dbg(dev, "setting LPC/ESPI(%d) slew rate to high\n", pin);
+			regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, SRCNT_ESPI);
+			return 0;
+		default:
+			return -ENOTSUPP;
+		}
+	}
+
+	return -ENOTSUPP;
+}
+
+static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin,
+			       unsigned int param, unsigned int arg)
+{
+	struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
+	int err = 0;
+	int bank = pin / NPCM7XX_GPIO_PER_BANK;
+	int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
+	void __iomem *base = priv->gpio_base + (0x1000 * bank);
+
+	npcm7xx_setfunc(dev, (const int *)&pin, 1, fn_gpio);
+
+	/* To prevent unexpected IRQ trap at verctor 00 in linux kernel */
+	if (param == PIN_CONFIG_EVENT_CLEAR) {
+		dev_dbg(dev, "set pin %d event clear\n", pin);
+		clrbits_le32(base + NPCM7XX_GP_N_EVEN, BIT(gpio));
+		setbits_le32(base + NPCM7XX_GP_N_EVST, BIT(gpio));
+		return err;
+	}
+
+	// allow set persist state disable
+	if (param == PIN_CONFIG_PERSIST_STATE) {
+		npcm7xx_gpio_reset_persist(dev, bank, arg);
+		return err;
+	}
+
+	if (is_gpio_persist(dev, bank))
+		return err;
+
+	switch (param) {
+	case PIN_CONFIG_BIAS_DISABLE:
+		dev_dbg(dev, "set pin %d bias dsiable\n", pin);
+		clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
+		clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		dev_dbg(dev, "set pin %d bias pull down\n", pin);
+		clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
+		setbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		dev_dbg(dev, "set pin %d bias pull up\n", pin);
+		setbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
+		clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
+		break;
+	case PIN_CONFIG_INPUT_ENABLE:
+		dev_dbg(dev, "set pin %d input enable\n", pin);
+		setbits_le32(base + NPCM7XX_GP_N_OEC, BIT(gpio));
+		setbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
+		break;
+	case PIN_CONFIG_OUTPUT_ENABLE:
+		dev_dbg(dev, "set pin %d output enable\n", pin);
+		clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
+		setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
+	case PIN_CONFIG_OUTPUT:
+		dev_dbg(dev, "set pin %d output %d\n", pin, arg);
+		clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
+		setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
+		if (arg)
+			setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
+		else
+			clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
+		break;
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
+		dev_dbg(dev, "set pin %d push pull\n", pin);
+		clrbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio));
+		break;
+	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+		dev_dbg(dev, "set pin %d open drain\n", pin);
+		setbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio));
+		break;
+	case PIN_CONFIG_INPUT_DEBOUNCE:
+		dev_dbg(dev, "set pin %d input debounce\n", pin);
+		setbits_le32(base + NPCM7XX_GP_N_DBNC, BIT(gpio));
+		break;
+	case PIN_CONFIG_POLARITY_STATE:
+		dev_dbg(dev, "set pin %d active %d\n", pin, arg);
+		if (arg)
+			setbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio));
+		else
+			clrbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio));
+		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		dev_dbg(dev, "set pin %d driver strength %d\n", pin, arg);
+		err = npcm7xx_set_drive_strength(dev, pin, arg);
+		break;
+	case PIN_CONFIG_SLEW_RATE:
+		dev_dbg(dev, "set pin %d slew rate %d\n", pin, arg);
+		err = npcm7xx_set_slew_rate(dev, pin, arg);
+		break;
+	default:
+		err = -ENOTSUPP;
+	}
+	return err;
+}
+
+#endif
+
+static struct pinctrl_ops npcm7xx_pinctrl_ops = {
+	.set_state	= pinctrl_generic_set_state,
+	.get_pins_count = npcm7xx_get_pins_count,
+	.get_pin_name = npcm7xx_get_pin_name,
+	.get_groups_count = npcm7xx_get_groups_count,
+	.get_group_name = npcm7xx_get_group_name,
+	.get_functions_count = npcm7xx_get_functions_count,
+	.get_function_name = npcm7xx_get_function_name,
+	.pinmux_set = npcm7xx_pinmux_set,
+	.pinmux_group_set = npcm7xx_pinmux_set,
+#if CONFIG_IS_ENABLED(PINCONF)
+	.pinconf_num_params = ARRAY_SIZE(npcm7xx_conf_params),
+	.pinconf_params = npcm7xx_conf_params,
+	.pinconf_set = npcm7xx_pinconf_set,
+	.pinconf_group_set = npcm7xx_pinconf_set,
+#endif
+};
+
+static const struct udevice_id npcm7xx_pinctrl_ids[] = {
+	{ .compatible = "nuvoton,npcm750-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_npcm7xx) = {
+	.name = "nuvoton_npcm7xx_pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = npcm7xx_pinctrl_ids,
+	.priv_auto = sizeof(struct npcm7xx_pinctrl_priv),
+	.ops = &npcm7xx_pinctrl_ops,
+	.probe = npcm7xx_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index 7c5a02d..52d428f 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -467,6 +467,10 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
 				 pin);
 		break;
 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+		param = PM_PINCTRL_CONFIG_TRI_STATE;
+		arg = PM_PINCTRL_TRI_STATE_ENABLE;
+		ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
+		break;
 	case PIN_CONFIG_LOW_POWER_MODE:
 		/*
 		 * This cases are mentioned in dts but configurable
@@ -475,6 +479,11 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
 		 */
 		ret = 0;
 		break;
+	case PIN_CONFIG_OUTPUT_ENABLE:
+		param = PM_PINCTRL_CONFIG_TRI_STATE;
+		arg = PM_PINCTRL_TRI_STATE_DISABLE;
+		ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
+		break;
 	default:
 		dev_warn(dev, "unsupported configuration parameter '%u'\n",
 			 param);
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 56a20e8..990cd19 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -488,6 +488,7 @@ static const struct udevice_id stm32_pinctrl_ids[] = {
 	{ .compatible = "st,stm32h743-pinctrl" },
 	{ .compatible = "st,stm32mp157-pinctrl" },
 	{ .compatible = "st,stm32mp157-z-pinctrl" },
+	{ .compatible = "st,stm32mp135-pinctrl" },
 	{ }
 };
 
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 2c20dc7..bc47cf1 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -29,6 +29,7 @@ config POWER_LEGACY
 
 config SPL_POWER_LEGACY
 	bool "Legacy power support in SPL"
+	depends on SPL && !SPL_DM_PMIC
 	default y if POWER_LEGACY
 	help
 	  Note: This is a legacy option. Use SPL_DM_PMIC instead.
@@ -425,6 +426,10 @@ config POWER_MT6323
 	  This adds poweroff driver for mt6323
 	  this pmic is used on mt7623 / Bananapi R2
 
+config PALMAS_POWER
+	bool "Palmas power support"
+	depends on OMAP54XX
+
 config POWER_I2C
 	bool "I2C-based power control for legacy power"
 	depends on POWER_LEGACY
diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig
index fcd50e3..629acb0 100644
--- a/drivers/power/acpi_pmc/Kconfig
+++ b/drivers/power/acpi_pmc/Kconfig
@@ -8,6 +8,7 @@ config ACPI_PMC
 
 config SPL_ACPI_PMC
 	bool "Power Manager (x86 PMC) support in SPL"
+	depends on SPL
 	default y if ACPI_PMC
 	help
 	  Enable support for an x86-style power-management controller which
@@ -17,6 +18,7 @@ config SPL_ACPI_PMC
 
 config TPL_ACPI_PMC
 	bool "Power Manager (x86 PMC) support in TPL"
+	depends on TPL
 	default y if ACPI_PMC
 	help
 	  Enable support for an x86-style power-management controller which
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index 292fff0..a7f64d0 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -87,6 +87,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
 		.data = &j721s2_pd_platdata,
 	},
 #endif
+#ifdef CONFIG_SOC_K3_AM625
+	{
+		.family = "AM62X",
+		.data = &am62x_pd_platdata,
+	},
+#endif
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index d6cea8e..c519e06 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -55,7 +55,7 @@ config DM_REGULATOR_BD71837
 
 config SPL_DM_REGULATOR_BD71837
 	bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL"
-	depends on DM_REGULATOR_BD71837
+	depends on DM_REGULATOR_BD71837 && SPL
 	help
 	This config enables implementation of driver-model regulator uclass
 	features for regulators on ROHM BD71837 and BD71847 in SPL.
@@ -70,7 +70,7 @@ config DM_REGULATOR_PCA9450
 
 config SPL_DM_REGULATOR_PCA9450
 	bool "Enable Driver Model for NXP PCA9450 regulators in SPL"
-	depends on DM_REGULATOR_PCA9450
+	depends on DM_REGULATOR_PCA9450 && SPL
 	help
 	This config enables implementation of driver-model regulator uclass
 	features for regulators on ROHM PCA9450 in SPL.
@@ -115,7 +115,7 @@ config REGULATOR_PWM
 
 config SPL_REGULATOR_PWM
 	bool "Enable Driver for PWM regulators in SPL"
-	depends on REGULATOR_PWM
+	depends on REGULATOR_PWM && SPL
 	help
 	  This config enables implementation of driver-model regulator uclass
 	  features for PWM regulators in SPL.
@@ -163,7 +163,7 @@ config DM_REGULATOR_FIXED
 
 config SPL_DM_REGULATOR_FIXED
 	bool "Enable Driver Model for REGULATOR Fixed value in SPL"
-	depends on DM_REGULATOR_FIXED
+	depends on DM_REGULATOR_FIXED && SPL
 	select SPL_DM_REGULATOR_COMMON
 	---help---
 	This config enables implementation of driver-model regulator uclass
@@ -345,7 +345,7 @@ config SPL_DM_REGULATOR_STPMIC1
 
 config SPL_DM_REGULATOR_PALMAS
 	bool "Enable driver for PALMAS PMIC regulators"
-       depends on SPL_PMIC_PALMAS
+	depends on SPL_PMIC_PALMAS
 	help
 	This enables implementation of driver-model regulator uclass
 	features for REGULATOR PALMAS and the family of PALMAS PMICs.
@@ -353,7 +353,7 @@ config SPL_DM_REGULATOR_PALMAS
 
 config SPL_DM_REGULATOR_LP87565
 	bool "Enable driver for LP87565 PMIC regulators"
-       depends on SPL_PMIC_LP87565
+	depends on SPL_PMIC_LP87565
 	help
 	This enables implementation of driver-model regulator uclass
 	features for REGULATOR LP87565 and the family of LP87565 PMICs.
diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c
index 2966bdc..8011480 100644
--- a/drivers/power/regulator/scmi_regulator.c
+++ b/drivers/power/regulator/scmi_regulator.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2020-2021 Linaro Limited
+ * Copyright (C) 2020-2022 Linaro Limited
  */
 
 #define LOG_CATEGORY UCLASS_REGULATOR
@@ -25,9 +25,18 @@ struct scmi_regulator_platdata {
 	u32 domain_id;
 };
 
+/**
+ * struct scmi_regulator_priv - Private data for SCMI voltage regulator
+ * @channel: Reference to the SCMI channel to use
+ */
+struct scmi_regulator_priv {
+	struct scmi_channel *channel;
+};
+
 static int scmi_voltd_set_enable(struct udevice *dev, bool enable)
 {
 	struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
+	struct scmi_regulator_priv *priv = dev_get_priv(dev);
 	struct scmi_voltd_config_set_in in = {
 		.domain_id = pdata->domain_id,
 		.config = enable ? SCMI_VOLTD_CONFIG_ON : SCMI_VOLTD_CONFIG_OFF,
@@ -38,20 +47,17 @@ static int scmi_voltd_set_enable(struct udevice *dev, bool enable)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(dev, &msg);
-	if (ret)
-		return ret;
-
-	ret = scmi_to_linux_errno(out.status);
+	ret = devm_scmi_process_msg(dev, priv->channel, &msg);
 	if (ret)
 		return ret;
 
-	return ret;
+	return scmi_to_linux_errno(out.status);
 }
 
 static int scmi_voltd_get_enable(struct udevice *dev)
 {
 	struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
+	struct scmi_regulator_priv *priv = dev_get_priv(dev);
 	struct scmi_voltd_config_get_in in = {
 		.domain_id = pdata->domain_id,
 	};
@@ -61,7 +67,7 @@ static int scmi_voltd_get_enable(struct udevice *dev)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(dev, &msg);
+	ret = devm_scmi_process_msg(dev, priv->channel, &msg);
 	if (ret < 0)
 		return ret;
 
@@ -74,6 +80,7 @@ static int scmi_voltd_get_enable(struct udevice *dev)
 
 static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV)
 {
+	struct scmi_regulator_priv *priv = dev_get_priv(dev);
 	struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
 	struct scmi_voltd_level_set_in in = {
 		.domain_id = pdata->domain_id,
@@ -85,7 +92,7 @@ static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(dev, &msg);
+	ret = devm_scmi_process_msg(dev, priv->channel, &msg);
 	if (ret < 0)
 		return ret;
 
@@ -94,6 +101,7 @@ static int scmi_voltd_set_voltage_level(struct udevice *dev, int uV)
 
 static int scmi_voltd_get_voltage_level(struct udevice *dev)
 {
+	struct scmi_regulator_priv *priv = dev_get_priv(dev);
 	struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
 	struct scmi_voltd_level_get_in in = {
 		.domain_id = pdata->domain_id,
@@ -104,7 +112,7 @@ static int scmi_voltd_get_voltage_level(struct udevice *dev)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(dev, &msg);
+	ret = devm_scmi_process_msg(dev, priv->channel, &msg);
 	if (ret < 0)
 		return ret;
 
@@ -132,6 +140,7 @@ static int scmi_regulator_of_to_plat(struct udevice *dev)
 static int scmi_regulator_probe(struct udevice *dev)
 {
 	struct scmi_regulator_platdata *pdata = dev_get_plat(dev);
+	struct scmi_regulator_priv *priv = dev_get_priv(dev);
 	struct scmi_voltd_attr_in in = { 0 };
 	struct scmi_voltd_attr_out out = { 0 };
 	struct scmi_msg scmi_msg = {
@@ -144,10 +153,14 @@ static int scmi_regulator_probe(struct udevice *dev)
 	};
 	int ret;
 
+	ret = devm_scmi_of_get_channel(dev->parent, &priv->channel);
+	if (ret)
+		return ret;
+
 	/* Check voltage domain is known from SCMI server */
 	in.domain_id = pdata->domain_id;
 
-	ret = devm_scmi_process_msg(dev, &scmi_msg);
+	ret = devm_scmi_process_msg(dev, priv->channel, &scmi_msg);
 	if (ret) {
 		dev_err(dev, "Failed to query voltage domain %u: %d\n",
 			pdata->domain_id, ret);
@@ -171,6 +184,7 @@ U_BOOT_DRIVER(scmi_regulator) = {
 	.probe = scmi_regulator_probe,
 	.of_to_plat = scmi_regulator_of_to_plat,
 	.plat_auto = sizeof(struct scmi_regulator_platdata),
+	.priv_auto = sizeof(struct scmi_regulator_priv *),
 };
 
 static int scmi_regulator_bind(struct udevice *dev)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index cb54e67..8fd5a2e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -84,6 +84,11 @@ config PWM_SANDBOX
 	  useful. The PWM can be enabled but is not connected to any outputs
 	  so this is not very useful.
 
+config PWM_S5P
+	bool "Enable non-DM support for S5P PWM"
+	depends on (S5P || ARCH_NEXELL)
+	default y
+
 config PWM_SIFIVE
 	bool "Enable support for SiFive PWM"
 	depends on DM_PWM
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 709c916..7c34618 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -19,7 +19,7 @@ config SPL_RAM
 
 config TPL_RAM
 	bool "Enable RAM support in TPL"
-	depends on RAM
+	depends on RAM && TPL
 	help
 	  The RAM subsystem adds a small amount of overhead to the image.
 	  If this is acceptable and you have a need to use RAM drivers in
@@ -64,6 +64,7 @@ choice
 
 	default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
 	default K3_AM64_DDRSS if SOC_K3_AM642
+	default K3_AM64_DDRSS if SOC_K3_AM625
 
 config K3_J721E_DDRSS
 	bool "Enable J721E DDRSS support"
diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c
index 49b1262..a6c19af 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ram.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ram.c
@@ -230,29 +230,29 @@ static u8 get_nb_col(struct stm32mp1_ddrctl *ctl, u8 data_bus_width)
 
 	reg = readl(&ctl->addrmap3);
 	/* addrmap3.addrmap_col_b6 */
-	val = (reg & GENMASK(3, 0)) >> 0;
+	val = (reg & GENMASK(4, 0)) >> 0;
 	if (val <= 7)
 		bits++;
 	/* addrmap3.addrmap_col_b7 */
-	val = (reg & GENMASK(11, 8)) >> 8;
+	val = (reg & GENMASK(12, 8)) >> 8;
 	if (val <= 7)
 		bits++;
 	/* addrmap3.addrmap_col_b8 */
-	val = (reg & GENMASK(19, 16)) >> 16;
+	val = (reg & GENMASK(20, 16)) >> 16;
 	if (val <= 7)
 		bits++;
 	/* addrmap3.addrmap_col_b9 */
-	val = (reg & GENMASK(27, 24)) >> 24;
+	val = (reg & GENMASK(28, 24)) >> 24;
 	if (val <= 7)
 		bits++;
 
 	reg = readl(&ctl->addrmap4);
 	/* addrmap4.addrmap_col_b10 */
-	val = (reg & GENMASK(3, 0)) >> 0;
+	val = (reg & GENMASK(4, 0)) >> 0;
 	if (val <= 7)
 		bits++;
 	/* addrmap4.addrmap_col_b11 */
-	val = (reg & GENMASK(11, 8)) >> 8;
+	val = (reg & GENMASK(12, 8)) >> 8;
 	if (val <= 7)
 		bits++;
 
@@ -296,21 +296,24 @@ static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
 	reg = readl(&ctl->addrmap6);
 	/* addrmap6.addrmap_row_b12 */
 	val = (reg & GENMASK(3, 0)) >> 0;
-	if (val <= 7)
+	if (val <= 11)
 		bits++;
 	/* addrmap6.addrmap_row_b13 */
 	val = (reg & GENMASK(11, 8)) >> 8;
-	if (val <= 7)
+	if (val <= 11)
 		bits++;
 	/* addrmap6.addrmap_row_b14 */
 	val = (reg & GENMASK(19, 16)) >> 16;
-	if (val <= 7)
+	if (val <= 11)
 		bits++;
 	/* addrmap6.addrmap_row_b15 */
 	val = (reg & GENMASK(27, 24)) >> 24;
-	if (val <= 7)
+	if (val <= 11)
 		bits++;
 
+	if (reg & BIT(31))
+		printf("warning: LPDDR3_6GB_12GB is not supported\n");
+
 	return bits;
 }
 
@@ -392,12 +395,17 @@ static struct ram_ops stm32mp1_ddr_ops = {
 	.get_info = stm32mp1_ddr_get_info,
 };
 
+static const struct stm32mp1_ddr_cfg stm32mp13x_ddr_cfg = {
+	.nb_bytes = 2,
+};
+
 static const struct stm32mp1_ddr_cfg stm32mp15x_ddr_cfg = {
 	.nb_bytes = 4,
 };
 
 static const struct udevice_id stm32mp1_ddr_ids[] = {
 	{ .compatible = "st,stm32mp1-ddr", .data = (ulong)&stm32mp15x_ddr_cfg},
+	{ .compatible = "st,stm32mp13-ddr", .data = (ulong)&stm32mp13x_ddr_cfg},
 	{ }
 };
 
diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c
index 0a1dd23..d9cecf3 100644
--- a/drivers/reset/reset-ast2500.c
+++ b/drivers/reset/reset-ast2500.c
@@ -48,6 +48,24 @@ static int ast2500_reset_deassert(struct reset_ctl *reset_ctl)
 	return 0;
 }
 
+static int ast2500_reset_status(struct reset_ctl *reset_ctl)
+{
+	struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2500_scu *scu = priv->scu;
+	int status;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		status = BIT(reset_ctl->id) & readl(&scu->sysreset_ctrl1);
+	else
+		status = BIT(reset_ctl->id - 32) & readl(&scu->sysreset_ctrl2);
+
+	return !!status;
+}
+
+
+
 static int ast2500_reset_probe(struct udevice *dev)
 {
 	int rc;
@@ -79,6 +97,7 @@ static const struct udevice_id ast2500_reset_ids[] = {
 struct reset_ops ast2500_reset_ops = {
 	.rst_assert = ast2500_reset_assert,
 	.rst_deassert = ast2500_reset_deassert,
+	.rst_status = ast2500_reset_status,
 };
 
 U_BOOT_DRIVER(ast2500_reset) = {
diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c
index 985235a..1732a45 100644
--- a/drivers/reset/reset-ast2600.c
+++ b/drivers/reset/reset-ast2600.c
@@ -47,6 +47,22 @@ static int ast2600_reset_deassert(struct reset_ctl *reset_ctl)
 	return 0;
 }
 
+static int ast2600_reset_status(struct reset_ctl *reset_ctl)
+{
+	struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ast2600_scu *scu = priv->scu;
+	int status;
+
+	debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id);
+
+	if (reset_ctl->id < 32)
+		status = BIT(reset_ctl->id) & readl(&scu->modrst_ctrl1);
+	else
+		status = BIT(reset_ctl->id - 32) & readl(&scu->modrst_ctrl2);
+
+	return !!status;
+}
+
 static int ast2600_reset_probe(struct udevice *dev)
 {
 	int rc;
@@ -78,6 +94,7 @@ static const struct udevice_id ast2600_reset_ids[] = {
 struct reset_ops ast2600_reset_ops = {
 	.rst_assert = ast2600_reset_assert,
 	.rst_deassert = ast2600_reset_deassert,
+	.rst_status = ast2600_reset_status,
 };
 
 U_BOOT_DRIVER(ast2600_reset) = {
diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c
index 81d195a..1225561 100644
--- a/drivers/reset/reset-scmi.c
+++ b/drivers/reset/reset-scmi.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2019-2020 Linaro Limited
+ * Copyright (C) 2019-2022 Linaro Limited
  */
 
 #define LOG_CATEGORY UCLASS_RESET
@@ -13,8 +13,17 @@
 #include <scmi_protocols.h>
 #include <asm/types.h>
 
+/**
+ * struct scmi_reset_priv - Private data for SCMI reset controller
+ * @channel: Reference to the SCMI channel to use
+ */
+struct scmi_reset_priv {
+	struct scmi_channel *channel;
+};
+
 static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert)
 {
+	struct scmi_reset_priv *priv = dev_get_priv(rst->dev);
 	struct scmi_rd_reset_in in = {
 		.domain_id = rst->id,
 		.flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : 0,
@@ -26,7 +35,7 @@ static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert)
 					  in, out);
 	int ret;
 
-	ret = devm_scmi_process_msg(rst->dev, &msg);
+	ret = devm_scmi_process_msg(rst->dev, priv->channel, &msg);
 	if (ret)
 		return ret;
 
@@ -45,6 +54,7 @@ static int scmi_reset_deassert(struct reset_ctl *rst)
 
 static int scmi_reset_request(struct reset_ctl *rst)
 {
+	struct scmi_reset_priv *priv = dev_get_priv(rst->dev);
 	struct scmi_rd_attr_in in = {
 		.domain_id = rst->id,
 	};
@@ -58,7 +68,7 @@ static int scmi_reset_request(struct reset_ctl *rst)
 	 * We don't really care about the attribute, just check
 	 * the reset domain exists.
 	 */
-	ret = devm_scmi_process_msg(rst->dev, &msg);
+	ret = devm_scmi_process_msg(rst->dev, priv->channel, &msg);
 	if (ret)
 		return ret;
 
@@ -71,8 +81,17 @@ static const struct reset_ops scmi_reset_domain_ops = {
 	.rst_deassert	= scmi_reset_deassert,
 };
 
+static int scmi_reset_probe(struct udevice *dev)
+{
+	struct scmi_reset_priv *priv = dev_get_priv(dev);
+
+	return devm_scmi_of_get_channel(dev, &priv->channel);
+}
+
 U_BOOT_DRIVER(scmi_reset_domain) = {
 	.name = "scmi_reset_domain",
 	.id = UCLASS_RESET,
 	.ops = &scmi_reset_domain_ops,
+	.probe = scmi_reset_probe,
+	.priv_auto = sizeof(struct scmi_reset_priv *),
 };
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index c10f7d3..21a9ff0 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -31,6 +31,13 @@ config RNG_MSM
 	  This driver provides support for the Random Number
 	  Generator hardware found on Qualcomm SoCs.
 
+config RNG_NPCM
+	bool "Nuvoton NPCM SoCs Random Number Generator support"
+	depends on DM_RNG
+	help
+	  Enable random number generator on NPCM SoCs.
+	  This unit can provide 750 to 1000 random bits per second
+
 config RNG_OPTEE
 	bool "OP-TEE based Random Number Generator support"
 	depends on DM_RNG && OPTEE
@@ -58,4 +65,13 @@ config RNG_IPROC200
 	depends on DM_RNG
 	help
 	  Enable random number generator for RPI4.
+
+config RNG_SMCCC_TRNG
+	bool "Arm SMCCC TRNG interface"
+	depends on DM_RNG && ARM_PSCI_FW
+	default y if ARM_SMCCC_FEATURES
+	help
+	  Enable random number generator for platforms that support Arm
+	  SMCCC TRNG interface.
+
 endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 435b3b9..2494717 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -7,7 +7,9 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o
 obj-$(CONFIG_RNG_MESON) += meson-rng.o
 obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
 obj-$(CONFIG_RNG_MSM) += msm_rng.o
+obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
 obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
 obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
 obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
 obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
+obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
diff --git a/drivers/rng/npcm_rng.c b/drivers/rng/npcm_rng.c
new file mode 100644
index 0000000..70c1c03
--- /dev/null
+++ b/drivers/rng/npcm_rng.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <rng.h>
+#include <uboot_aes.h>
+#include <asm/io.h>
+
+#define RNGCS_RNGE              BIT(0)
+#define RNGCS_DVALID            BIT(1)
+#define RNGCS_CLKP(range)       ((0x0f & (range)) << 2)
+#define RNGMODE_M1ROSEL_VAL     (0x02) /* Ring Oscillator Select for Method I */
+
+enum {
+	RNG_CLKP_80_100_MHZ = 0x00, /*default */
+	RNG_CLKP_60_80_MHZ  = 0x01,
+	RNG_CLKP_50_60_MHZ  = 0x02,
+	RNG_CLKP_40_50_MHZ  = 0x03,
+	RNG_CLKP_30_40_MHZ  = 0x04,
+	RNG_CLKP_25_30_MHZ  = 0x05,
+	RNG_CLKP_20_25_MHZ  = 0x06,
+	RNG_CLKP_5_20_MHZ   = 0x07,
+	RNG_CLKP_2_15_MHZ   = 0x08,
+	RNG_CLKP_9_12_MHZ   = 0x09,
+	RNG_CLKP_7_9_MHZ    = 0x0A,
+	RNG_CLKP_6_7_MHZ    = 0x0B,
+	RNG_CLKP_5_6_MHZ    = 0x0C,
+	RNG_CLKP_4_5_MHZ    = 0x0D,
+	RNG_CLKP_3_4_MHZ    = 0x0E,
+	RNG_NUM_OF_CLKP
+};
+
+struct npcm_rng_regs {
+	unsigned int rngcs;
+	unsigned int rngd;
+	unsigned int rngmode;
+};
+
+struct npcm_rng_priv {
+	struct npcm_rng_regs *regs;
+};
+
+static struct npcm_rng_priv *rng_priv;
+
+void npcm_rng_init(void)
+{
+	struct npcm_rng_regs *regs = rng_priv->regs;
+	int init;
+
+	/* check if rng enabled */
+	init = readb(&regs->rngcs);
+	if ((init & RNGCS_RNGE) == 0) {
+		/* init rng */
+		writeb(RNGCS_CLKP(RNG_CLKP_20_25_MHZ) | RNGCS_RNGE, &regs->rngcs);
+		writeb(RNGMODE_M1ROSEL_VAL, &regs->rngmode);
+	}
+}
+
+void npcm_rng_disable(void)
+{
+	struct npcm_rng_regs *regs = rng_priv->regs;
+
+	/* disable rng */
+	writeb(0, &regs->rngcs);
+	writeb(0, &regs->rngmode);
+}
+
+void srand(unsigned int seed)
+{
+	/* no need to seed for now */
+}
+
+int npcm_rng_read(struct udevice *dev, void *data, size_t max)
+{
+	struct npcm_rng_regs *regs = rng_priv->regs;
+	int  i;
+	int ret_val = 0;
+	char *buf = data;
+
+	npcm_rng_init();
+
+	printf("NPCM HW RNG\n");
+	/* Wait for RNG done (max bytes) */
+	for (i = 0; i < max; i++) {
+		 /* wait until DVALID is set */
+		while ((readb(&regs->rngcs) & RNGCS_DVALID) == 0)
+			;
+		buf[i] = ((unsigned int)readb(&regs->rngd) & 0x000000FF);
+	}
+
+	return ret_val;
+}
+
+unsigned int rand_r(unsigned int *seedp)
+{
+	struct npcm_rng_regs *regs = rng_priv->regs;
+	int  i;
+	unsigned int ret_val = 0;
+
+	npcm_rng_init();
+
+	/* Wait for RNG done (4 bytes) */
+	for (i = 0; i < 4 ; i++) {
+		/* wait until DVALID is set */
+		while ((readb(&regs->rngcs) & RNGCS_DVALID) == 0)
+			;
+		ret_val |= (((unsigned int)readb(&regs->rngd) & 0x000000FF) << (i * 8));
+	}
+
+	return ret_val;
+}
+
+unsigned int rand(void)
+{
+	return rand_r(NULL);
+}
+
+static int npcm_rng_bind(struct udevice *dev)
+{
+	rng_priv = calloc(1, sizeof(struct npcm_rng_priv));
+	if (!rng_priv)
+		return -ENOMEM;
+
+	rng_priv->regs = dev_remap_addr_index(dev, 0);
+	if (!rng_priv->regs) {
+		printf("Cannot find rng reg address, binding failed\n");
+		return -EINVAL;
+	}
+
+	printf("RNG: NPCM RNG module bind OK\n");
+
+	return 0;
+}
+
+static const struct udevice_id npcm_rng_ids[] = {
+	{ .compatible = "nuvoton,npcm845-rng" },
+	{ .compatible = "nuvoton,npcm750-rng" },
+	{ }
+};
+
+static const struct dm_rng_ops npcm_rng_ops = {
+	.read = npcm_rng_read,
+};
+
+U_BOOT_DRIVER(npcm_rng) = {
+	.name = "npcm_rng",
+	.id = UCLASS_RNG,
+	.ops = &npcm_rng_ops,
+	.of_match = npcm_rng_ids,
+	.priv_auto = sizeof(struct npcm_rng_priv),
+	.bind = npcm_rng_bind,
+};
diff --git a/drivers/rng/smccc_trng.c b/drivers/rng/smccc_trng.c
new file mode 100644
index 0000000..3a4bb33
--- /dev/null
+++ b/drivers/rng/smccc_trng.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#define LOG_CATEGORY UCLASS_RNG
+
+#include <common.h>
+#include <dm.h>
+#include <linker_lists.h>
+#include <log.h>
+#include <rng.h>
+#include <dm/device_compat.h>
+#include <linux/arm-smccc.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/psci.h>
+
+#define DRIVER_NAME	"smccc-trng"
+
+/**
+ * Arm SMCCC TRNG firmware interface specification:
+ * https://developer.arm.com/documentation/den0098/latest/
+ */
+#define ARM_SMCCC_TRNG_VERSION		0x84000050
+#define ARM_SMCCC_TRNG_FEATURES		0x84000051
+#define ARM_SMCCC_TRNG_GET_UUID		0x84000052
+#define ARM_SMCCC_TRNG_RND_32		0x84000053
+#define ARM_SMCCC_TRNG_RND_64		0xC4000053
+
+#define ARM_SMCCC_RET_TRNG_SUCCESS		((ulong)0)
+#define ARM_SMCCC_RET_TRNG_NOT_SUPPORTED	((ulong)-1)
+#define ARM_SMCCC_RET_TRNG_INVALID_PARAMETER	((ulong)-2)
+#define ARM_SMCCC_RET_TRNG_NO_ENTROPY		((ulong)-3)
+
+#define TRNG_MAJOR_MASK		GENMASK(30, 16)
+#define TRNG_MAJOR_SHIFT	16
+#define TRNG_MINOR_MASK		GENMASK(15, 0)
+#define TRNG_MINOR_SHIFT	0
+
+#define TRNG_MAX_RND_64		(192 / 8)
+#define TRNG_MAX_RND_32		(96 / 8)
+
+/**
+ * struct smccc_trng_priv - Private data for SMCCC TRNG support
+ *
+ * @smc64 - True if TRNG_RND_64 is supported, false if TRNG_RND_32 is supported
+ */
+struct smccc_trng_priv {
+	bool smc64;
+};
+
+/*
+ * Copy random bytes from ulong SMCCC output register to target buffer
+ * Defines 2 function flavors for whether ARM_SMCCC_TRNG_RND_32 or
+ * ARM_SMCCC_TRNG_RND_64 was used to invoke the service.
+ */
+static size_t smc32_copy_sample(u8 **ptr, size_t size, ulong *rnd)
+{
+	size_t len = min(size, sizeof(u32));
+	u32 sample = *rnd;
+
+	memcpy(*ptr, &sample, len);
+	*ptr += len;
+
+	return size - len;
+}
+
+static size_t smc64_copy_sample(u8 **ptr, size_t size, ulong *rnd)
+{
+	size_t len = min(size, sizeof(u64));
+	u64 sample = *rnd;
+
+	memcpy(*ptr, &sample, len);
+	*ptr += len;
+
+	return size - len;
+}
+
+static int smccc_trng_read(struct udevice *dev, void *data, size_t len)
+{
+	struct psci_plat_data *smccc = dev_get_parent_plat(dev);
+	struct smccc_trng_priv *priv = dev_get_priv(dev);
+	struct arm_smccc_res res;
+	u32 func_id;
+	u8 *ptr = data;
+	size_t rem = len;
+	size_t max_sz;
+	size_t (*copy_sample)(u8 **ptr, size_t size, ulong *rnd);
+
+	if (priv->smc64) {
+		copy_sample = smc64_copy_sample;
+		func_id = ARM_SMCCC_TRNG_RND_64;
+		max_sz = TRNG_MAX_RND_64;
+	} else {
+		copy_sample = smc32_copy_sample;
+		func_id = ARM_SMCCC_TRNG_RND_32;
+		max_sz = TRNG_MAX_RND_32;
+	}
+
+	while (rem) {
+		size_t sz = min(rem, max_sz);
+
+		smccc->invoke_fn(func_id, sz * 8, 0, 0, 0, 0, 0, 0, &res);
+
+		switch (res.a0) {
+		case ARM_SMCCC_RET_TRNG_SUCCESS:
+			break;
+		case ARM_SMCCC_RET_TRNG_NO_ENTROPY:
+			continue;
+		default:
+			return -EIO;
+		}
+
+		rem -= sz;
+
+		sz = copy_sample(&ptr, sz, &res.a3);
+		if (sz)
+			sz = copy_sample(&ptr, sz, &res.a2);
+		if (sz)
+			sz = copy_sample(&ptr, sz, &res.a1);
+	}
+
+	return 0;
+}
+
+static const struct dm_rng_ops smccc_trng_ops = {
+	.read = smccc_trng_read,
+};
+
+static bool smccc_trng_is_supported(void (*invoke_fn)(unsigned long a0, unsigned long a1,
+						      unsigned long a2, unsigned long a3,
+						      unsigned long a4, unsigned long a5,
+						      unsigned long a6, unsigned long a7,
+						      struct arm_smccc_res *res))
+{
+	struct arm_smccc_res res;
+
+	(*invoke_fn)(ARM_SMCCC_ARCH_FEATURES, ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, &res);
+	if (res.a0 == ARM_SMCCC_RET_NOT_SUPPORTED)
+		return false;
+
+	(*invoke_fn)(ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+	if (res.a0 & BIT(31))
+		return false;
+
+	/* Test 64bit interface and fallback to 32bit interface */
+	invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_64,
+		  0, 0, 0, 0, 0, 0, &res);
+
+	if (res.a0 == ARM_SMCCC_RET_TRNG_NOT_SUPPORTED)
+		invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_32,
+			  0, 0, 0, 0, 0, 0, &res);
+
+	return res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS;
+}
+
+ARM_SMCCC_FEATURE_DRIVER(smccc_trng) = {
+	.driver_name = DRIVER_NAME,
+	.is_supported = smccc_trng_is_supported,
+};
+
+static int smccc_trng_probe(struct udevice *dev)
+{
+	struct psci_plat_data *smccc = dev_get_parent_plat(dev);
+	struct smccc_trng_priv *priv = dev_get_priv(dev);
+	struct arm_smccc_res res;
+
+	if (!(smccc_trng_is_supported(smccc->invoke_fn)))
+		return -ENODEV;
+
+	/* At least one of 64bit and 32bit interfaces is available */
+	smccc->invoke_fn(ARM_SMCCC_TRNG_FEATURES, ARM_SMCCC_TRNG_RND_64,
+			 0, 0, 0, 0, 0, 0, &res);
+	priv->smc64 = (res.a0 == ARM_SMCCC_RET_TRNG_SUCCESS);
+
+#ifdef DEBUG
+	smccc->invoke_fn(ARM_SMCCC_TRNG_GET_UUID, 0, 0, 0, 0, 0, 0, 0, &res);
+	if (res.a0 != ARM_SMCCC_RET_TRNG_NOT_SUPPORTED) {
+		unsigned long uuid_a0 = res.a0;
+		unsigned long uuid_a1 = res.a1;
+		unsigned long uuid_a2 = res.a2;
+		unsigned long uuid_a3 = res.a3;
+		unsigned long major, minor;
+
+		smccc->invoke_fn(ARM_SMCCC_TRNG_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+		major = (res.a0 & TRNG_MAJOR_MASK) >> TRNG_MAJOR_SHIFT;
+		minor = (res.a0 & TRNG_MINOR_MASK) >> TRNG_MINOR_SHIFT;
+
+		dev_dbg(dev, "Version %lu.%lu, UUID %08lx-%04lx-%04lx-%04lx-%04lx%08lx\n",
+			major, minor, uuid_a0, uuid_a1 >> 16, uuid_a1 & GENMASK(16, 0),
+			uuid_a2 >> 16, uuid_a2 & GENMASK(16, 0), uuid_a3);
+	} else {
+		dev_warn(dev, "Can't get TRNG UUID\n");
+	}
+#endif
+
+	return 0;
+}
+
+U_BOOT_DRIVER(smccc_trng) = {
+	.name = DRIVER_NAME,
+	.id = UCLASS_RNG,
+	.ops = &smccc_trng_ops,
+	.probe = smccc_trng_probe,
+	.priv_auto = sizeof(struct smccc_trng_priv),
+};
diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c
index ba418c2..c307d60 100644
--- a/drivers/rtc/i2c_rtc_emul.c
+++ b/drivers/rtc/i2c_rtc_emul.c
@@ -203,6 +203,15 @@ static int sandbox_i2c_rtc_bind(struct udevice *dev)
 	return 0;
 }
 
+static int sandbox_i2c_rtc_probe(struct udevice *dev)
+{
+	const u8 mac[] = { 0x02, 0x00, 0x11, 0x22, 0x33, 0x48 };
+	struct sandbox_i2c_rtc_plat_data *plat = dev_get_plat(dev);
+
+	memcpy(&plat->reg[0x40], mac, sizeof(mac));
+	return 0;
+}
+
 static const struct udevice_id sandbox_i2c_rtc_ids[] = {
 	{ .compatible = "sandbox,i2c-rtc-emul" },
 	{ }
@@ -213,6 +222,7 @@ U_BOOT_DRIVER(sandbox_i2c_rtc_emul) = {
 	.id		= UCLASS_I2C_EMUL,
 	.of_match	= sandbox_i2c_rtc_ids,
 	.bind		= sandbox_i2c_rtc_bind,
+	.probe		= sandbox_i2c_rtc_probe,
 	.priv_auto	= sizeof(struct sandbox_i2c_rtc),
 	.plat_auto	= sizeof(struct sandbox_i2c_rtc_plat_data),
 	.ops		= &sandbox_i2c_rtc_emul_ops,
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 45c284a..de02e08 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -476,6 +476,8 @@ config DEBUG_UART_BASE
 	depends on DEBUG_UART
 	default 0 if DEBUG_SBI_CONSOLE
 	default 0 if DEBUG_UART_SANDBOX
+	default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
+	default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
 	help
 	  This is the base address of your UART for memory-mapped UARTs.
 
@@ -502,6 +504,8 @@ config DEBUG_UART_CLOCK
 	default 0 if DEBUG_SBI_CONSOLE
 	default 0 if DEBUG_UART_SANDBOX
 	default 0 if DEBUG_MVEBU_A3700_UART
+	default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP
+	default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ
 	help
 	  The UART input clock determines the speed of the internal UART
 	  circuitry. The baud rate is derived from this by dividing the input
@@ -936,12 +940,6 @@ config OWL_SERIAL
 	  serial port, say Y to this option. If unsure, say N.
 	  Single baudrate is supported in current implementation (115200).
 
-config PXA_SERIAL
-	bool "PXA serial port support"
-	help
-	  If you have a machine based on a Marvell XScale PXA2xx CPU you
-	  can enable its onboard serial ports by enabling this option.
-
 config HTIF_CONSOLE
 	bool "RISC-V HTIF console support"
 	depends on DM_SERIAL && 64BIT
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 51de06a..eb7b8f2 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -43,7 +43,6 @@ obj-$(CONFIG_MCFUART) += serial_mcf.o
 obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
-obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
 obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
 obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c
index 4435fcf..9e39da7 100644
--- a/drivers/serial/altera_jtag_uart.c
+++ b/drivers/serial/altera_jtag_uart.c
@@ -134,7 +134,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct altera_jtaguart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	struct altera_jtaguart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (1) {
 		u32 st = readl(&regs->control);
diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c
index b18be6e..3592048 100644
--- a/drivers/serial/altera_uart.c
+++ b/drivers/serial/altera_uart.c
@@ -123,7 +123,7 @@ U_BOOT_DRIVER(altera_uart) = {
 
 static inline void _debug_uart_init(void)
 {
-	struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
 	u32 div;
 
 	div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;
@@ -132,7 +132,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (1) {
 		u32 st = readl(&regs->status);
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index bd14f3e..1fb9ee5 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -319,14 +319,14 @@ U_BOOT_DRIVER(serial_atmel) = {
 #ifdef CONFIG_DEBUG_UART_ATMEL
 static inline void _debug_uart_init(void)
 {
-	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
+	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	_atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 }
 
 static inline void _debug_uart_putc(int ch)
 {
-	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
+	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
 		;
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 78bfe62..47bad6f 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -328,6 +328,10 @@ static inline void _debug_uart_init(void)
 	struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
 	int baud_divisor;
 
+	/* Wait until tx buffer is empty */
+	while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT))
+		;
+
 	/*
 	 * We copy the code from above because it is already horribly messy.
 	 * Trying to refactor to nicely remove the duplication doesn't seem
diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index e726e19..13b5492 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -114,7 +114,7 @@ static ssize_t sandbox_serial_puts(struct udevice *dev, const char *s,
 	struct sandbox_serial_priv *priv = dev_get_priv(dev);
 	ssize_t ret;
 
-	if (s[len - 1] == '\n')
+	if (len && s[len - 1] == '\n')
 		priv->start_of_line = true;
 
 	if (sandbox_serial_enabled) {
diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c
index da06bef..4f91634 100644
--- a/drivers/serial/serial_ar933x.c
+++ b/drivers/serial/serial_ar933x.c
@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_ar933x) = {
 
 static inline void _debug_uart_init(void)
 {
-	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
 	u32 val, scale, step;
 
 	/*
@@ -227,7 +227,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int c)
 {
-	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
 	u32 data;
 
 	do {
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
index 8f3e4dd..b2d95bd 100644
--- a/drivers/serial/serial_arc.c
+++ b/drivers/serial/serial_arc.c
@@ -137,7 +137,7 @@ U_BOOT_DRIVER(serial_arc) = {
 
 static inline void _debug_uart_init(void)
 {
-	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE);
 	int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1;
 
 	writeb(arc_console_baud & 0xff, &regs->baudl);
@@ -146,7 +146,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int c)
 {
-	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+	struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (!(readb(&regs->status) & UART_TXEMPTY))
 		;
diff --git a/drivers/serial/serial_bcm6345.c b/drivers/serial/serial_bcm6345.c
index f08e91f..2359656 100644
--- a/drivers/serial/serial_bcm6345.c
+++ b/drivers/serial/serial_bcm6345.c
@@ -269,7 +269,7 @@ U_BOOT_DRIVER(bcm6345_serial) = {
 #ifdef CONFIG_DEBUG_UART_BCM6345
 static inline void _debug_uart_init(void)
 {
-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 }
@@ -285,7 +285,7 @@ static inline void wait_xfered(void __iomem *base)
 
 static inline void _debug_uart_putc(int ch)
 {
-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	wait_xfered(base);
 	writel(ch, base + UART_FIFO_REG);
diff --git a/drivers/serial/serial_linflexuart.c b/drivers/serial/serial_linflexuart.c
index 876a4ba..b449e55 100644
--- a/drivers/serial/serial_linflexuart.c
+++ b/drivers/serial/serial_linflexuart.c
@@ -201,14 +201,14 @@ U_BOOT_DRIVER(serial_linflex) = {
 
 static inline void _debug_uart_init(void)
 {
-	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	linflex_serial_init_internal(base);
 }
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE;
+	struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	/* XXX: Is this OK? Should this use the non-DM version? */
 	_linflex_serial_putc(base, ch);
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
index d69ec22..c5ed3ed 100644
--- a/drivers/serial/serial_meson.c
+++ b/drivers/serial/serial_meson.c
@@ -182,7 +182,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
+	struct meson_uart *regs = (struct meson_uart *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (readl(&regs->status) & AML_UART_TX_FULL)
 		;
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3e255a9..3943ca4 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -569,7 +569,7 @@ U_BOOT_DRIVER(serial_msm_geni) = {
 #ifdef CONFIG_DEBUG_UART_MSM_GENI
 
 static struct msm_serial_data init_serial_data = {
-	.base = CONFIG_DEBUG_UART_BASE
+	.base = CONFIG_VAL(DEBUG_UART_BASE)
 };
 
 /* Serial dumb device, to reuse driver code */
@@ -587,7 +587,7 @@ static struct udevice init_dev = {
 
 static inline void _debug_uart_init(void)
 {
-	phys_addr_t base = CONFIG_DEBUG_UART_BASE;
+	phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
 
 	geni_serial_init(&init_dev);
 	geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
@@ -596,7 +596,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	phys_addr_t base = CONFIG_DEBUG_UART_BASE;
+	phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
 
 	writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG);
 	qcom_geni_serial_setup_tx(base, 1);
diff --git a/drivers/serial/serial_mt7620.c b/drivers/serial/serial_mt7620.c
index 76ecc2b..5c5264b 100644
--- a/drivers/serial/serial_mt7620.c
+++ b/drivers/serial/serial_mt7620.c
@@ -220,7 +220,7 @@ static inline void _debug_uart_init(void)
 {
 	struct mt7620_serial_plat plat;
 
-	plat.regs = (void *)CONFIG_DEBUG_UART_BASE;
+	plat.regs = (void *)CONFIG_VAL(DEBUG_UART_BASE);
 	plat.clock = CONFIG_DEBUG_UART_CLOCK;
 
 	writel(0, &plat.regs->ier);
@@ -233,7 +233,7 @@ static inline void _debug_uart_init(void)
 static inline void _debug_uart_putc(int ch)
 {
 	struct mt7620_serial_regs __iomem *regs =
-		(void *)CONFIG_DEBUG_UART_BASE;
+		(void *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (!(readl(&regs->lsr) & UART_LSR_THRE))
 		;
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
index 4145d9f..a84f39b 100644
--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
@@ -426,7 +426,7 @@ static inline void _debug_uart_init(void)
 {
 	struct mtk_serial_priv priv;
 
-	priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
+	priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE);
 	priv.clock = CONFIG_DEBUG_UART_CLOCK;
 
 	writel(0, &priv.regs->ier);
@@ -439,7 +439,7 @@ static inline void _debug_uart_init(void)
 static inline void _debug_uart_putc(int ch)
 {
 	struct mtk_serial_regs __iomem *regs =
-		(void *) CONFIG_DEBUG_UART_BASE;
+		(void *) CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (!(readl(&regs->lsr) & UART_LSR_THRE))
 		;
diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c
index 3e673bd..0fcd7e8 100644
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -321,7 +321,7 @@ U_BOOT_DRIVER(serial_mvebu) = {
 
 static inline void _debug_uart_init(void)
 {
-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
 	u32 parent_rate, divider;
 
 	/* reset FIFOs */
@@ -349,7 +349,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
 		;
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index e4970a1..70a0e5e 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -372,7 +372,7 @@ U_BOOT_DRIVER(serial_mxc) = {
 
 static inline void _debug_uart_init(void)
 {
-	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+	struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	_mxc_serial_init(base, false);
 	_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
@@ -381,7 +381,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+	struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (!(readl(&base->ts) & UTS_TXEMPTY))
 		WATCHDOG_RESET();
diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c
index ee938f6..e9ff61a 100644
--- a/drivers/serial/serial_omap.c
+++ b/drivers/serial/serial_omap.c
@@ -66,7 +66,7 @@ static inline int serial_in_shift(void *addr, int shift)
 
 static inline void _debug_uart_init(void)
 {
-	struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
+	struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
 	int baud_divisor;
 
 	baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
@@ -85,7 +85,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
+	struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
 		;
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
index ccdda9f..3c5d37c 100644
--- a/drivers/serial/serial_pic32.c
+++ b/drivers/serial/serial_pic32.c
@@ -187,14 +187,14 @@ U_BOOT_DRIVER(pic32_serial) = {
 
 static inline void _debug_uart_init(void)
 {
-	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 }
 
 static inline void _debug_uart_putc(int ch)
 {
-	writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);
+	writel(ch, CONFIG_VAL(DEBUG_UART_BASE) + U_TXR);
 }
 
 DEBUG_UART_FUNCS
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 67caa06..9b0d16f 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -403,7 +403,7 @@ U_BOOT_DRIVER(serial_pl01x) = {
 static void _debug_uart_init(void)
 {
 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
-	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
+	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
 	enum pl01x_type type;
 
 	if (IS_ENABLED(CONFIG_DEBUG_UART_PL011))
@@ -419,7 +419,7 @@ static void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
+	struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (pl01x_putc(regs, ch) == -EAGAIN)
 		;
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
deleted file mode 100644
index 330fc12..0000000
--- a/drivers/serial/serial_pxa.c
+++ /dev/null
@@ -1,343 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- *
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * Modified to add driver model (DM) support
- * (C) Copyright 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
- */
-
-#include <common.h>
-#include <hang.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/regs-uart.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <dm.h>
-#include <dm/platform_data/serial_pxa.h>
-#include <linux/compiler.h>
-#include <serial.h>
-#include <watchdog.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static uint32_t pxa_uart_get_baud_divider(int baudrate)
-{
-	return 921600 / baudrate;
-}
-
-static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
-{
-	uint32_t clk_reg, clk_offset, reg;
-
-	clk_reg = UART_CLK_REG;
-	clk_offset = UART_CLK_BASE << uart_index;
-
-	reg = readl(clk_reg);
-
-	if (enable)
-		reg |= clk_offset;
-	else
-		reg &= ~clk_offset;
-
-	writel(reg, clk_reg);
-}
-
-/*
- * Enable clock and set baud rate, parity etc.
- */
-void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate)
-{
-	uint32_t divider = pxa_uart_get_baud_divider(baudrate);
-	if (!divider)
-		hang();
-
-
-	pxa_uart_toggle_clock(port, 1);
-
-	/* Disable interrupts and FIFOs */
-	writel(0, &uart_regs->ier);
-	writel(0, &uart_regs->fcr);
-
-	/* Set baud rate */
-	writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr);
-	writel(divider & 0xff, &uart_regs->dll);
-	writel(divider >> 8, &uart_regs->dlh);
-	writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr);
-
-	/* Enable UART */
-	writel(IER_UUE, &uart_regs->ier);
-}
-
-#ifndef CONFIG_DM_SERIAL
-static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
-{
-	switch (uart_index) {
-	case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
-	case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
-	case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
-	case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
-	default:
-		return NULL;
-	}
-}
-
-/*
- * Enable clock and set baud rate, parity etc.
- */
-void pxa_setbrg_dev(uint32_t uart_index)
-{
-	struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index);
-	if (!uart_regs)
-		panic("Failed getting UART registers\n");
-
-	pxa_setbrg_common(uart_regs, uart_index, gd->baudrate);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-int pxa_init_dev(unsigned int uart_index)
-{
-	pxa_setbrg_dev(uart_index);
-	return 0;
-}
-
-/*
- * Output a single byte to the serial port.
- */
-void pxa_putc_dev(unsigned int uart_index, const char c)
-{
-	struct pxa_uart_regs *uart_regs;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		pxa_putc_dev(uart_index, '\r');
-
-	uart_regs = pxa_uart_index_to_regs(uart_index);
-	if (!uart_regs)
-		hang();
-
-	while (!(readl(&uart_regs->lsr) & LSR_TEMT))
-		WATCHDOG_RESET();
-	writel(c, &uart_regs->thr);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int pxa_tstc_dev(unsigned int uart_index)
-{
-	struct pxa_uart_regs *uart_regs;
-
-	uart_regs = pxa_uart_index_to_regs(uart_index);
-	if (!uart_regs)
-		return -1;
-
-	return readl(&uart_regs->lsr) & LSR_DR;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int pxa_getc_dev(unsigned int uart_index)
-{
-	struct pxa_uart_regs *uart_regs;
-
-	uart_regs = pxa_uart_index_to_regs(uart_index);
-	if (!uart_regs)
-		return -1;
-
-	while (!(readl(&uart_regs->lsr) & LSR_DR))
-		WATCHDOG_RESET();
-	return readl(&uart_regs->rbr) & 0xff;
-}
-
-void pxa_puts_dev(unsigned int uart_index, const char *s)
-{
-	while (*s)
-		pxa_putc_dev(uart_index, *s++);
-}
-
-#define	pxa_uart(uart, UART)						\
-	int uart##_init(void)						\
-	{								\
-		return pxa_init_dev(UART##_INDEX);			\
-	}								\
-									\
-	void uart##_setbrg(void)					\
-	{								\
-		return pxa_setbrg_dev(UART##_INDEX);			\
-	}								\
-									\
-	void uart##_putc(const char c)					\
-	{								\
-		return pxa_putc_dev(UART##_INDEX, c);			\
-	}								\
-									\
-	void uart##_puts(const char *s)					\
-	{								\
-		return pxa_puts_dev(UART##_INDEX, s);			\
-	}								\
-									\
-	int uart##_getc(void)						\
-	{								\
-		return pxa_getc_dev(UART##_INDEX);			\
-	}								\
-									\
-	int uart##_tstc(void)						\
-	{								\
-		return pxa_tstc_dev(UART##_INDEX);			\
-	}								\
-
-#define	pxa_uart_desc(uart)						\
-	struct serial_device serial_##uart##_device =			\
-	{								\
-		.name	= "serial_"#uart,				\
-		.start	= uart##_init,					\
-		.stop	= NULL,						\
-		.setbrg	= uart##_setbrg,				\
-		.getc	= uart##_getc,					\
-		.tstc	= uart##_tstc,					\
-		.putc	= uart##_putc,					\
-		.puts	= uart##_puts,					\
-	};
-
-#define	pxa_uart_multi(uart, UART)					\
-	pxa_uart(uart, UART)						\
-	pxa_uart_desc(uart)
-
-#if defined(CONFIG_HWUART)
-	pxa_uart_multi(hwuart, HWUART)
-#endif
-#if defined(CONFIG_STUART)
-	pxa_uart_multi(stuart, STUART)
-#endif
-#if defined(CONFIG_FFUART)
-	pxa_uart_multi(ffuart, FFUART)
-#endif
-#if defined(CONFIG_BTUART)
-	pxa_uart_multi(btuart, BTUART)
-#endif
-
-__weak struct serial_device *default_serial_console(void)
-{
-#if CONFIG_CONS_INDEX == 1
-	return &serial_hwuart_device;
-#elif CONFIG_CONS_INDEX == 2
-	return &serial_stuart_device;
-#elif CONFIG_CONS_INDEX == 3
-	return &serial_ffuart_device;
-#elif CONFIG_CONS_INDEX == 4
-	return &serial_btuart_device;
-#else
-#error "Bad CONFIG_CONS_INDEX."
-#endif
-}
-
-void pxa_serial_initialize(void)
-{
-#if defined(CONFIG_FFUART)
-	serial_register(&serial_ffuart_device);
-#endif
-#if defined(CONFIG_BTUART)
-	serial_register(&serial_btuart_device);
-#endif
-#if defined(CONFIG_STUART)
-	serial_register(&serial_stuart_device);
-#endif
-}
-#endif /* CONFIG_DM_SERIAL */
-
-#ifdef CONFIG_DM_SERIAL
-static int pxa_serial_probe(struct udevice *dev)
-{
-	struct pxa_serial_plat *plat = dev_get_plat(dev);
-
-	pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port,
-			  plat->baudrate);
-	return 0;
-}
-
-static int pxa_serial_putc(struct udevice *dev, const char ch)
-{
-	struct pxa_serial_plat *plat = dev_get_plat(dev);
-	struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
-
-	/* Wait for last character to go. */
-	if (!(readl(&uart_regs->lsr) & LSR_TEMT))
-		return -EAGAIN;
-
-	writel(ch, &uart_regs->thr);
-
-	return 0;
-}
-
-static int pxa_serial_getc(struct udevice *dev)
-{
-	struct pxa_serial_plat *plat = dev_get_plat(dev);
-	struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
-
-	/* Wait for a character to arrive. */
-	if (!(readl(&uart_regs->lsr) & LSR_DR))
-		return -EAGAIN;
-
-	return readl(&uart_regs->rbr) & 0xff;
-}
-
-int pxa_serial_setbrg(struct udevice *dev, int baudrate)
-{
-	struct pxa_serial_plat *plat = dev_get_plat(dev);
-	struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
-	int port = plat->port;
-
-	pxa_setbrg_common(uart_regs, port, baudrate);
-
-	return 0;
-}
-
-static int pxa_serial_pending(struct udevice *dev, bool input)
-{
-	struct pxa_serial_plat *plat = dev_get_plat(dev);
-	struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
-
-	if (input)
-		return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0;
-	else
-		return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1;
-
-	return 0;
-}
-
-static const struct dm_serial_ops pxa_serial_ops = {
-	.putc		= pxa_serial_putc,
-	.pending	= pxa_serial_pending,
-	.getc		= pxa_serial_getc,
-	.setbrg		= pxa_serial_setbrg,
-};
-
-U_BOOT_DRIVER(serial_pxa) = {
-	.name	= "serial_pxa",
-	.id	= UCLASS_SERIAL,
-	.probe	= pxa_serial_probe,
-	.ops	= &pxa_serial_ops,
-	.flags	= DM_FLAG_PRE_RELOC,
-};
-#endif /* CONFIG_DM_SERIAL */
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index de420d2..4b3947e 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -276,7 +276,7 @@ static inline void _debug_uart_init(void)
 	if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT))
 		return;
 
-	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
+	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	s5p_serial_init(uart);
 #if CONFIG_IS_ENABLED(ARCH_APPLE)
@@ -288,7 +288,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE;
+	struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE);
 
 #if CONFIG_IS_ENABLED(ARCH_APPLE)
 	while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL);
diff --git a/drivers/serial/serial_semihosting.c b/drivers/serial/serial_semihosting.c
index 2561414..cfa1ec3 100644
--- a/drivers/serial/serial_semihosting.c
+++ b/drivers/serial/serial_semihosting.c
@@ -13,10 +13,12 @@
  * struct smh_serial_priv - Semihosting serial private data
  * @infd: stdin file descriptor (or error)
  * @outfd: stdout file descriptor (or error)
+ * @counter: Counter used to fake pending every other call
  */
 struct smh_serial_priv {
 	int infd;
 	int outfd;
+	unsigned counter;
 };
 
 #if CONFIG_IS_ENABLED(DM_SERIAL)
@@ -68,10 +70,20 @@ static ssize_t smh_serial_puts(struct udevice *dev, const char *s, size_t len)
 	return ret;
 }
 
+static int smh_serial_pending(struct udevice *dev, bool input)
+{
+	struct smh_serial_priv *priv = dev_get_priv(dev);
+
+	if (input)
+		return priv->counter++ & 1;
+	return false;
+}
+
 static const struct dm_serial_ops smh_serial_ops = {
 	.putc = smh_serial_putc,
 	.puts = smh_serial_puts,
 	.getc = smh_serial_getc,
+	.pending = smh_serial_pending,
 };
 
 static int smh_serial_bind(struct udevice *dev)
@@ -106,6 +118,7 @@ U_BOOT_DRVINFO(smh_serial) = {
 #else /* DM_SERIAL */
 static int infd = -ENODEV;
 static int outfd = -ENODEV;
+static unsigned counter = 1;
 
 static int smh_serial_start(void)
 {
@@ -138,7 +151,7 @@ static int smh_serial_getc(void)
 
 static int smh_serial_tstc(void)
 {
-	return 1;
+	return counter++ & 1;
 }
 
 static void smh_serial_puts(const char *s)
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index 794f9c9..4af1ff5 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -212,7 +212,7 @@ U_BOOT_DRIVER(serial_sifive) = {
 static inline void _debug_uart_init(void)
 {
 	struct uart_sifive *regs =
-			(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
+			(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	_sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
 			      CONFIG_BAUDRATE);
@@ -222,7 +222,7 @@ static inline void _debug_uart_init(void)
 static inline void _debug_uart_putc(int ch)
 {
 	struct uart_sifive *regs =
-			(struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
+			(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (_sifive_serial_putc(regs, ch) == -EAGAIN)
 		WATCHDOG_RESET();
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index f6cb708..2ba92bf 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -270,7 +270,7 @@ static inline struct stm32_uart_info *_debug_uart_info(void)
 
 static inline void _debug_uart_init(void)
 {
-	fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+	fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
 	struct stm32_uart_info *uart_info = _debug_uart_info();
 
 	_stm32_serial_init(base, uart_info);
@@ -281,7 +281,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int c)
 {
-	fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+	fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
 	struct stm32_uart_info *uart_info = _debug_uart_info();
 
 	while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 9780a44..b6197da 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -143,7 +143,7 @@ U_BOOT_DRIVER(serial_uartlite) = {
 
 static inline void _debug_uart_init(void)
 {
-	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+	struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
 	int ret;
 
 	uart_out32(&regs->control, 0);
@@ -159,7 +159,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE;
+	struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (uart_in32(&regs->status) & SR_TX_FIFO_FULL)
 		;
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 6bb003d..83adfb5 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -295,7 +295,7 @@ U_BOOT_DRIVER(serial_zynq) = {
 #ifdef CONFIG_DEBUG_UART_ZYNQ
 static inline void _debug_uart_init(void)
 {
-	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	_uart_zynq_serial_init(regs);
 	_uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
@@ -304,7 +304,7 @@ static inline void _debug_uart_init(void)
 
 static inline void _debug_uart_putc(int ch)
 {
-	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;
+	struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
 
 	while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
 		WATCHDOG_RESET();
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index 05b3c01..0d89fc0 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -13,8 +13,6 @@
 #include <usbdevice.h>
 #if defined(CONFIG_PPC)
 #include <usb/mpc8xx_udc.h>
-#elif defined(CONFIG_CPU_PXA27X)
-#include <usb/pxa27x_udc.h>
 #elif defined(CONFIG_DW_UDC)
 #include <usb/designware_udc.h>
 #elif defined(CONFIG_CI_UDC)
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 965728e..b1e7c4a 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -15,6 +15,7 @@
 #define J7200			0xbb6d
 #define AM64X			0xbb38
 #define J721S2			0xbb75
+#define AM62X			0xbb7e
 
 #define JTAG_ID_VARIANT_SHIFT	28
 #define JTAG_ID_VARIANT_MASK	(0xf << 28)
@@ -49,6 +50,9 @@ static const char *get_family_string(u32 idreg)
 	case J721S2:
 		family = "J721S2";
 		break;
+	case AM62X:
+		family = "AM62X";
+		break;
 	default:
 		family = "Unknown Silicon";
 	};
@@ -60,8 +64,8 @@ static char *j721e_rev_string_map[] = {
 	"1.0", "1.1",
 };
 
-static char *am65x_rev_string_map[] = {
-	"1.0", "2.0",
+static char *typical_rev_string_map[] = {
+	"1.0", "2.0", "3.0",
 };
 
 static const char *get_rev_string(u32 idreg)
@@ -78,16 +82,10 @@ static const char *get_rev_string(u32 idreg)
 			goto bail;
 		return j721e_rev_string_map[rev];
 
-	case AM65X:
-		if (rev > ARRAY_SIZE(am65x_rev_string_map))
-			goto bail;
-		return am65x_rev_string_map[rev];
-
-	case AM64X:
-	case J7200:
 	default:
-		if (!rev)
-			return "1.0";
+		if (rev > ARRAY_SIZE(typical_rev_string_map))
+			goto bail;
+		return typical_rev_string_map[rev];
 	};
 
 bail:
diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c
index a71115b..c10fc7d 100644
--- a/drivers/soc/soc_xilinx_zynqmp.c
+++ b/drivers/soc/soc_xilinx_zynqmp.c
@@ -3,10 +3,15 @@
  * Xilinx ZynqMP SOC driver
  *
  * Copyright (C) 2021 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
+ * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
  */
 
 #include <common.h>
 #include <dm.h>
+#include <dm/device_compat.h>
 #include <asm/cache.h>
 #include <soc.h>
 #include <zynqmp_firmware.h>
@@ -22,11 +27,257 @@
  */
 static const char zynqmp_family[] = "ZynqMP";
 
+#define EFUSE_VCU_DIS_SHIFT	8
+#define EFUSE_VCU_DIS_MASK	BIT(EFUSE_VCU_DIS_SHIFT)
+#define EFUSE_GPU_DIS_SHIFT	5
+#define EFUSE_GPU_DIS_MASK	BIT(EFUSE_GPU_DIS_SHIFT)
+#define IDCODE_DEV_TYPE_MASK	GENMASK(27, 0)
+#define IDCODE2_PL_INIT_SHIFT	9
+#define IDCODE2_PL_INIT_MASK	BIT(IDCODE2_PL_INIT_SHIFT)
+
+#define ZYNQMP_VERSION_SIZE	7
+
+enum {
+	ZYNQMP_VARIANT_EG = BIT(0),
+	ZYNQMP_VARIANT_EV = BIT(1),
+	ZYNQMP_VARIANT_CG = BIT(2),
+	ZYNQMP_VARIANT_DR = BIT(3),
+};
+
+struct zynqmp_device {
+	u32 id;
+	u8 device;
+	u8 variants;
+};
+
 struct soc_xilinx_zynqmp_priv {
 	const char *family;
+	char machine[ZYNQMP_VERSION_SIZE];
 	char revision;
 };
 
+static const struct zynqmp_device zynqmp_devices[] = {
+	{
+		.id = 0x04688093,
+		.device = 1,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04711093,
+		.device = 2,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04710093,
+		.device = 3,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04721093,
+		.device = 4,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04720093,
+		.device = 5,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04739093,
+		.device = 6,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04730093,
+		.device = 7,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
+			ZYNQMP_VARIANT_EV,
+	},
+	{
+		.id = 0x04738093,
+		.device = 9,
+		.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
+	},
+	{
+		.id = 0x04740093,
+		.device = 11,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04750093,
+		.device = 15,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04759093,
+		.device = 17,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x04758093,
+		.device = 19,
+		.variants = ZYNQMP_VARIANT_EG,
+	},
+	{
+		.id = 0x047E1093,
+		.device = 21,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E3093,
+		.device = 23,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E5093,
+		.device = 25,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E4093,
+		.device = 27,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E0093,
+		.device = 28,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E2093,
+		.device = 29,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047E6093,
+		.device = 39,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FD093,
+		.device = 43,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047F8093,
+		.device = 46,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FF093,
+		.device = 47,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FB093,
+		.device = 48,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x047FE093,
+		.device = 49,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x046d0093,
+		.device = 67,
+		.variants = ZYNQMP_VARIANT_DR,
+	},
+	{
+		.id = 0x04714093,
+		.device = 24,
+		.variants = 0,
+	},
+	{
+		.id = 0x04724093,
+		.device = 26,
+		.variants = 0,
+	},
+};
+
+static const struct zynqmp_device *zynqmp_get_device(u32 idcode)
+{
+	idcode &= IDCODE_DEV_TYPE_MASK;
+
+	for (int i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
+		if (zynqmp_devices[i].id == idcode)
+			return &zynqmp_devices[i];
+	}
+
+	return NULL;
+}
+
+static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
+					    u32 idcode2)
+{
+	struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
+	const struct zynqmp_device *device;
+	int ret;
+
+	device = zynqmp_get_device(idcode);
+	if (!device)
+		return 0;
+
+	/* Add device prefix to the name */
+	ret = snprintf(priv->machine, sizeof(priv->machine), "%s%d",
+		       device->variants ? "zu" : "xck", device->device);
+	if (ret < 0)
+		return ret;
+
+	if (device->variants & ZYNQMP_VARIANT_EV) {
+		/* Devices with EV variant might be EG/CG/EV family */
+		if (idcode2 & IDCODE2_PL_INIT_MASK) {
+			u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
+				      EFUSE_VCU_DIS_SHIFT) << 1 |
+				     ((idcode2 & EFUSE_GPU_DIS_MASK) >>
+				      EFUSE_GPU_DIS_SHIFT);
+
+			/*
+			 * Get family name based on extended idcode values as
+			 * determined on UG1087, EXTENDED_IDCODE register
+			 * description
+			 */
+			switch (family) {
+			case 0x00:
+				strlcat(priv->machine, "ev",
+					sizeof(priv->machine));
+				break;
+			case 0x10:
+				strlcat(priv->machine, "eg",
+					sizeof(priv->machine));
+				break;
+			case 0x11:
+				strlcat(priv->machine, "cg",
+					sizeof(priv->machine));
+				break;
+			default:
+				/* Do not append family name*/
+				break;
+			}
+		} else {
+			/*
+			 * When PL powered down the VCU Disable efuse cannot be
+			 * read. So, ignore the bit and just findout if it is CG
+			 * or EG/EV variant.
+			 */
+			strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
+				"cg" : "e", sizeof(priv->machine));
+		}
+	} else if (device->variants & ZYNQMP_VARIANT_CG) {
+		/* Devices with CG variant might be EG or CG family */
+		strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
+			"cg" : "eg", sizeof(priv->machine));
+	} else if (device->variants & ZYNQMP_VARIANT_EG) {
+		strlcat(priv->machine, "eg", sizeof(priv->machine));
+	} else if (device->variants & ZYNQMP_VARIANT_DR) {
+		strlcat(priv->machine, "dr", sizeof(priv->machine));
+	}
+
+	return 0;
+}
+
 static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size)
 {
 	struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
@@ -34,6 +285,17 @@ static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size
 	return snprintf(buf, size, "%s", priv->family);
 }
 
+int soc_xilinx_zynqmp_get_machine(struct udevice *dev, char *buf, int size)
+{
+	struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
+	const char *machine = priv->machine;
+
+	if (!machine[0])
+		machine = "unknown";
+
+	return snprintf(buf, size, "%s", machine);
+}
+
 static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size)
 {
 	struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
@@ -44,6 +306,7 @@ static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int si
 static const struct soc_ops soc_xilinx_zynqmp_ops = {
 	.get_family = soc_xilinx_zynqmp_get_family,
 	.get_revision = soc_xilinx_zynqmp_get_revision,
+	.get_machine = soc_xilinx_zynqmp_get_machine,
 };
 
 static int soc_xilinx_zynqmp_probe(struct udevice *dev)
@@ -54,8 +317,7 @@ static int soc_xilinx_zynqmp_probe(struct udevice *dev)
 
 	priv->family = zynqmp_family;
 
-	if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3 ||
-	    !IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
+	if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
 		ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]);
 	else
 		ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
@@ -65,6 +327,26 @@ static int soc_xilinx_zynqmp_probe(struct udevice *dev)
 
 	priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK;
 
+	if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
+		/*
+		 * Firmware returns:
+		 * payload[0][31:0] = status of the operation
+		 * payload[1] = IDCODE
+		 * payload[2][19:0] = Version
+		 * payload[2][28:20] = EXTENDED_IDCODE
+		 * payload[2][29] = PL_INIT
+		 */
+		u32 idcode = ret_payload[1];
+		u32 idcode2 = ret_payload[2] >>
+				   ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
+		dev_dbg(dev, "IDCODE: 0x%0x, IDCODE2: 0x%0x\n", idcode,
+			idcode2);
+
+		ret = soc_xilinx_zynqmp_detect_machine(dev, idcode, idcode2);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c
index 8d674bc..c1edef4 100644
--- a/drivers/sound/da7219.c
+++ b/drivers/sound/da7219.c
@@ -23,6 +23,7 @@
 
 #define DA7219_ACPI_HID		"DLGS7219"
 
+__maybe_unused
 static int da7219_acpi_fill_ssdt(const struct udevice *dev,
 				 struct acpi_ctx *ctx)
 {
@@ -171,10 +172,12 @@ static int da7219_acpi_setup_nhlt(const struct udevice *dev,
 #endif
 
 struct acpi_ops da7219_acpi_ops = {
+#ifdef CONFIG_ACPIGEN
 	.fill_ssdt	= da7219_acpi_fill_ssdt,
 #ifdef CONFIG_X86
 	.setup_nhlt	= da7219_acpi_setup_nhlt,
 #endif
+#endif
 };
 
 static const struct udevice_id da7219_ids[] = {
diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c
index a2088f0..bdf6dc2 100644
--- a/drivers/sound/max98357a.c
+++ b/drivers/sound/max98357a.c
@@ -38,6 +38,7 @@ static int max98357a_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
+__maybe_unused
 static int max98357a_acpi_fill_ssdt(const struct udevice *dev,
 				    struct acpi_ctx *ctx)
 {
@@ -137,10 +138,12 @@ static int max98357a_acpi_setup_nhlt(const struct udevice *dev,
 #endif
 
 struct acpi_ops max98357a_acpi_ops = {
+#ifdef CONFIG_ACPIGEN
 	.fill_ssdt	= max98357a_acpi_fill_ssdt,
 #ifdef CONFIG_X86
 	.setup_nhlt	= max98357a_acpi_setup_nhlt,
 #endif
+#endif
 };
 
 static const struct audio_codec_ops max98357a_ops = {
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1e515c..766d563 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -136,6 +136,14 @@ config CQSPI_REF_CLK
 	int "Cadence QSPI reference clock value in Hz"
 	depends on HAS_CQSPI_REF_CLK
 
+config CADENCE_OSPI_VERSAL
+	bool "Configure Versal OSPI"
+	depends on ARCH_VERSAL && CADENCE_QSPI
+	imply DM_GPIO
+	help
+	  This option is used to enable Versal OSPI DMA operations which
+	  are used for ospi flash read using cadence qspi controller.
+
 config CF_SPI
         bool "ColdFire SPI driver"
         help
@@ -186,6 +194,12 @@ config FSL_QSPI_AHB_FULL_MAP
 	  Enable the Freescale QSPI driver to use full AHB memory map space for
 	  flash access.
 
+config GXP_SPI
+	bool "SPI driver for GXP"
+	imply SPI_FLASH_BAR
+	help
+	  Enable support for SPI on GXP.
+
 config ICH_SPI
 	bool "Intel ICH SPI driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06e81b4..4de77c2 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -7,6 +7,7 @@
 ifdef CONFIG_$(SPL_TPL_)DM_SPI
 obj-y += spi-uclass.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
+obj-$(CONFIG_CADENCE_OSPI_VERSAL) += cadence_ospi_versal.o
 obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
 obj-$(CONFIG_SOFT_SPI) += soft_spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem.o
@@ -33,6 +34,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
+obj-$(CONFIG_GXP_SPI) += gxp_spi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
new file mode 100644
index 0000000..52bcad0
--- /dev/null
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2018 Xilinx
+ *
+ * Cadence QSPI controller DMA operations
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <memalign.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/cache.h>
+#include <cpu_func.h>
+#include <zynqmp_firmware.h>
+#include <asm/arch/hardware.h>
+#include "cadence_qspi.h"
+#include <dt-bindings/power/xlnx-versal-power.h>
+
+#define CMD_4BYTE_READ  0x13
+#define CMD_4BYTE_FAST_READ  0x0C
+
+int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
+			      const struct spi_mem_op *op)
+{
+	u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
+	u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
+
+	n_rx = op->data.nbytes;
+	rxbuf = op->data.buf.in;
+	rx_rem = n_rx % 4;
+	bytes_to_dma = n_rx - rx_rem;
+
+	if (bytes_to_dma) {
+		cadence_qspi_apb_enable_linear_mode(false);
+		reg = readl(plat->regbase + CQSPI_REG_CONFIG);
+		reg |= CQSPI_REG_CONFIG_ENBL_DMA;
+		writel(reg, plat->regbase + CQSPI_REG_CONFIG);
+
+		writel(bytes_to_dma, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
+
+		writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE,
+		       plat->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
+		writel(CQSPI_DFLT_DMA_PERIPH_CFG,
+		       plat->regbase + CQSPI_REG_DMA_PERIPH_CFG);
+		writel((unsigned long)rxbuf, plat->regbase +
+		       CQSPI_DMA_DST_ADDR_REG);
+		writel(plat->trigger_address, plat->regbase +
+		       CQSPI_DMA_SRC_RD_ADDR_REG);
+		writel(bytes_to_dma, plat->regbase +
+		       CQSPI_DMA_DST_SIZE_REG);
+		flush_dcache_range((unsigned long)rxbuf,
+				   (unsigned long)rxbuf + bytes_to_dma);
+		writel(CQSPI_DFLT_DST_CTRL_REG_VAL,
+		       plat->regbase + CQSPI_DMA_DST_CTRL_REG);
+
+		/* Start the indirect read transfer */
+		writel(CQSPI_REG_INDIRECTRD_START, plat->regbase +
+		       CQSPI_REG_INDIRECTRD);
+		/* Wait for dma to complete transfer */
+		ret = cadence_qspi_apb_wait_for_dma_cmplt(plat);
+		if (ret)
+			return ret;
+
+		/* Clear indirect completion status */
+		writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase +
+		       CQSPI_REG_INDIRECTRD);
+		rxbuf += bytes_to_dma;
+	}
+
+	if (rx_rem) {
+		reg = readl(plat->regbase + CQSPI_REG_CONFIG);
+		reg &= ~CQSPI_REG_CONFIG_ENBL_DMA;
+		writel(reg, plat->regbase + CQSPI_REG_CONFIG);
+
+		reg = readl(plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+		reg += bytes_to_dma;
+		writel(reg, plat->regbase + CQSPI_REG_CMDADDRESS);
+
+		addr_bytes = readl(plat->regbase + CQSPI_REG_SIZE) &
+				   CQSPI_REG_SIZE_ADDRESS_MASK;
+
+		opcode = CMD_4BYTE_FAST_READ;
+		dummy_cycles = 8;
+		writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
+		       plat->regbase + CQSPI_REG_RD_INSTR);
+
+		reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+		reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
+		reg |= (addr_bytes & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
+			CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
+		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
+		dummy_cycles = (readl(plat->regbase + CQSPI_REG_RD_INSTR) >>
+				CQSPI_REG_RD_INSTR_DUMMY_LSB) &
+				CQSPI_REG_RD_INSTR_DUMMY_MASK;
+		reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) <<
+			CQSPI_REG_CMDCTRL_DUMMY_LSB;
+		reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) <<
+			CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
+		ret = cadence_qspi_apb_exec_flash_cmd(plat->regbase, reg);
+		if (ret)
+			return ret;
+
+		data = readl(plat->regbase + CQSPI_REG_CMDREADDATALOWER);
+		memcpy(rxbuf, &data, rx_rem);
+	}
+
+	return 0;
+}
+
+int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat)
+{
+	u32 timeout = CQSPI_DMA_TIMEOUT;
+
+	while (!(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG) &
+		 CQSPI_DMA_DST_I_STS_DONE) && timeout--)
+		udelay(1);
+
+	if (!timeout) {
+		printf("DMA timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	writel(readl(plat->regbase + CQSPI_DMA_DST_I_STS_REG),
+	       plat->regbase + CQSPI_DMA_DST_I_STS_REG);
+	return 0;
+}
+
+#if defined(CONFIG_DM_GPIO)
+int cadence_spi_versal_flash_reset(struct udevice *dev)
+{
+	struct gpio_desc gpio;
+	u32 reset_gpio;
+	int ret;
+
+	/* request gpio and set direction as output set to 1 */
+	ret = gpio_request_by_name(dev, "reset-gpios", 0, &gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret) {
+		printf("%s: unable to reset ospi flash device", __func__);
+		return ret;
+	}
+
+	reset_gpio = PMIO_NODE_ID_BASE + gpio.offset;
+
+	/* Request for pin */
+	xilinx_pm_request(PM_PINCTRL_REQUEST, reset_gpio, 0, 0, 0, NULL);
+
+	/* Enable hysteresis in cmos receiver */
+	xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
+			  PM_PINCTRL_CONFIG_SCHMITT_CMOS,
+			  PM_PINCTRL_INPUT_TYPE_SCHMITT, 0, NULL);
+
+	/* Disable Tri-state */
+	xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, reset_gpio,
+			  PM_PINCTRL_CONFIG_TRI_STATE,
+			  PM_PINCTRL_TRI_STATE_DISABLE, 0, NULL);
+	udelay(1);
+
+	/* Set value 0 to pin */
+	dm_gpio_set_value(&gpio, 0);
+	udelay(1);
+
+	/* Set value 1 to pin */
+	dm_gpio_set_value(&gpio, 1);
+	udelay(1);
+
+	return 0;
+}
+#else
+int cadence_spi_versal_flash_reset(struct udevice *dev)
+{
+	/* CRP WPROT */
+	writel(0, WPROT_CRP);
+	/* GPIO Reset */
+	writel(0, RST_GPIO);
+
+	/* disable IOU write protection */
+	writel(0, WPROT_LPD_MIO);
+
+	/* set direction as output */
+	writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)),
+	       BOOT_MODE_POR_0);
+
+	/* Data output enable */
+	writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)),
+	       BOOT_MODE_POR_1);
+
+	/* IOU SLCR write enable */
+	writel(0, WPROT_PMC_MIO);
+
+	/* set MIO as GPIO */
+	writel(0x60, MIO_PIN_12);
+
+	/* Set value 1 to pin */
+	writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
+	udelay(10);
+
+	/* Disable Tri-state */
+	writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
+	udelay(1);
+
+	/* Set value 0 to pin */
+	writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
+	udelay(10);
+
+	/* Set value 1 to pin */
+	writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
+	udelay(10);
+
+	return 0;
+}
+#endif
+
+void cadence_qspi_apb_enable_linear_mode(bool enable)
+{
+	if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) {
+		if (enable)
+			/* ahb read mode */
+			xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
+					  IOCTL_OSPI_MUX_SELECT,
+					  PM_OSPI_MUX_SEL_LINEAR, 0, NULL);
+		else
+			/* DMA mode */
+			xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
+					  IOCTL_OSPI_MUX_SELECT,
+					  PM_OSPI_MUX_SEL_DMA, 0, NULL);
+	} else {
+		if (enable)
+			writel(readl(VERSAL_AXI_MUX_SEL) |
+			       VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
+		else
+			writel(readl(VERSAL_AXI_MUX_SEL) &
+			       ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
+	}
+}
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 7209bb4..907f5da 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -18,7 +18,9 @@
 #include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/sizes.h>
+#include <zynqmp_firmware.h>
 #include "cadence_qspi.h"
+#include <dt-bindings/power/xlnx-versal-power.h>
 
 #define NSEC_PER_SEC			1000000000L
 
@@ -27,6 +29,17 @@
 #define CQSPI_READ			2
 #define CQSPI_WRITE			3
 
+__weak int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
+				     const struct spi_mem_op *op)
+{
+	return 0;
+}
+
+__weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
+{
+	return 0;
+}
+
 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
 {
 	struct cadence_spi_plat *plat = dev_get_plat(bus);
@@ -138,7 +151,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
 	int err;
 
-	if (hz > plat->max_hz)
+	if (!hz || hz > plat->max_hz)
 		hz = plat->max_hz;
 
 	/* Disable QSPI */
@@ -185,6 +198,11 @@ static int cadence_spi_probe(struct udevice *bus)
 	priv->regbase = plat->regbase;
 	priv->ahbbase = plat->ahbbase;
 
+	if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE))
+		xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
+				  ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
+				  ZYNQMP_PM_REQUEST_ACK_NO, NULL);
+
 	if (plat->ref_clk_hz == 0) {
 		ret = clk_get_by_index(bus, 0, &clk);
 		if (ret) {
@@ -214,6 +232,16 @@ static int cadence_spi_probe(struct udevice *bus)
 
 	plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz);
 
+	if (CONFIG_IS_ENABLED(ARCH_VERSAL)) {
+		/* Versal platform uses spi calibration to set read delay */
+		if (plat->read_delay >= 0)
+			plat->read_delay = -1;
+		/* Reset ospi flash device */
+		ret = cadence_qspi_versal_flash_reset(bus);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
@@ -288,8 +316,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
 		break;
 	case CQSPI_READ:
 		err = cadence_qspi_apb_read_setup(plat, op);
-		if (!err)
-			err = cadence_qspi_apb_read_execute(plat, op);
+		if (!err) {
+			if (plat->is_dma)
+				err = cadence_qspi_apb_dma_read(plat, op);
+			else
+				err = cadence_qspi_apb_read_execute(plat, op);
+		}
 		break;
 	case CQSPI_WRITE:
 		err = cadence_qspi_apb_write_setup(plat, op);
@@ -342,6 +374,8 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
 	if (plat->ahbsize >= SZ_8M)
 		plat->use_dac_mode = true;
 
+	plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
+
 	/* All other paramters are embedded in the child node */
 	subnode = dev_read_first_subnode(bus);
 	if (!ofnode_valid(subnode)) {
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index a2b620a..c8d16bb 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -8,6 +8,8 @@
 #define __CADENCE_QSPI_H__
 
 #include <reset.h>
+#include <linux/mtd/spi-nor.h>
+#include <spi-mem.h>
 
 #define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)
 
@@ -15,6 +17,186 @@
 #define CQSPI_DECODER_MAX_CS		16
 #define CQSPI_READ_CAPTURE_MAX_DELAY	16
 
+#define CQSPI_REG_POLL_US                       1 /* 1us */
+#define CQSPI_REG_RETRY                         10000
+#define CQSPI_POLL_IDLE_RETRY                   3
+
+/* Transfer mode */
+#define CQSPI_INST_TYPE_SINGLE                  0
+#define CQSPI_INST_TYPE_DUAL                    1
+#define CQSPI_INST_TYPE_QUAD                    2
+#define CQSPI_INST_TYPE_OCTAL                   3
+
+#define CQSPI_STIG_DATA_LEN_MAX                 8
+
+#define CQSPI_DUMMY_CLKS_PER_BYTE               8
+#define CQSPI_DUMMY_BYTES_MAX                   4
+#define CQSPI_DUMMY_CLKS_MAX                    31
+
+/****************************************************************************
+ * Controller's configuration and status register (offset from QSPI_BASE)
+ ****************************************************************************/
+#define CQSPI_REG_CONFIG                        0x00
+#define CQSPI_REG_CONFIG_ENABLE                 BIT(0)
+#define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
+#define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
+#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK        BIT(3)
+#define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
+#define CQSPI_REG_CONFIG_DECODE                 BIT(9)
+#define CQSPI_REG_CONFIG_ENBL_DMA               BIT(15)
+#define CQSPI_REG_CONFIG_XIP_IMM                BIT(18)
+#define CQSPI_REG_CONFIG_DTR_PROT_EN_MASK       BIT(24)
+#define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
+#define CQSPI_REG_CONFIG_BAUD_LSB               19
+#define CQSPI_REG_CONFIG_DTR_PROTO		BIT(24)
+#define CQSPI_REG_CONFIG_DUAL_OPCODE		BIT(30)
+#define CQSPI_REG_CONFIG_IDLE_LSB               31
+#define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
+#define CQSPI_REG_CONFIG_BAUD_MASK              0xF
+
+#define CQSPI_REG_RD_INSTR                      0x04
+#define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
+#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
+#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
+#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
+#define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
+#define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
+#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
+#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
+#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
+#define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
+
+#define CQSPI_REG_WR_INSTR                      0x08
+#define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
+#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB	12
+#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB	16
+
+#define CQSPI_REG_DELAY                         0x0C
+#define CQSPI_REG_DELAY_TSLCH_LSB               0
+#define CQSPI_REG_DELAY_TCHSH_LSB               8
+#define CQSPI_REG_DELAY_TSD2D_LSB               16
+#define CQSPI_REG_DELAY_TSHSL_LSB               24
+#define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
+#define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
+#define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
+#define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
+
+#define CQSPI_REG_RD_DATA_CAPTURE               0x10
+#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS        BIT(0)
+#define CQSPI_REG_READCAPTURE_DQS_ENABLE        BIT(8)
+#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB     1
+#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK    0xF
+
+#define CQSPI_REG_SIZE                          0x14
+#define CQSPI_REG_SIZE_ADDRESS_LSB              0
+#define CQSPI_REG_SIZE_PAGE_LSB                 4
+#define CQSPI_REG_SIZE_BLOCK_LSB                16
+#define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
+#define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
+#define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
+
+#define CQSPI_REG_SRAMPARTITION                 0x18
+#define CQSPI_REG_INDIRECTTRIGGER               0x1C
+
+#define CQSPI_REG_REMAP                         0x24
+#define CQSPI_REG_MODE_BIT                      0x28
+
+#define CQSPI_REG_SDRAMLEVEL                    0x2C
+#define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
+#define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
+#define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
+#define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
+
+#define CQSPI_REG_WR_COMPLETION_CTRL		0x38
+#define CQSPI_REG_WR_DISABLE_AUTO_POLL		BIT(14)
+
+#define CQSPI_REG_IRQSTATUS                     0x40
+#define CQSPI_REG_IRQMASK                       0x44
+
+#define CQSPI_REG_INDIRECTRD                    0x60
+#define CQSPI_REG_INDIRECTRD_START              BIT(0)
+#define CQSPI_REG_INDIRECTRD_CANCEL             BIT(1)
+#define CQSPI_REG_INDIRECTRD_INPROGRESS         BIT(2)
+#define CQSPI_REG_INDIRECTRD_DONE               BIT(5)
+
+#define CQSPI_REG_INDIRECTRDWATERMARK           0x64
+#define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
+#define CQSPI_REG_INDIRECTRDBYTES               0x6C
+
+#define CQSPI_REG_CMDCTRL                       0x90
+#define CQSPI_REG_CMDCTRL_EXECUTE               BIT(0)
+#define CQSPI_REG_CMDCTRL_INPROGRESS            BIT(1)
+#define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
+#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
+#define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
+#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
+#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
+#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
+#define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
+#define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
+#define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
+#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
+#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
+#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
+#define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
+
+#define CQSPI_REG_INDIRECTWR                    0x70
+#define CQSPI_REG_INDIRECTWR_START              BIT(0)
+#define CQSPI_REG_INDIRECTWR_CANCEL             BIT(1)
+#define CQSPI_REG_INDIRECTWR_INPROGRESS         BIT(2)
+#define CQSPI_REG_INDIRECTWR_DONE               BIT(5)
+
+#define CQSPI_REG_INDIRECTWRWATERMARK           0x74
+#define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
+#define CQSPI_REG_INDIRECTWRBYTES               0x7C
+
+#define CQSPI_REG_CMDADDRESS                    0x94
+#define CQSPI_REG_CMDREADDATALOWER              0xA0
+#define CQSPI_REG_CMDREADDATAUPPER              0xA4
+#define CQSPI_REG_CMDWRITEDATALOWER             0xA8
+#define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
+
+#define CQSPI_REG_OP_EXT_LOWER                  0xE0
+#define CQSPI_REG_OP_EXT_READ_LSB               24
+#define CQSPI_REG_OP_EXT_WRITE_LSB              16
+#define CQSPI_REG_OP_EXT_STIG_LSB               0
+
+#define CQSPI_REG_PHY_CONFIG                    0xB4
+#define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK     0x40000000
+
+#define CQSPI_DMA_DST_ADDR_REG                  0x1800
+#define CQSPI_DMA_DST_SIZE_REG                  0x1804
+#define CQSPI_DMA_DST_STS_REG                   0x1808
+#define CQSPI_DMA_DST_CTRL_REG                  0x180C
+#define CQSPI_DMA_DST_I_STS_REG                 0x1814
+#define CQSPI_DMA_DST_I_ENBL_REG                0x1818
+#define CQSPI_DMA_DST_I_DISBL_REG               0x181C
+#define CQSPI_DMA_DST_CTRL2_REG                 0x1824
+#define CQSPI_DMA_DST_ADDR_MSB_REG              0x1828
+
+#define CQSPI_DMA_SRC_RD_ADDR_REG               0x1000
+
+#define CQSPI_REG_DMA_PERIPH_CFG                0x20
+#define CQSPI_REG_INDIR_TRIG_ADDR_RANGE         0x80
+#define CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE        6
+#define CQSPI_DFLT_DMA_PERIPH_CFG               0x602
+#define CQSPI_DFLT_DST_CTRL_REG_VAL             0xF43FFA00
+
+#define CQSPI_DMA_DST_I_STS_DONE                BIT(1)
+#define CQSPI_DMA_TIMEOUT                       10000000
+
+#define CQSPI_REG_IS_IDLE(base)				\
+	((readl((base) + CQSPI_REG_CONFIG) >>		\
+	CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
+
+#define CQSPI_GET_RD_SRAM_LEVEL(reg_base)		\
+	(((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >>	\
+	CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
+
+#define CQSPI_GET_WR_SRAM_LEVEL(reg_base)		\
+	(((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >>	\
+	CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
+
 struct cadence_spi_plat {
 	unsigned int	ref_clk_hz;
 	unsigned int	max_hz;
@@ -42,6 +224,7 @@ struct cadence_spi_plat {
 	u8		addr_width;
 	u8		data_width;
 	bool		dtr;
+	bool            is_dma;
 };
 
 struct cadence_spi_priv {
@@ -96,5 +279,11 @@ void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
 void cadence_qspi_apb_readdata_capture(void *reg_base,
 	unsigned int bypass, unsigned int delay);
 unsigned int cm_get_qspi_controller_clk_hz(void);
+int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
+			      const struct spi_mem_op *op);
+int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_plat *plat);
+int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg);
+int cadence_qspi_versal_flash_reset(struct udevice *dev);
+void cadence_qspi_apb_enable_linear_mode(bool enable);
 
 #endif /* __CADENCE_QSPI_H__ */
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 2cdf4c9..c007550 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -38,156 +38,10 @@
 #include <malloc.h>
 #include "cadence_qspi.h"
 
-#define CQSPI_REG_POLL_US			1 /* 1us */
-#define CQSPI_REG_RETRY				10000
-#define CQSPI_POLL_IDLE_RETRY			3
-
-/* Transfer mode */
-#define CQSPI_INST_TYPE_SINGLE			0
-#define CQSPI_INST_TYPE_DUAL			1
-#define CQSPI_INST_TYPE_QUAD			2
-#define CQSPI_INST_TYPE_OCTAL			3
-
-#define CQSPI_STIG_DATA_LEN_MAX			8
-
-#define CQSPI_DUMMY_CLKS_PER_BYTE		8
-#define CQSPI_DUMMY_CLKS_MAX			31
-
-/****************************************************************************
- * Controller's configuration and status register (offset from QSPI_BASE)
- ****************************************************************************/
-#define	CQSPI_REG_CONFIG			0x00
-#define	CQSPI_REG_CONFIG_ENABLE			BIT(0)
-#define	CQSPI_REG_CONFIG_CLK_POL		BIT(1)
-#define	CQSPI_REG_CONFIG_CLK_PHA		BIT(2)
-#define	CQSPI_REG_CONFIG_DIRECT			BIT(7)
-#define	CQSPI_REG_CONFIG_DECODE			BIT(9)
-#define	CQSPI_REG_CONFIG_XIP_IMM		BIT(18)
-#define	CQSPI_REG_CONFIG_CHIPSELECT_LSB		10
-#define	CQSPI_REG_CONFIG_BAUD_LSB		19
-#define CQSPI_REG_CONFIG_DTR_PROTO		BIT(24)
-#define CQSPI_REG_CONFIG_DUAL_OPCODE		BIT(30)
-#define	CQSPI_REG_CONFIG_IDLE_LSB		31
-#define	CQSPI_REG_CONFIG_CHIPSELECT_MASK	0xF
-#define	CQSPI_REG_CONFIG_BAUD_MASK		0xF
-
-#define	CQSPI_REG_RD_INSTR			0x04
-#define	CQSPI_REG_RD_INSTR_OPCODE_LSB		0
-#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB	8
-#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB	12
-#define	CQSPI_REG_RD_INSTR_TYPE_DATA_LSB	16
-#define	CQSPI_REG_RD_INSTR_MODE_EN_LSB		20
-#define	CQSPI_REG_RD_INSTR_DUMMY_LSB		24
-#define	CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK	0x3
-#define	CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK	0x3
-#define	CQSPI_REG_RD_INSTR_TYPE_DATA_MASK	0x3
-#define	CQSPI_REG_RD_INSTR_DUMMY_MASK		0x1F
-
-#define	CQSPI_REG_WR_INSTR			0x08
-#define	CQSPI_REG_WR_INSTR_OPCODE_LSB		0
-#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB	12
-#define	CQSPI_REG_WR_INSTR_TYPE_DATA_LSB	16
-
-#define	CQSPI_REG_DELAY				0x0C
-#define	CQSPI_REG_DELAY_TSLCH_LSB		0
-#define	CQSPI_REG_DELAY_TCHSH_LSB		8
-#define	CQSPI_REG_DELAY_TSD2D_LSB		16
-#define	CQSPI_REG_DELAY_TSHSL_LSB		24
-#define	CQSPI_REG_DELAY_TSLCH_MASK		0xFF
-#define	CQSPI_REG_DELAY_TCHSH_MASK		0xFF
-#define	CQSPI_REG_DELAY_TSD2D_MASK		0xFF
-#define	CQSPI_REG_DELAY_TSHSL_MASK		0xFF
-
-#define	CQSPI_REG_RD_DATA_CAPTURE		0x10
-#define	CQSPI_REG_RD_DATA_CAPTURE_BYPASS	BIT(0)
-#define	CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB	1
-#define	CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK	0xF
-
-#define	CQSPI_REG_SIZE				0x14
-#define	CQSPI_REG_SIZE_ADDRESS_LSB		0
-#define	CQSPI_REG_SIZE_PAGE_LSB			4
-#define	CQSPI_REG_SIZE_BLOCK_LSB		16
-#define	CQSPI_REG_SIZE_ADDRESS_MASK		0xF
-#define	CQSPI_REG_SIZE_PAGE_MASK		0xFFF
-#define	CQSPI_REG_SIZE_BLOCK_MASK		0x3F
-
-#define	CQSPI_REG_SRAMPARTITION			0x18
-#define	CQSPI_REG_INDIRECTTRIGGER		0x1C
-
-#define	CQSPI_REG_REMAP				0x24
-#define	CQSPI_REG_MODE_BIT			0x28
-
-#define	CQSPI_REG_SDRAMLEVEL			0x2C
-#define	CQSPI_REG_SDRAMLEVEL_RD_LSB		0
-#define	CQSPI_REG_SDRAMLEVEL_WR_LSB		16
-#define	CQSPI_REG_SDRAMLEVEL_RD_MASK		0xFFFF
-#define	CQSPI_REG_SDRAMLEVEL_WR_MASK		0xFFFF
-
-#define CQSPI_REG_WR_COMPLETION_CTRL		0x38
-#define CQSPI_REG_WR_DISABLE_AUTO_POLL		BIT(14)
-
-#define	CQSPI_REG_IRQSTATUS			0x40
-#define	CQSPI_REG_IRQMASK			0x44
-
-#define	CQSPI_REG_INDIRECTRD			0x60
-#define	CQSPI_REG_INDIRECTRD_START		BIT(0)
-#define	CQSPI_REG_INDIRECTRD_CANCEL		BIT(1)
-#define	CQSPI_REG_INDIRECTRD_INPROGRESS		BIT(2)
-#define	CQSPI_REG_INDIRECTRD_DONE		BIT(5)
-
-#define	CQSPI_REG_INDIRECTRDWATERMARK		0x64
-#define	CQSPI_REG_INDIRECTRDSTARTADDR		0x68
-#define	CQSPI_REG_INDIRECTRDBYTES		0x6C
-
-#define	CQSPI_REG_CMDCTRL			0x90
-#define	CQSPI_REG_CMDCTRL_EXECUTE		BIT(0)
-#define	CQSPI_REG_CMDCTRL_INPROGRESS		BIT(1)
-#define	CQSPI_REG_CMDCTRL_DUMMY_LSB		7
-#define	CQSPI_REG_CMDCTRL_WR_BYTES_LSB		12
-#define	CQSPI_REG_CMDCTRL_WR_EN_LSB		15
-#define	CQSPI_REG_CMDCTRL_ADD_BYTES_LSB		16
-#define	CQSPI_REG_CMDCTRL_ADDR_EN_LSB		19
-#define	CQSPI_REG_CMDCTRL_RD_BYTES_LSB		20
-#define	CQSPI_REG_CMDCTRL_RD_EN_LSB		23
-#define	CQSPI_REG_CMDCTRL_OPCODE_LSB		24
-#define	CQSPI_REG_CMDCTRL_DUMMY_MASK		0x1F
-#define	CQSPI_REG_CMDCTRL_WR_BYTES_MASK		0x7
-#define	CQSPI_REG_CMDCTRL_ADD_BYTES_MASK	0x3
-#define	CQSPI_REG_CMDCTRL_RD_BYTES_MASK		0x7
-#define	CQSPI_REG_CMDCTRL_OPCODE_MASK		0xFF
-
-#define	CQSPI_REG_INDIRECTWR			0x70
-#define	CQSPI_REG_INDIRECTWR_START		BIT(0)
-#define	CQSPI_REG_INDIRECTWR_CANCEL		BIT(1)
-#define	CQSPI_REG_INDIRECTWR_INPROGRESS		BIT(2)
-#define	CQSPI_REG_INDIRECTWR_DONE		BIT(5)
-
-#define	CQSPI_REG_INDIRECTWRWATERMARK		0x74
-#define	CQSPI_REG_INDIRECTWRSTARTADDR		0x78
-#define	CQSPI_REG_INDIRECTWRBYTES		0x7C
-
-#define	CQSPI_REG_CMDADDRESS			0x94
-#define	CQSPI_REG_CMDREADDATALOWER		0xA0
-#define	CQSPI_REG_CMDREADDATAUPPER		0xA4
-#define	CQSPI_REG_CMDWRITEDATALOWER		0xA8
-#define	CQSPI_REG_CMDWRITEDATAUPPER		0xAC
-
-#define CQSPI_REG_OP_EXT_LOWER			0xE0
-#define CQSPI_REG_OP_EXT_READ_LSB		24
-#define CQSPI_REG_OP_EXT_WRITE_LSB		16
-#define CQSPI_REG_OP_EXT_STIG_LSB		0
-
-#define CQSPI_REG_IS_IDLE(base)					\
-	((readl(base + CQSPI_REG_CONFIG) >>		\
-		CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
-
-#define CQSPI_GET_RD_SRAM_LEVEL(reg_base)			\
-	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
-	CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
-
-#define CQSPI_GET_WR_SRAM_LEVEL(reg_base)			\
-	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
-	CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
+__weak void cadence_qspi_apb_enable_linear_mode(bool enable)
+{
+	return;
+}
 
 void cadence_qspi_apb_controller_enable(void *reg_base)
 {
@@ -487,8 +341,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat)
 	cadence_qspi_apb_controller_enable(plat->regbase);
 }
 
-static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
-	unsigned int reg)
+int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg)
 {
 	unsigned int retry = CQSPI_REG_RETRY;
 
@@ -882,6 +735,9 @@ int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
 	void *buf = op->data.buf.in;
 	size_t len = op->data.nbytes;
 
+	if (CONFIG_IS_ENABLED(ARCH_VERSAL))
+		cadence_qspi_apb_enable_linear_mode(true);
+
 	if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
 		if (len < 256 ||
 		    dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
@@ -1049,6 +905,9 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
 	const void *buf = op->data.buf.out;
 	size_t len = op->data.nbytes;
 
+	if (CONFIG_IS_ENABLED(ARCH_VERSAL))
+		cadence_qspi_apb_enable_linear_mode(true);
+
 	/*
 	 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
 	 * address (all 0s) with the read status register command in DTR mode.
diff --git a/drivers/spi/gxp_spi.c b/drivers/spi/gxp_spi.c
new file mode 100644
index 0000000..70d76ac
--- /dev/null
+++ b/drivers/spi/gxp_spi.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * GXP SPI driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#include <spi.h>
+#include <asm/io.h>
+#include <dm.h>
+
+#define GXP_SPI0_MAX_CHIPSELECT		2
+
+#define MANUAL_MODE	0
+#define AUTO_MODE		1
+#define OFFSET_SPIMCFG	0x00
+#define OFFSET_SPIMCTRL	0x04
+#define OFFSET_SPICMD		0x05
+#define OFFSET_SPIDCNT	0x06
+#define OFFSET_SPIADDR	0x08
+#define OFFSET_SPILDAT	0x40
+#define GXP_SPILDAT_SIZE 64
+
+#define SPIMCTRL_START	0x01
+#define SPIMCTRL_BUSY		0x02
+
+#define CMD_READ_ARRAY_FAST		0x0b
+
+struct gxp_spi_priv {
+	struct spi_slave	slave;
+	void __iomem *base;
+	unsigned int mode;
+
+};
+
+static void spi_set_mode(struct gxp_spi_priv *priv, int mode)
+{
+	unsigned char value;
+
+	value = readb(priv->base + OFFSET_SPIMCTRL);
+	if (mode == MANUAL_MODE) {
+		writeb(0x55, priv->base + OFFSET_SPICMD);
+		writeb(0xaa, priv->base + OFFSET_SPICMD);
+		/* clear bit5 and bit4, auto_start and start_mask */
+		value &= ~(0x03 << 4);
+	} else {
+		value |= (0x03 << 4);
+	}
+	writeb(value, priv->base + OFFSET_SPIMCTRL);
+}
+
+static int gxp_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din,
+			unsigned long flags)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+	unsigned int len = bitlen / 8;
+	unsigned int value;
+	unsigned int addr = 0;
+	unsigned char uchar_out[len];
+	unsigned char *uchar_in = (unsigned char *)din;
+	int read_len;
+	int read_ptr;
+
+	if (dout && din) {
+		/*
+		 * error: gxp spi engin cannot send data to dout and read data from din at the same
+		 * time
+		 */
+		return -1;
+	}
+
+	memset(uchar_out, 0, sizeof(uchar_out));
+	if (dout)
+		memcpy(uchar_out, dout, len);
+
+	if (flags & SPI_XFER_BEGIN) {
+		/* the dout is cmd + addr, cmd=dout[0], add1~3=dout[1~3]. */
+		/* cmd reg */
+		writeb(uchar_out[0], priv->base + OFFSET_SPICMD);
+
+		/* config reg */
+		value = readl(priv->base + OFFSET_SPIMCFG);
+		value &= ~(1 << 24);
+		/* set chipselect */
+		value |= (slave_plat->cs << 24);
+
+		/* addr reg and addr size */
+		if (len >= 4) {
+			addr = uchar_out[1] << 16 | uchar_out[2] << 8 | uchar_out[3];
+			writel(addr, priv->base + OFFSET_SPIADDR);
+			value &= ~(0x07 << 16);
+			/* set the address size to 3 byte */
+			value |= (3 << 16);
+		} else {
+			writel(0, priv->base + OFFSET_SPIADDR);
+			/* set the address size to 0 byte */
+			value &= ~(0x07 << 16);
+		}
+
+		/* dummy */
+		/* clear dummy_cnt to */
+		value &= ~(0x1f << 19);
+		if (uchar_out[0] == CMD_READ_ARRAY_FAST) {
+			/* fast read needs 8 dummy clocks */
+			value |= (8 << 19);
+		}
+
+		writel(value, priv->base + OFFSET_SPIMCFG);
+
+		if (flags & SPI_XFER_END) {
+			/* no data cmd just start it */
+			/* set the data direction bit to 1 */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value |= (1 << 3);
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* set the data byte count */
+			writeb(0, priv->base + OFFSET_SPIDCNT);
+
+			/* set the start bit */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value |= SPIMCTRL_START;
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* wait busy bit is cleared */
+			do {
+				value = readb(priv->base + OFFSET_SPIMCTRL);
+			} while (value & SPIMCTRL_BUSY);
+			return 0;
+		}
+	}
+
+	if (!(flags & SPI_XFER_END) && (flags & SPI_XFER_BEGIN)) {
+		/* first of spi_xfer calls */
+		return 0;
+	}
+
+	/* if dout != null, write data to buf and start transaction */
+	if (dout) {
+		if (len > slave->max_write_size) {
+			printf("SF: write length is too big(>%d)\n", slave->max_write_size);
+			return -1;
+		}
+
+		/* load the data bytes */
+		memcpy((u8 *)priv->base + OFFSET_SPILDAT, dout, len);
+
+		/* write: set the data direction bit to 1 */
+		value = readb(priv->base + OFFSET_SPIMCTRL);
+		value |= (1 << 3);
+		writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+		/* set the data byte count */
+		writeb(len, priv->base + OFFSET_SPIDCNT);
+
+		/* set the start bit */
+		value = readb(priv->base + OFFSET_SPIMCTRL);
+		value |= SPIMCTRL_START;
+		writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+		/* wait busy bit is cleared */
+		do {
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+		} while (value & SPIMCTRL_BUSY);
+
+		return 0;
+	}
+
+	/* if din !=null, start and read data */
+	if (uchar_in) {
+		read_ptr = 0;
+
+		while (read_ptr < len) {
+			read_len = len - read_ptr;
+			if (read_len > GXP_SPILDAT_SIZE)
+				read_len = GXP_SPILDAT_SIZE;
+
+			/* read: set the data direction bit to 0 */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value &= ~(1 << 3);
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* set the data byte count */
+			writeb(read_len, priv->base + OFFSET_SPIDCNT);
+
+			/* set the start bit */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value |= SPIMCTRL_START;
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* wait busy bit is cleared */
+			do {
+				value = readb(priv->base + OFFSET_SPIMCTRL);
+			} while (value & SPIMCTRL_BUSY);
+
+			/* store the data bytes */
+			memcpy(uchar_in + read_ptr, (u8 *)priv->base + OFFSET_SPILDAT, read_len);
+			/* update read_ptr and addr reg */
+			read_ptr += read_len;
+
+			addr = readl(priv->base + OFFSET_SPIADDR);
+			addr += read_len;
+			writel(addr, priv->base + OFFSET_SPIADDR);
+		}
+
+		return 0;
+	}
+	return -2;
+}
+
+static int gxp_spi_set_speed(struct udevice *dev, unsigned int speed)
+{
+	/* Accept any speed */
+	return 0;
+}
+
+static int gxp_spi_set_mode(struct udevice *dev, unsigned int mode)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+
+	priv->mode = mode;
+
+	return 0;
+}
+
+static int gxp_spi_claim_bus(struct udevice *dev)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+	unsigned char cmd;
+
+	spi_set_mode(priv, MANUAL_MODE);
+
+	/* exit 4 bytes addr mode, uboot spi_flash only supports 3 byets address mode */
+	cmd = 0xe9;
+	gxp_spi_xfer(dev, 1 * 8, &cmd, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+	return 0;
+}
+
+static int gxp_spi_release_bus(struct udevice *dev)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+
+	spi_set_mode(priv, AUTO_MODE);
+
+	return 0;
+}
+
+int gxp_spi_cs_info(struct udevice *bus, unsigned int cs, struct spi_cs_info *info)
+{
+	if (cs < GXP_SPI0_MAX_CHIPSELECT)
+		return 0;
+	else
+		return -ENODEV;
+}
+
+static int gxp_spi_probe(struct udevice *bus)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(bus);
+
+	priv->base = dev_read_addr_ptr(bus);
+	if (!priv->base)
+		return -ENOENT;
+
+	return 0;
+}
+
+static int gxp_spi_child_pre_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+
+	slave->max_write_size = GXP_SPILDAT_SIZE;
+
+	return 0;
+}
+
+static const struct dm_spi_ops gxp_spi_ops = {
+	.claim_bus = gxp_spi_claim_bus,
+	.release_bus = gxp_spi_release_bus,
+	.xfer = gxp_spi_xfer,
+	.set_speed = gxp_spi_set_speed,
+	.set_mode = gxp_spi_set_mode,
+	.cs_info = gxp_spi_cs_info,
+};
+
+static const struct udevice_id gxp_spi_ids[] = {
+	{ .compatible = "hpe,gxp-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(gxp_spi) = {
+	.name	= "gxp_spi",
+	.id	= UCLASS_SPI,
+	.of_match = gxp_spi_ids,
+	.ops	= &gxp_spi_ops,
+	.priv_auto = sizeof(struct gxp_spi_priv),
+	.probe	= gxp_spi_probe,
+	.child_pre_probe = gxp_spi_child_pre_probe,
+};
+
diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c
index ea16914..828eab3 100644
--- a/drivers/spi/pl022_spi.c
+++ b/drivers/spi/pl022_spi.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012
- * Armando Visconti, ST Microelectronics, armando.visconti@st.com.
+ * Armando Visconti, STMicroelectronics, armando.visconti@st.com.
  *
  * (C) Copyright 2018
  * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index ce558c4..0cae3df 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -45,8 +45,11 @@
 #define RXF		0x20
 #define RXE		0x24
 #define RXC		0x28
+#define TFES		1
 #define TFLETE		4
+#define TSSRS		6
 #define RFMTE		5
+#define RSSRS		6
 
 #define FAULTF		0x2c
 #define FAULTC		0x30
@@ -170,6 +173,11 @@ static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active)
 			priv->rx_words = 16;
 			read_fifo(priv);
 		}
+
+		/* wait until slave is deselected */
+		while (!(readl(priv->base + TXF) & BIT(TSSRS)) ||
+		       !(readl(priv->base + RXF) & BIT(RSSRS)))
+			;
 	}
 }
 
@@ -275,7 +283,7 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
 {
 	struct udevice *bus = dev->parent;
 	struct synquacer_spi_priv *priv = dev_get_priv(bus);
-	u32 val, words, busy;
+	u32 val, words, busy = 0;
 
 	val = readl(priv->base + FIFOCFG);
 	val |= (1 << RX_FLUSH);
@@ -323,9 +331,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	writel(~0, priv->base + RXC);
 
 	/* Trigger */
-	val = readl(priv->base + DMSTART);
-	val |= BIT(TRIGGER);
-	writel(val, priv->base + DMSTART);
+	if (flags & SPI_XFER_BEGIN) {
+		val = readl(priv->base + DMSTART);
+		val |= BIT(TRIGGER);
+		writel(val, priv->base + DMSTART);
+	}
 
 	while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
 		if (priv->rx_words)
@@ -336,13 +346,10 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		if (priv->tx_words) {
 			write_fifo(priv);
 		} else {
-			u32 len;
-
-			do { /* wait for shifter to empty out */
+			/* wait for shifter to empty out */
+			while (!(readl(priv->base + TXF) & BIT(TFES)))
 				cpu_relax();
-				len = readl(priv->base + DMSTATUS);
-				len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK;
-			} while (tx_buf && len);
+
 			busy &= ~BIT(TXBIT);
 		}
 	}
diff --git a/drivers/tee/optee/rpmb.c b/drivers/tee/optee/rpmb.c
index 0804fc9..cf5e0a0 100644
--- a/drivers/tee/optee/rpmb.c
+++ b/drivers/tee/optee/rpmb.c
@@ -72,6 +72,10 @@ static struct mmc *get_mmc(struct optee_private *priv, int dev_id)
 		debug("Cannot find RPMB device\n");
 		return NULL;
 	}
+	if (mmc_init(mmc)) {
+		log(LOGC_BOARD, LOGL_ERR, "%s:MMC device %d init failed\n", __func__, dev_id);
+		return NULL;
+	}
 	if (!(mmc->version & MMC_VERSION_MMC)) {
 		debug("Device id %d is not an eMMC device\n", dev_id);
 		return NULL;
@@ -104,6 +108,11 @@ static u32 rpmb_get_dev_info(u16 dev_id, struct rpmb_dev_info *info)
 	if (!mmc)
 		return TEE_ERROR_ITEM_NOT_FOUND;
 
+	if (mmc_init(mmc)) {
+		log(LOGC_BOARD, LOGL_ERR, "%s:MMC device %d init failed\n", __func__, dev_id);
+		return TEE_ERROR_NOT_SUPPORTED;
+	}
+
 	if (!mmc->ext_csd)
 		return TEE_ERROR_GENERIC;
 
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56..20b5af7 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -139,6 +139,13 @@ config DESIGNWARE_APB_TIMER
 	  Enables support for the Designware APB Timer driver. This timer is
 	  present on Altera SoCFPGA SoCs.
 
+config GXP_TIMER
+	bool "HPE GXP Timer"
+	depends on TIMER
+	help
+	  Enables support for the GXP Timer driver. This timer is
+	  present on HPE GXP SoCs.
+
 config MPC83XX_TIMER
 	bool "MPC83xx timer support"
 	depends on TIMER
@@ -272,4 +279,13 @@ config IMX_GPT_TIMER
 	  Select this to enable support for the timer found on
 	  NXP i.MX devices.
 
+config XILINX_TIMER
+	bool "Xilinx timer support"
+	depends on TIMER
+	select REGMAP
+	select SPL_REGMAP if SPL
+	help
+	  Select this to enable support for the timer found on
+	  any Xilinx boards (axi timer).
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b2f002d..d9822a5 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
 obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence-ttc.o
 obj-$(CONFIG_DESIGNWARE_APB_TIMER)	+= dw-apb-timer.o
+obj-$(CONFIG_GXP_TIMER)		+= gxp-timer.o
 obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
 obj-$(CONFIG_NOMADIK_MTU_TIMER)	+= nomadik-mtu-timer.o
 obj-$(CONFIG_NPCM_TIMER)        += npcm-timer.o
@@ -27,3 +28,4 @@ obj-$(CONFIG_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_MTK_TIMER)		+= mtk_timer.o
 obj-$(CONFIG_MCHP_PIT64B_TIMER)	+= mchp-pit64b-timer.o
 obj-$(CONFIG_IMX_GPT_TIMER)	+= imx-gpt-timer.o
+obj-$(CONFIG_XILINX_TIMER)	+= xilinx-timer.o
diff --git a/drivers/timer/gxp-timer.c b/drivers/timer/gxp-timer.c
new file mode 100644
index 0000000..6f316bc
--- /dev/null
+++ b/drivers/timer/gxp-timer.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define USTIMELO	0x18
+#define USTIMEHI	0x1C
+
+struct gxp_timer_priv {
+	void __iomem *base;
+};
+
+static u64 gxp_timer_get_count(struct udevice *dev)
+{
+	struct gxp_timer_priv *priv = dev_get_priv(dev);
+	u64 val;
+
+	val = readl(priv->base + USTIMEHI);
+	val = (val << 32) | readl(priv->base + USTIMELO);
+
+	return val;
+}
+
+static int gxp_timer_probe(struct udevice *dev)
+{
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct gxp_timer_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOENT;
+
+	uc_priv->clock_rate = 1000000;
+
+	return 0;
+}
+
+static const struct timer_ops gxp_timer_ops = {
+	.get_count = gxp_timer_get_count,
+};
+
+static const struct udevice_id gxp_timer_ids[] = {
+	{ .compatible = "hpe,gxp-timer" },
+	{}
+};
+
+U_BOOT_DRIVER(gxp_timer) = {
+	.name = "gxp-timer",
+	.id = UCLASS_TIMER,
+	.of_match = gxp_timer_ids,
+	.priv_auto = sizeof(struct gxp_timer_priv),
+	.probe = gxp_timer_probe,
+	.ops = &gxp_timer_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
index 25a6108..aa2e436 100644
--- a/drivers/timer/omap-timer.c
+++ b/drivers/timer/omap-timer.c
@@ -11,6 +11,7 @@
 #include <timer.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/omap_common.h>
 #include <linux/bitops.h>
 
 /* Timer register bits */
@@ -61,13 +62,13 @@ static int omap_timer_probe(struct udevice *dev)
 	if (!uc_priv->clock_rate)
 		uc_priv->clock_rate = V_SCLK;
 
-	uc_priv->clock_rate /= (2 << CONFIG_SYS_PTV);
+	uc_priv->clock_rate /= (2 << SYS_PTV);
 
 	/* start the counter ticking up, reload value on overflow */
 	writel(0, &priv->regs->tldr);
 	writel(0, &priv->regs->tcrr);
 	/* enable timer */
-	writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
+	writel((SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
 	       TCLR_START, &priv->regs->tclr);
 
 	return 0;
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
new file mode 100644
index 0000000..75b4473
--- /dev/null
+++ b/drivers/timer/xilinx-timer.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Advanced Micro Devices, Inc
+ * Michal Simek <michal.simek@amd.com>
+ *
+ * (C) Copyright 2007 Michal Simek
+ * Michal SIMEK <monstr@monstr.eu>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+#include <regmap.h>
+#include <dm/device_compat.h>
+
+#define TIMER_ENABLE_ALL    0x400 /* ENALL */
+#define TIMER_PWM           0x200 /* PWMA0 */
+#define TIMER_INTERRUPT     0x100 /* T0INT */
+#define TIMER_ENABLE        0x080 /* ENT0 */
+#define TIMER_ENABLE_INTR   0x040 /* ENIT0 */
+#define TIMER_RESET         0x020 /* LOAD0 */
+#define TIMER_RELOAD        0x010 /* ARHT0 */
+#define TIMER_EXT_CAPTURE   0x008 /* CAPT0 */
+#define TIMER_EXT_COMPARE   0x004 /* GENT0 */
+#define TIMER_DOWN_COUNT    0x002 /* UDT0 */
+#define TIMER_CAPTURE_MODE  0x001 /* MDT0 */
+
+#define TIMER_CONTROL_OFFSET	0
+#define TIMER_LOADREG_OFFSET	4
+#define TIMER_COUNTER_OFFSET	8
+
+struct xilinx_timer_priv {
+	struct regmap *regs;
+};
+
+static u64 xilinx_timer_get_count(struct udevice *dev)
+{
+	struct xilinx_timer_priv *priv = dev_get_priv(dev);
+	u32 value;
+
+	regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value);
+
+	return value;
+}
+
+static int xilinx_timer_probe(struct udevice *dev)
+{
+	struct xilinx_timer_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	/* uc_priv->clock_rate has already clock rate */
+	ret = regmap_init_mem(dev_ofnode(dev), &priv->regs);
+	if (ret) {
+		dev_dbg(dev, "failed to get regbase of timer\n");
+		return ret;
+	}
+
+	regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0);
+	regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET);
+	regmap_write(priv->regs, TIMER_CONTROL_OFFSET,
+		     TIMER_ENABLE | TIMER_RELOAD);
+
+	return 0;
+}
+
+static const struct timer_ops xilinx_timer_ops = {
+	.get_count = xilinx_timer_get_count,
+};
+
+static const struct udevice_id xilinx_timer_ids[] = {
+	{ .compatible = "xlnx,xps-timer-1.00.a" },
+	{}
+};
+
+U_BOOT_DRIVER(xilinx_timer) = {
+	.name = "xilinx_timer",
+	.id = UCLASS_TIMER,
+	.of_match = xilinx_timer_ids,
+	.priv_auto = sizeof(struct xilinx_timer_priv),
+	.probe = xilinx_timer_probe,
+	.ops = &xilinx_timer_ops,
+};
diff --git a/drivers/usb/common/fsl-dt-fixup.c b/drivers/usb/common/fsl-dt-fixup.c
index 4d7a2ac..00b8cd3 100644
--- a/drivers/usb/common/fsl-dt-fixup.c
+++ b/drivers/usb/common/fsl-dt-fixup.c
@@ -16,10 +16,6 @@
 #include <fsl_usb.h>
 #include <fdt_support.h>
 
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
 /* USB Controllers */
 #define FSL_USB2_MPH	"fsl-usb2-mph"
 #define FSL_USB2_DR	"fsl-usb2-dr"
diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c
index cc80f67..01b2b41 100644
--- a/drivers/usb/emul/sandbox_flash.c
+++ b/drivers/usb/emul/sandbox_flash.c
@@ -228,9 +228,9 @@ static void handle_read(struct sandbox_flash_priv *priv, ulong lba,
 			ulong transfer_len)
 {
 	debug("%s: lba=%lx, transfer_len=%lx\n", __func__, lba, transfer_len);
+	priv->read_len = transfer_len;
 	if (priv->fd != -1) {
 		os_lseek(priv->fd, lba * SANDBOX_FLASH_BLOCK_LEN, OS_SEEK_SET);
-		priv->read_len = transfer_len;
 		setup_response(priv, priv->buff,
 			       transfer_len * SANDBOX_FLASH_BLOCK_LEN);
 	} else {
@@ -336,6 +336,9 @@ static int sandbox_flash_bulk(struct udevice *dev, struct usb_device *udev,
 			if (priv->read_len) {
 				ulong bytes_read;
 
+				if (priv->fd == -1)
+					return -EIO;
+
 				bytes_read = os_read(priv->fd, buff, len);
 				if (bytes_read != len)
 					return -EIO;
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 8c6cf47..da9c9e3 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -93,6 +93,11 @@ config USB_GADGET_DWC2_OTG
 
 if USB_GADGET_DWC2_OTG
 
+config USB_GADGET_DWC2_OTG_PHY
+	bool "DesignWare USB2.0 HS OTG PHY"
+	help
+	  Enable the DesignWare USB2.0 HS OTG physical device interface.
+
 config USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
 	bool "DesignWare USB2.0 HS OTG controller 8-bit PHY bus width"
 	help
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index d5d891b..306dd31 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -37,13 +37,11 @@ ifdef CONFIG_USB_ETHER
 obj-y += ether.o
 obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o
 obj-$(CONFIG_CI_UDC)	+= ci_udc.o
-obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o
 else
 # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
 ifdef CONFIG_USB_DEVICE
 obj-y += core.o
 obj-y += ep0.o
 obj-$(CONFIG_DW_UDC) += designware_udc.o
-obj-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
 endif
 endif
diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c
index 7fc5d27..41a6e8c 100644
--- a/drivers/usb/gadget/designware_udc.c
+++ b/drivers/usb/gadget/designware_udc.c
@@ -4,7 +4,7 @@
  * TI OMAP1510 USB bus interface driver
  *
  * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
  */
 
 #include <common.h>
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 01337d6..bb0d297 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -79,12 +79,6 @@ static int ep_matches(
 				 */
 				if ('s' == tmp[2])	/* == "-iso" */
 					return 0;
-				/* for now, avoid PXA "interrupt-in";
-				 * it's documented as never using DATA1.
-				 */
-				if (gadget_is_pxa(gadget)
-						&& 'i' == tmp[1])
-					return 0;
 				break;
 			case USB_ENDPOINT_XFER_BULK:
 				if ('b' != tmp[1])	/* != "-bulk" */
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 4307328..abb5332 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -1048,13 +1048,6 @@ static int eth_set_config(struct eth_dev *dev, unsigned number,
 	int			result = 0;
 	struct usb_gadget	*gadget = dev->gadget;
 
-	if (gadget_is_sa1100(gadget)
-			&& dev->config
-			&& dev->tx_qlen != 0) {
-		/* tx fifo is full, but we can't clear it...*/
-		pr_err("can't change configurations");
-		return -ESPIPE;
-	}
 	eth_reset_config(dev);
 
 	switch (number) {
@@ -1325,24 +1318,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
 		if (!cdc_active(dev) && wIndex != 0)
 			break;
 
-		/*
-		 * PXA hardware partially handles SET_INTERFACE;
-		 * we need to kluge around that interference.
-		 */
-		if (gadget_is_pxa(gadget)) {
-			value = eth_set_config(dev, DEV_CONFIG_VALUE,
-						GFP_ATOMIC);
-			/*
-			 * PXA25x driver use non-CDC ethernet gadget.
-			 * But only _CDC and _RNDIS code can signalize
-			 * that network is working. So we signalize it
-			 * here.
-			 */
-			dev->network_started = 1;
-			debug("USB network up!\n");
-			goto done_set_intf;
-		}
-
 #ifdef CONFIG_USB_ETH_CDC
 		switch (wIndex) {
 		case 0:		/* control/master intf */
@@ -1386,8 +1361,6 @@ eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
 		 */
 		debug("set_interface ignored!\n");
 #endif /* CONFIG_USB_ETH_CDC */
-
-done_set_intf:
 		break;
 	case USB_REQ_GET_INTERFACE:
 		if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)
@@ -2032,24 +2005,13 @@ static int eth_bind(struct usb_gadget *gadget)
 	 * standard protocol is _strongly_ preferred for interop purposes.
 	 * (By everyone except Microsoft.)
 	 */
-	if (gadget_is_pxa(gadget)) {
-		/* pxa doesn't support altsettings */
-		cdc = 0;
-	} else if (gadget_is_musbhdrc(gadget)) {
+	if (gadget_is_musbhdrc(gadget)) {
 		/* reduce tx dma overhead by avoiding special cases */
 		zlp = 0;
 	} else if (gadget_is_sh(gadget)) {
 		/* sh doesn't support multiple interfaces or configs */
 		cdc = 0;
 		rndis = 0;
-	} else if (gadget_is_sa1100(gadget)) {
-		/* hardware can't write zlps */
-		zlp = 0;
-		/*
-		 * sa1100 CAN do CDC, without status endpoint ... we use
-		 * non-CDC to be compatible with ARM Linux-2.4 "usb-eth".
-		 */
-		cdc = 0;
 	}
 
 	gcnum = usb_gadget_controller_number(gadget);
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 06e6a48..abc6dc7 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -32,12 +32,6 @@
 #define	gadget_is_dummy(g)	0
 #endif
 
-#ifdef CONFIG_USB_GADGET_PXA2XX
-#define	gadget_is_pxa(g)	(!strcmp("pxa2xx_udc", (g)->name))
-#else
-#define	gadget_is_pxa(g)	0
-#endif
-
 #ifdef CONFIG_USB_GADGET_GOKU
 #define	gadget_is_goku(g)	(!strcmp("goku_udc", (g)->name))
 #else
@@ -51,13 +45,6 @@
 #define	gadget_is_sh(g)		0
 #endif
 
-/* not yet stable on 2.6 (would help "original Zaurus") */
-#ifdef CONFIG_USB_GADGET_SA1100
-#define	gadget_is_sa1100(g)	(!strcmp("sa1100_udc", (g)->name))
-#else
-#define	gadget_is_sa1100(g)	0
-#endif
-
 /* handhelds.org tree (?) */
 #ifdef CONFIG_USB_GADGET_MQ11XX
 #define	gadget_is_mq11xx(g)	(!strcmp("mq11xx_udc", (g)->name))
@@ -78,13 +65,6 @@
 #define	gadget_is_n9604(g)	0
 #endif
 
-/* various unstable versions available */
-#ifdef CONFIG_USB_GADGET_PXA27X
-#define	gadget_is_pxa27x(g)	(!strcmp("pxa27x_udc", (g)->name))
-#else
-#define	gadget_is_pxa27x(g)	0
-#endif
-
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 #define gadget_is_atmel_usba(g)	(!strcmp("atmel_usba_udc", (g)->name))
 #else
@@ -194,12 +174,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 		return 0x01;
 	else if (gadget_is_dummy(gadget))
 		return 0x02;
-	else if (gadget_is_pxa(gadget))
-		return 0x03;
 	else if (gadget_is_sh(gadget))
 		return 0x04;
-	else if (gadget_is_sa1100(gadget))
-		return 0x05;
 	else if (gadget_is_goku(gadget))
 		return 0x06;
 	else if (gadget_is_mq11xx(gadget))
@@ -208,8 +184,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 		return 0x08;
 	else if (gadget_is_n9604(gadget))
 		return 0x09;
-	else if (gadget_is_pxa27x(gadget))
-		return 0x10;
 	else if (gadget_is_at91(gadget))
 		return 0x12;
 	else if (gadget_is_imx(gadget))
diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
deleted file mode 100644
index d19ac1d..0000000
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ /dev/null
@@ -1,2049 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
- *
- * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
- * Copyright (C) 2003 Robert Schwebel, Pengutronix
- * Copyright (C) 2003 Benedikt Spranger, Pengutronix
- * Copyright (C) 2003 David Brownell
- * Copyright (C) 2003 Joshua Wise
- * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
- *
- * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
- */
-
-#define CONFIG_USB_PXA25X_SMALL
-#define DRIVER_NAME "pxa25x_udc_linux"
-#define ARCH_HAS_PREFETCH
-
-#include <common.h>
-#include <errno.h>
-#include <log.h>
-#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <asm/unaligned.h>
-#include <dm/devres.h>
-#include <linux/bug.h>
-#include <linux/compat.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/arch/pxa.h>
-#include <linux/delay.h>
-
-#include <linux/usb/ch9.h>
-#include <linux/usb/gadget.h>
-#include <asm/arch/pxa-regs.h>
-
-#include "pxa25x_udc.h"
-
-/*
- * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
- * series processors.  The UDC for the IXP 4xx series is very similar.
- * There are fifteen endpoints, in addition to ep0.
- *
- * Such controller drivers work with a gadget driver.  The gadget driver
- * returns descriptors, implements configuration and data protocols used
- * by the host to interact with this device, and allocates endpoints to
- * the different protocol interfaces.  The controller driver virtualizes
- * usb hardware so that the gadget drivers will be more portable.
- *
- * This UDC hardware wants to implement a bit too much USB protocol, so
- * it constrains the sorts of USB configuration change events that work.
- * The errata for these chips are misleading; some "fixed" bugs from
- * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
- *
- * Note that the UDC hardware supports DMA (except on IXP) but that's
- * not used here.  IN-DMA (to host) is simple enough, when the data is
- * suitably aligned (16 bytes) ... the network stack doesn't do that,
- * other software can.  OUT-DMA is buggy in most chip versions, as well
- * as poorly designed (data toggle not automatic).  So this driver won't
- * bother using DMA.  (Mostly-working IN-DMA support was available in
- * kernels before 2.6.23, but was never enabled or well tested.)
- */
-
-#define DRIVER_VERSION	"18-August-2012"
-#define DRIVER_DESC	"PXA 25x USB Device Controller driver"
-
-static const char driver_name[] = "pxa25x_udc";
-static const char ep0name[] = "ep0";
-
-/* Watchdog */
-static inline void start_watchdog(struct pxa25x_udc *udc)
-{
-	debug("Started watchdog\n");
-	udc->watchdog.base = get_timer(0);
-	udc->watchdog.running = 1;
-}
-
-static inline void stop_watchdog(struct pxa25x_udc *udc)
-{
-	udc->watchdog.running = 0;
-	debug("Stopped watchdog\n");
-}
-
-static inline void test_watchdog(struct pxa25x_udc *udc)
-{
-	if (!udc->watchdog.running)
-		return;
-
-	debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
-		udc->watchdog.period);
-
-	if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
-		stop_watchdog(udc);
-		udc->watchdog.function(udc);
-	}
-}
-
-static void udc_watchdog(struct pxa25x_udc *dev)
-{
-	uint32_t udccs0 = readl(&dev->regs->udccs[0]);
-
-	debug("Fired up udc_watchdog\n");
-
-	local_irq_disable();
-	if (dev->ep0state == EP0_STALL
-			&& (udccs0 & UDCCS0_FST) == 0
-			&& (udccs0 & UDCCS0_SST) == 0) {
-		writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
-		debug("ep0 re-stall\n");
-		start_watchdog(dev);
-	}
-	local_irq_enable();
-}
-
-#ifdef DEBUG
-
-static const char * const state_name[] = {
-	"EP0_IDLE",
-	"EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
-	"EP0_END_XFER", "EP0_STALL"
-};
-
-static void
-dump_udccr(const char *label)
-{
-	u32 udccr = readl(&UDC_REGS->udccr);
-	debug("%s %02X =%s%s%s%s%s%s%s%s\n",
-		label, udccr,
-		(udccr & UDCCR_REM) ? " rem" : "",
-		(udccr & UDCCR_RSTIR) ? " rstir" : "",
-		(udccr & UDCCR_SRM) ? " srm" : "",
-		(udccr & UDCCR_SUSIR) ? " susir" : "",
-		(udccr & UDCCR_RESIR) ? " resir" : "",
-		(udccr & UDCCR_RSM) ? " rsm" : "",
-		(udccr & UDCCR_UDA) ? " uda" : "",
-		(udccr & UDCCR_UDE) ? " ude" : "");
-}
-
-static void
-dump_udccs0(const char *label)
-{
-	u32 udccs0 = readl(&UDC_REGS->udccs[0]);
-
-	debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
-		label, state_name[the_controller->ep0state], udccs0,
-		(udccs0 & UDCCS0_SA) ? " sa" : "",
-		(udccs0 & UDCCS0_RNE) ? " rne" : "",
-		(udccs0 & UDCCS0_FST) ? " fst" : "",
-		(udccs0 & UDCCS0_SST) ? " sst" : "",
-		(udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
-		(udccs0 & UDCCS0_FTF) ? " ftf" : "",
-		(udccs0 & UDCCS0_IPR) ? " ipr" : "",
-		(udccs0 & UDCCS0_OPR) ? " opr" : "");
-}
-
-static void
-dump_state(struct pxa25x_udc *dev)
-{
-	u32 tmp;
-	unsigned i;
-
-	debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
-		state_name[dev->ep0state],
-		readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
-		readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
-		readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
-	dump_udccr("udccr");
-	if (dev->has_cfr) {
-		tmp = readl(&UDC_REGS->udccfr);
-		debug("udccfr %02X =%s%s\n", tmp,
-			(tmp & UDCCFR_AREN) ? " aren" : "",
-			(tmp & UDCCFR_ACM) ? " acm" : "");
-	}
-
-	if (!dev->driver) {
-		debug("no gadget driver bound\n");
-		return;
-	} else
-		debug("ep0 driver '%s'\n", "ether");
-
-	dump_udccs0("udccs0");
-	debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
-		dev->stats.write.bytes, dev->stats.write.ops,
-		dev->stats.read.bytes, dev->stats.read.ops);
-
-	for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
-		if (dev->ep[i].desc == NULL)
-			continue;
-		debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
-	}
-}
-
-#else /* DEBUG */
-
-static inline void dump_udccr(const char *label) { }
-static inline void dump_udccs0(const char *label) { }
-static inline void dump_state(struct pxa25x_udc *dev) { }
-
-#endif /* DEBUG */
-
-/*
- * ---------------------------------------------------------------------------
- *	endpoint related parts of the api to the usb controller hardware,
- *	used by gadget driver; and the inner talker-to-hardware core.
- * ---------------------------------------------------------------------------
- */
-
-static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
-static void nuke(struct pxa25x_ep *, int status);
-
-/* one GPIO should control a D+ pullup, so host sees this device (or not) */
-static void pullup_off(void)
-{
-	struct pxa2xx_udc_mach_info *mach = the_controller->mach;
-
-	if (mach->udc_command)
-		mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
-}
-
-static void pullup_on(void)
-{
-	struct pxa2xx_udc_mach_info *mach = the_controller->mach;
-
-	if (mach->udc_command)
-		mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
-}
-
-static void pio_irq_enable(int bEndpointAddress)
-{
-	bEndpointAddress &= 0xf;
-	if (bEndpointAddress < 8) {
-		clrbits_le32(&the_controller->regs->uicr0,
-			1 << bEndpointAddress);
-	} else {
-		bEndpointAddress -= 8;
-		clrbits_le32(&the_controller->regs->uicr1,
-			1 << bEndpointAddress);
-	}
-}
-
-static void pio_irq_disable(int bEndpointAddress)
-{
-	bEndpointAddress &= 0xf;
-	if (bEndpointAddress < 8) {
-		setbits_le32(&the_controller->regs->uicr0,
-			1 << bEndpointAddress);
-	} else {
-		bEndpointAddress -= 8;
-		setbits_le32(&the_controller->regs->uicr1,
-			1 << bEndpointAddress);
-	}
-}
-
-static inline void udc_set_mask_UDCCR(int mask)
-{
-	/*
-	 * The UDCCR reg contains mask and interrupt status bits,
-	 * so using '|=' isn't safe as it may ack an interrupt.
-	 */
-	const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
-
-	mask &= mask_bits;
-	clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
-}
-
-static inline void udc_clear_mask_UDCCR(int mask)
-{
-	const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
-
-	mask = ~mask & mask_bits;
-	clrbits_le32(&the_controller->regs->udccr, ~mask);
-}
-
-static inline void udc_ack_int_UDCCR(int mask)
-{
-	const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
-
-	mask &= ~mask_bits;
-	clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
-}
-
-/*
- * endpoint enable/disable
- *
- * we need to verify the descriptors used to enable endpoints.  since pxa25x
- * endpoint configurations are fixed, and are pretty much always enabled,
- * there's not a lot to manage here.
- *
- * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
- * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
- * for a single interface (with only the default altsetting) and for gadget
- * drivers that don't halt endpoints (not reset by set_interface).  that also
- * means that if you use ISO, you must violate the USB spec rule that all
- * iso endpoints must be in non-default altsettings.
- */
-static int pxa25x_ep_enable(struct usb_ep *_ep,
-		const struct usb_endpoint_descriptor *desc)
-{
-	struct pxa25x_ep *ep;
-	struct pxa25x_udc *dev;
-
-	ep = container_of(_ep, struct pxa25x_ep, ep);
-	if (!_ep || !desc || ep->desc || _ep->name == ep0name
-			|| desc->bDescriptorType != USB_DT_ENDPOINT
-			|| ep->bEndpointAddress != desc->bEndpointAddress
-			|| ep->fifo_size <
-			   le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
-		printf("%s, bad ep or descriptor\n", __func__);
-		return -EINVAL;
-	}
-
-	/* xfer types must match, except that interrupt ~= bulk */
-	if (ep->bmAttributes != desc->bmAttributes
-			&& ep->bmAttributes != USB_ENDPOINT_XFER_BULK
-			&& desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
-		printf("%s, %s type mismatch\n", __func__, _ep->name);
-		return -EINVAL;
-	}
-
-	/* hardware _could_ do smaller, but driver doesn't */
-	if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
-			&& le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
-						!= BULK_FIFO_SIZE)
-			|| !get_unaligned(&desc->wMaxPacketSize)) {
-		printf("%s, bad %s maxpacket\n", __func__, _ep->name);
-		return -ERANGE;
-	}
-
-	dev = ep->dev;
-	if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
-		printf("%s, bogus device state\n", __func__);
-		return -ESHUTDOWN;
-	}
-
-	ep->desc = desc;
-	ep->stopped = 0;
-	ep->pio_irqs = 0;
-	ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
-
-	/* flush fifo (mostly for OUT buffers) */
-	pxa25x_ep_fifo_flush(_ep);
-
-	/* ... reset halt state too, if we could ... */
-
-	debug("enabled %s\n", _ep->name);
-	return 0;
-}
-
-static int pxa25x_ep_disable(struct usb_ep *_ep)
-{
-	struct pxa25x_ep *ep;
-	unsigned long flags;
-
-	ep = container_of(_ep, struct pxa25x_ep, ep);
-	if (!_ep || !ep->desc) {
-		printf("%s, %s not enabled\n", __func__,
-			_ep ? ep->ep.name : NULL);
-		return -EINVAL;
-	}
-	local_irq_save(flags);
-
-	nuke(ep, -ESHUTDOWN);
-
-	/* flush fifo (mostly for IN buffers) */
-	pxa25x_ep_fifo_flush(_ep);
-
-	ep->desc = NULL;
-	ep->stopped = 1;
-
-	local_irq_restore(flags);
-	debug("%s disabled\n", _ep->name);
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * for the pxa25x, these can just wrap kmalloc/kfree.  gadget drivers
- * must still pass correctly initialized endpoints, since other controller
- * drivers may care about how it's currently set up (dma issues etc).
- */
-
-/*
- *	pxa25x_ep_alloc_request - allocate a request data structure
- */
-static struct usb_request *
-pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
-{
-	struct pxa25x_request *req;
-
-	req = kzalloc(sizeof(*req), gfp_flags);
-	if (!req)
-		return NULL;
-
-	INIT_LIST_HEAD(&req->queue);
-	return &req->req;
-}
-
-
-/*
- *	pxa25x_ep_free_request - deallocate a request data structure
- */
-static void
-pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
-{
-	struct pxa25x_request	*req;
-
-	req = container_of(_req, struct pxa25x_request, req);
-	WARN_ON(!list_empty(&req->queue));
-	kfree(req);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- *	done - retire a request; caller blocked irqs
- */
-static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
-{
-	unsigned stopped = ep->stopped;
-
-	list_del_init(&req->queue);
-
-	if (likely(req->req.status == -EINPROGRESS))
-		req->req.status = status;
-	else
-		status = req->req.status;
-
-	if (status && status != -ESHUTDOWN)
-		debug("complete %s req %p stat %d len %u/%u\n",
-			ep->ep.name, &req->req, status,
-			req->req.actual, req->req.length);
-
-	/* don't modify queue heads during completion callback */
-	ep->stopped = 1;
-	req->req.complete(&ep->ep, &req->req);
-	ep->stopped = stopped;
-}
-
-
-static inline void ep0_idle(struct pxa25x_udc *dev)
-{
-	dev->ep0state = EP0_IDLE;
-}
-
-static int
-write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
-{
-	u8 *buf;
-	unsigned length, count;
-
-	debug("%s(): uddr %p\n", __func__, uddr);
-
-	buf = req->req.buf + req->req.actual;
-	prefetch(buf);
-
-	/* how big will this packet be? */
-	length = min(req->req.length - req->req.actual, max);
-	req->req.actual += length;
-
-	count = length;
-	while (likely(count--))
-		writeb(*buf++, uddr);
-
-	return length;
-}
-
-/*
- * write to an IN endpoint fifo, as many packets as possible.
- * irqs will use this to write the rest later.
- * caller guarantees at least one packet buffer is ready (or a zlp).
- */
-static int
-write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
-{
-	unsigned max;
-
-	max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
-	do {
-		unsigned count;
-		int is_last, is_short;
-
-		count = write_packet(ep->reg_uddr, req, max);
-
-		/* last packet is usually short (or a zlp) */
-		if (unlikely(count != max))
-			is_last = is_short = 1;
-		else {
-			if (likely(req->req.length != req->req.actual)
-					|| req->req.zero)
-				is_last = 0;
-			else
-				is_last = 1;
-			/* interrupt/iso maxpacket may not fill the fifo */
-			is_short = unlikely(max < ep->fifo_size);
-		}
-
-		debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
-			ep->ep.name, count,
-			is_last ? "/L" : "", is_short ? "/S" : "",
-			req->req.length - req->req.actual, req);
-
-		/*
-		 * let loose that packet. maybe try writing another one,
-		 * double buffering might work.  TSP, TPC, and TFS
-		 * bit values are the same for all normal IN endpoints.
-		 */
-		writel(UDCCS_BI_TPC, ep->reg_udccs);
-		if (is_short)
-			writel(UDCCS_BI_TSP, ep->reg_udccs);
-
-		/* requests complete when all IN data is in the FIFO */
-		if (is_last) {
-			done(ep, req, 0);
-			if (list_empty(&ep->queue))
-				pio_irq_disable(ep->bEndpointAddress);
-			return 1;
-		}
-
-		/*
-		 * TODO experiment: how robust can fifo mode tweaking be?
-		 * double buffering is off in the default fifo mode, which
-		 * prevents TFS from being set here.
-		 */
-
-	} while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
-	return 0;
-}
-
-/*
- * caller asserts req->pending (ep0 irq status nyet cleared); starts
- * ep0 data stage.  these chips want very simple state transitions.
- */
-static inline
-void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
-{
-	writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
-	writel(USIR0_IR0, &dev->regs->usir0);
-	dev->req_pending = 0;
-	debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
-		__func__, tag, readl(&dev->regs->udccs[0]), flags,
-		readl(&dev->regs->usir1), readl(&dev->regs->usir0));
-}
-
-static int
-write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
-{
-	unsigned count;
-	int is_short;
-
-	count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
-	ep->dev->stats.write.bytes += count;
-
-	/* last packet "must be" short (or a zlp) */
-	is_short = (count != EP0_FIFO_SIZE);
-
-	debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
-		req->req.length - req->req.actual, req);
-
-	if (unlikely(is_short)) {
-		if (ep->dev->req_pending)
-			ep0start(ep->dev, UDCCS0_IPR, "short IN");
-		else
-			writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
-
-		count = req->req.length;
-		done(ep, req, 0);
-		ep0_idle(ep->dev);
-
-		/*
-		 * This seems to get rid of lost status irqs in some cases:
-		 * host responds quickly, or next request involves config
-		 * change automagic, or should have been hidden, or ...
-		 *
-		 * FIXME get rid of all udelays possible...
-		 */
-		if (count >= EP0_FIFO_SIZE) {
-			count = 100;
-			do {
-				if ((readl(&ep->dev->regs->udccs[0]) &
-				     UDCCS0_OPR) != 0) {
-					/* clear OPR, generate ack */
-					writel(UDCCS0_OPR,
-						&ep->dev->regs->udccs[0]);
-					break;
-				}
-				count--;
-				udelay(1);
-			} while (count);
-		}
-	} else if (ep->dev->req_pending)
-		ep0start(ep->dev, 0, "IN");
-
-	return is_short;
-}
-
-
-/*
- * read_fifo -  unload packet(s) from the fifo we use for usb OUT
- * transfers and put them into the request.  caller should have made
- * sure there's at least one packet ready.
- *
- * returns true if the request completed because of short packet or the
- * request buffer having filled (and maybe overran till end-of-packet).
- */
-static int
-read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
-{
-	u32 udccs;
-	u8 *buf;
-	unsigned bufferspace, count, is_short;
-
-	for (;;) {
-		/*
-		 * make sure there's a packet in the FIFO.
-		 * UDCCS_{BO,IO}_RPC are all the same bit value.
-		 * UDCCS_{BO,IO}_RNE are all the same bit value.
-		 */
-		udccs = readl(ep->reg_udccs);
-		if (unlikely((udccs & UDCCS_BO_RPC) == 0))
-			break;
-		buf = req->req.buf + req->req.actual;
-		prefetchw(buf);
-		bufferspace = req->req.length - req->req.actual;
-
-		/* read all bytes from this packet */
-		if (likely(udccs & UDCCS_BO_RNE)) {
-			count = 1 + (0x0ff & readl(ep->reg_ubcr));
-			req->req.actual += min(count, bufferspace);
-		} else /* zlp */
-			count = 0;
-		is_short = (count < ep->ep.maxpacket);
-		debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
-			ep->ep.name, udccs, count,
-			is_short ? "/S" : "",
-			req, req->req.actual, req->req.length);
-		while (likely(count-- != 0)) {
-			u8 byte = readb(ep->reg_uddr);
-
-			if (unlikely(bufferspace == 0)) {
-				/*
-				 * this happens when the driver's buffer
-				 * is smaller than what the host sent.
-				 * discard the extra data.
-				 */
-				if (req->req.status != -EOVERFLOW)
-					printf("%s overflow %d\n",
-						ep->ep.name, count);
-				req->req.status = -EOVERFLOW;
-			} else {
-				*buf++ = byte;
-				bufferspace--;
-			}
-		}
-		writel(UDCCS_BO_RPC, ep->reg_udccs);
-		/* RPC/RSP/RNE could now reflect the other packet buffer */
-
-		/* iso is one request per packet */
-		if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
-			if (udccs & UDCCS_IO_ROF)
-				req->req.status = -EHOSTUNREACH;
-			/* more like "is_done" */
-			is_short = 1;
-		}
-
-		/* completion */
-		if (is_short || req->req.actual == req->req.length) {
-			done(ep, req, 0);
-			if (list_empty(&ep->queue))
-				pio_irq_disable(ep->bEndpointAddress);
-			return 1;
-		}
-
-		/* finished that packet.  the next one may be waiting... */
-	}
-	return 0;
-}
-
-/*
- * special ep0 version of the above.  no UBCR0 or double buffering; status
- * handshaking is magic.  most device protocols don't need control-OUT.
- * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
- * protocols do use them.
- */
-static int
-read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
-{
-	u8 *buf, byte;
-	unsigned bufferspace;
-
-	buf = req->req.buf + req->req.actual;
-	bufferspace = req->req.length - req->req.actual;
-
-	while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
-		byte = (u8)readb(&ep->dev->regs->uddr0);
-
-		if (unlikely(bufferspace == 0)) {
-			/*
-			 * this happens when the driver's buffer
-			 * is smaller than what the host sent.
-			 * discard the extra data.
-			 */
-			if (req->req.status != -EOVERFLOW)
-				printf("%s overflow\n", ep->ep.name);
-			req->req.status = -EOVERFLOW;
-		} else {
-			*buf++ = byte;
-			req->req.actual++;
-			bufferspace--;
-		}
-	}
-
-	writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
-
-	/* completion */
-	if (req->req.actual >= req->req.length)
-		return 1;
-
-	/* finished that packet.  the next one may be waiting... */
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int
-pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
-{
-	struct pxa25x_request *req;
-	struct pxa25x_ep *ep;
-	struct pxa25x_udc *dev;
-	unsigned long flags;
-
-	req = container_of(_req, struct pxa25x_request, req);
-	if (unlikely(!_req || !_req->complete || !_req->buf
-			|| !list_empty(&req->queue))) {
-		printf("%s, bad params\n", __func__);
-		return -EINVAL;
-	}
-
-	ep = container_of(_ep, struct pxa25x_ep, ep);
-	if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
-		printf("%s, bad ep\n", __func__);
-		return -EINVAL;
-	}
-
-	dev = ep->dev;
-	if (unlikely(!dev->driver
-			|| dev->gadget.speed == USB_SPEED_UNKNOWN)) {
-		printf("%s, bogus device state\n", __func__);
-		return -ESHUTDOWN;
-	}
-
-	/*
-	 * iso is always one packet per request, that's the only way
-	 * we can report per-packet status.  that also helps with dma.
-	 */
-	if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
-			&& req->req.length >
-			le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
-		return -EMSGSIZE;
-
-	debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
-		_ep->name, _req, _req->length, _req->buf);
-
-	local_irq_save(flags);
-
-	_req->status = -EINPROGRESS;
-	_req->actual = 0;
-
-	/* kickstart this i/o queue? */
-	if (list_empty(&ep->queue) && !ep->stopped) {
-		if (ep->desc == NULL/* ep0 */) {
-			unsigned length = _req->length;
-
-			switch (dev->ep0state) {
-			case EP0_IN_DATA_PHASE:
-				dev->stats.write.ops++;
-				if (write_ep0_fifo(ep, req))
-					req = NULL;
-				break;
-
-			case EP0_OUT_DATA_PHASE:
-				dev->stats.read.ops++;
-				/* messy ... */
-				if (dev->req_config) {
-					debug("ep0 config ack%s\n",
-						dev->has_cfr ?  "" : " raced");
-					if (dev->has_cfr)
-						writel(UDCCFR_AREN|UDCCFR_ACM
-							|UDCCFR_MB1,
-							&ep->dev->regs->udccfr);
-					done(ep, req, 0);
-					dev->ep0state = EP0_END_XFER;
-					local_irq_restore(flags);
-					return 0;
-				}
-				if (dev->req_pending)
-					ep0start(dev, UDCCS0_IPR, "OUT");
-				if (length == 0 ||
-						((readl(
-						&ep->dev->regs->udccs[0])
-						& UDCCS0_RNE) != 0
-						&& read_ep0_fifo(ep, req))) {
-					ep0_idle(dev);
-					done(ep, req, 0);
-					req = NULL;
-				}
-				break;
-
-			default:
-				printf("ep0 i/o, odd state %d\n",
-					dev->ep0state);
-				local_irq_restore(flags);
-				return -EL2HLT;
-			}
-		/* can the FIFO can satisfy the request immediately? */
-		} else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
-			if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
-					&& write_fifo(ep, req))
-				req = NULL;
-		} else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
-				&& read_fifo(ep, req)) {
-			req = NULL;
-		}
-
-		if (likely(req && ep->desc))
-			pio_irq_enable(ep->bEndpointAddress);
-	}
-
-	/* pio or dma irq handler advances the queue. */
-	if (likely(req != NULL))
-		list_add_tail(&req->queue, &ep->queue);
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-
-/*
- *	nuke - dequeue ALL requests
- */
-static void nuke(struct pxa25x_ep *ep, int status)
-{
-	struct pxa25x_request *req;
-
-	/* called with irqs blocked */
-	while (!list_empty(&ep->queue)) {
-		req = list_entry(ep->queue.next,
-				struct pxa25x_request,
-				queue);
-		done(ep, req, status);
-	}
-	if (ep->desc)
-		pio_irq_disable(ep->bEndpointAddress);
-}
-
-
-/* dequeue JUST ONE request */
-static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
-{
-	struct pxa25x_ep *ep;
-	struct pxa25x_request *req;
-	unsigned long flags;
-
-	ep = container_of(_ep, struct pxa25x_ep, ep);
-	if (!_ep || ep->ep.name == ep0name)
-		return -EINVAL;
-
-	local_irq_save(flags);
-
-	/* make sure it's actually queued on this endpoint */
-	list_for_each_entry(req, &ep->queue, queue) {
-		if (&req->req == _req)
-			break;
-	}
-	if (&req->req != _req) {
-		local_irq_restore(flags);
-		return -EINVAL;
-	}
-
-	done(ep, req, -ECONNRESET);
-
-	local_irq_restore(flags);
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
-{
-	struct pxa25x_ep *ep;
-	unsigned long flags;
-
-	ep = container_of(_ep, struct pxa25x_ep, ep);
-	if (unlikely(!_ep
-			|| (!ep->desc && ep->ep.name != ep0name))
-			|| ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
-		printf("%s, bad ep\n", __func__);
-		return -EINVAL;
-	}
-	if (value == 0) {
-		/*
-		 * this path (reset toggle+halt) is needed to implement
-		 * SET_INTERFACE on normal hardware.  but it can't be
-		 * done from software on the PXA UDC, and the hardware
-		 * forgets to do it as part of SET_INTERFACE automagic.
-		 */
-		printf("only host can clear %s halt\n", _ep->name);
-		return -EROFS;
-	}
-
-	local_irq_save(flags);
-
-	if ((ep->bEndpointAddress & USB_DIR_IN) != 0
-			&& ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
-			   || !list_empty(&ep->queue))) {
-		local_irq_restore(flags);
-		return -EAGAIN;
-	}
-
-	/* FST bit is the same for control, bulk in, bulk out, interrupt in */
-	writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
-
-	/* ep0 needs special care */
-	if (!ep->desc) {
-		start_watchdog(ep->dev);
-		ep->dev->req_pending = 0;
-		ep->dev->ep0state = EP0_STALL;
-
-	/* and bulk/intr endpoints like dropping stalls too */
-	} else {
-		unsigned i;
-		for (i = 0; i < 1000; i += 20) {
-			if (readl(ep->reg_udccs) & UDCCS_BI_SST)
-				break;
-			udelay(20);
-		}
-	}
-	local_irq_restore(flags);
-
-	debug("%s halt\n", _ep->name);
-	return 0;
-}
-
-static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
-{
-	struct pxa25x_ep        *ep;
-
-	ep = container_of(_ep, struct pxa25x_ep, ep);
-	if (!_ep) {
-		printf("%s, bad ep\n", __func__);
-		return -ENODEV;
-	}
-	/* pxa can't report unclaimed bytes from IN fifos */
-	if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
-		return -EOPNOTSUPP;
-	if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
-			|| (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
-		return 0;
-	else
-		return (readl(ep->reg_ubcr) & 0xfff) + 1;
-}
-
-static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
-{
-	struct pxa25x_ep        *ep;
-
-	ep = container_of(_ep, struct pxa25x_ep, ep);
-	if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
-		printf("%s, bad ep\n", __func__);
-		return;
-	}
-
-	/* toggle and halt bits stay unchanged */
-
-	/* for OUT, just read and discard the FIFO contents. */
-	if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
-		while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
-			(void)readb(ep->reg_uddr);
-		return;
-	}
-
-	/* most IN status is the same, but ISO can't stall */
-	writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
-		| (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
-			? 0 : UDCCS_BI_SST), ep->reg_udccs);
-}
-
-
-static struct usb_ep_ops pxa25x_ep_ops = {
-	.enable		= pxa25x_ep_enable,
-	.disable	= pxa25x_ep_disable,
-
-	.alloc_request	= pxa25x_ep_alloc_request,
-	.free_request	= pxa25x_ep_free_request,
-
-	.queue		= pxa25x_ep_queue,
-	.dequeue	= pxa25x_ep_dequeue,
-
-	.set_halt	= pxa25x_ep_set_halt,
-	.fifo_status	= pxa25x_ep_fifo_status,
-	.fifo_flush	= pxa25x_ep_fifo_flush,
-};
-
-
-/* ---------------------------------------------------------------------------
- *	device-scoped parts of the api to the usb controller hardware
- * ---------------------------------------------------------------------------
- */
-
-static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
-{
-	return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
-		(readl(&the_controller->regs->ufnrl) & 0xff);
-}
-
-static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
-{
-	/* host may not have enabled remote wakeup */
-	if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
-		return -EHOSTUNREACH;
-	udc_set_mask_UDCCR(UDCCR_RSM);
-	return 0;
-}
-
-static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
-static void udc_enable(struct pxa25x_udc *);
-static void udc_disable(struct pxa25x_udc *);
-
-/*
- * We disable the UDC -- and its 48 MHz clock -- whenever it's not
- * in active use.
- */
-static int pullup(struct pxa25x_udc *udc)
-{
-	if (udc->pullup)
-		pullup_on();
-	else
-		pullup_off();
-
-
-	int is_active = udc->pullup;
-	if (is_active) {
-		if (!udc->active) {
-			udc->active = 1;
-			udc_enable(udc);
-		}
-	} else {
-		if (udc->active) {
-			if (udc->gadget.speed != USB_SPEED_UNKNOWN)
-				stop_activity(udc, udc->driver);
-			udc_disable(udc);
-			udc->active = 0;
-		}
-
-	}
-	return 0;
-}
-
-/* VBUS reporting logically comes from a transceiver */
-static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
-{
-	struct pxa25x_udc *udc;
-
-	udc = container_of(_gadget, struct pxa25x_udc, gadget);
-	printf("vbus %s\n", is_active ? "supplied" : "inactive");
-	pullup(udc);
-	return 0;
-}
-
-/* drivers may have software control over D+ pullup */
-static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
-{
-	struct pxa25x_udc	*udc;
-
-	udc = container_of(_gadget, struct pxa25x_udc, gadget);
-
-	/* not all boards support pullup control */
-	if (!udc->mach->udc_command)
-		return -EOPNOTSUPP;
-
-	udc->pullup = (is_active != 0);
-	pullup(udc);
-	return 0;
-}
-
-/*
- * boards may consume current from VBUS, up to 100-500mA based on config.
- * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
- * violate USB specs.
- */
-static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
-{
-	return -EOPNOTSUPP;
-}
-
-static const struct usb_gadget_ops pxa25x_udc_ops = {
-	.get_frame	= pxa25x_udc_get_frame,
-	.wakeup		= pxa25x_udc_wakeup,
-	.vbus_session	= pxa25x_udc_vbus_session,
-	.pullup		= pxa25x_udc_pullup,
-	.vbus_draw	= pxa25x_udc_vbus_draw,
-};
-
-/*-------------------------------------------------------------------------*/
-
-/*
- *	udc_disable - disable USB device controller
- */
-static void udc_disable(struct pxa25x_udc *dev)
-{
-	/* block all irqs */
-	udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
-	writel(0xff, &dev->regs->uicr0);
-	writel(0xff, &dev->regs->uicr1);
-	writel(UFNRH_SIM, &dev->regs->ufnrh);
-
-	/* if hardware supports it, disconnect from usb */
-	pullup_off();
-
-	udc_clear_mask_UDCCR(UDCCR_UDE);
-
-	ep0_idle(dev);
-	dev->gadget.speed = USB_SPEED_UNKNOWN;
-}
-
-/*
- *	udc_reinit - initialize software state
- */
-static void udc_reinit(struct pxa25x_udc *dev)
-{
-	u32 i;
-
-	/* device/ep0 records init */
-	INIT_LIST_HEAD(&dev->gadget.ep_list);
-	INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
-	dev->ep0state = EP0_IDLE;
-
-	/* basic endpoint records init */
-	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
-		struct pxa25x_ep *ep = &dev->ep[i];
-
-		if (i != 0)
-			list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
-
-		ep->desc = NULL;
-		ep->stopped = 0;
-		INIT_LIST_HEAD(&ep->queue);
-		ep->pio_irqs = 0;
-	}
-
-	/* the rest was statically initialized, and is read-only */
-}
-
-/*
- * until it's enabled, this UDC should be completely invisible
- * to any USB host.
- */
-static void udc_enable(struct pxa25x_udc *dev)
-{
-	debug("udc: enabling udc\n");
-
-	udc_clear_mask_UDCCR(UDCCR_UDE);
-
-	/*
-	 * Try to clear these bits before we enable the udc.
-	 * Do not touch reset ack bit, we would take care of it in
-	 * interrupt handle routine
-	 */
-	udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
-
-	ep0_idle(dev);
-	dev->gadget.speed = USB_SPEED_UNKNOWN;
-	dev->stats.irqs = 0;
-
-	/*
-	 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
-	 * - enable UDC
-	 * - if RESET is already in progress, ack interrupt
-	 * - unmask reset interrupt
-	 */
-	udc_set_mask_UDCCR(UDCCR_UDE);
-	if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
-		udc_ack_int_UDCCR(UDCCR_RSTIR);
-
-	if (dev->has_cfr /* UDC_RES2 is defined */) {
-		/*
-		 * pxa255 (a0+) can avoid a set_config race that could
-		 * prevent gadget drivers from configuring correctly
-		 */
-		writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
-	}
-
-	/* enable suspend/resume and reset irqs */
-	udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
-
-	/* enable ep0 irqs */
-	clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
-
-	/* if hardware supports it, pullup D+ and wait for reset */
-	pullup_on();
-}
-
-static inline void clear_ep_state(struct pxa25x_udc *dev)
-{
-	unsigned i;
-
-	/*
-	 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
-	 * fifos, and pending transactions mustn't be continued in any case.
-	 */
-	for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
-		nuke(&dev->ep[i], -ECONNABORTED);
-}
-
-static void handle_ep0(struct pxa25x_udc *dev)
-{
-	u32 udccs0 = readl(&dev->regs->udccs[0]);
-	struct pxa25x_ep *ep = &dev->ep[0];
-	struct pxa25x_request *req;
-	union {
-		struct usb_ctrlrequest	r;
-		u8			raw[8];
-		u32			word[2];
-	} u;
-
-	if (list_empty(&ep->queue))
-		req = NULL;
-	else
-		req = list_entry(ep->queue.next, struct pxa25x_request, queue);
-
-	/* clear stall status */
-	if (udccs0 & UDCCS0_SST) {
-		nuke(ep, -EPIPE);
-		writel(UDCCS0_SST, &dev->regs->udccs[0]);
-		stop_watchdog(dev);
-		ep0_idle(dev);
-	}
-
-	/* previous request unfinished?  non-error iff back-to-back ... */
-	if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
-		nuke(ep, 0);
-		stop_watchdog(dev);
-		ep0_idle(dev);
-	}
-
-	switch (dev->ep0state) {
-	case EP0_IDLE:
-		/* late-breaking status? */
-		udccs0 = readl(&dev->regs->udccs[0]);
-
-		/* start control request? */
-		if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
-				== (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
-			int i;
-
-			nuke(ep, -EPROTO);
-
-			/* read SETUP packet */
-			for (i = 0; i < 8; i++) {
-				if (unlikely(!(readl(&dev->regs->udccs[0]) &
-						UDCCS0_RNE))) {
-bad_setup:
-					debug("SETUP %d!\n", i);
-					goto stall;
-				}
-				u.raw[i] = (u8)readb(&dev->regs->uddr0);
-			}
-			if (unlikely((readl(&dev->regs->udccs[0]) &
-					UDCCS0_RNE) != 0))
-				goto bad_setup;
-
-got_setup:
-			debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
-				u.r.bRequestType, u.r.bRequest,
-				le16_to_cpu(u.r.wValue),
-				le16_to_cpu(u.r.wIndex),
-				le16_to_cpu(u.r.wLength));
-
-			/* cope with automagic for some standard requests. */
-			dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
-						== USB_TYPE_STANDARD;
-			dev->req_config = 0;
-			dev->req_pending = 1;
-			switch (u.r.bRequest) {
-			/* hardware restricts gadget drivers here! */
-			case USB_REQ_SET_CONFIGURATION:
-				debug("GOT SET_CONFIGURATION\n");
-				if (u.r.bRequestType == USB_RECIP_DEVICE) {
-					/*
-					 * reflect hardware's automagic
-					 * up to the gadget driver.
-					 */
-config_change:
-					dev->req_config = 1;
-					clear_ep_state(dev);
-					/*
-					 * if !has_cfr, there's no synch
-					 * else use AREN (later) not SA|OPR
-					 * USIR0_IR0 acts edge sensitive
-					 */
-				}
-				break;
-			/* ... and here, even more ... */
-			case USB_REQ_SET_INTERFACE:
-				if (u.r.bRequestType == USB_RECIP_INTERFACE) {
-					/*
-					 * udc hardware is broken by design:
-					 *  - altsetting may only be zero;
-					 *  - hw resets all interfaces' eps;
-					 *  - ep reset doesn't include halt(?).
-					 */
-					printf("broken set_interface (%d/%d)\n",
-						le16_to_cpu(u.r.wIndex),
-						le16_to_cpu(u.r.wValue));
-					goto config_change;
-				}
-				break;
-			/* hardware was supposed to hide this */
-			case USB_REQ_SET_ADDRESS:
-				debug("GOT SET ADDRESS\n");
-				if (u.r.bRequestType == USB_RECIP_DEVICE) {
-					ep0start(dev, 0, "address");
-					return;
-				}
-				break;
-			}
-
-			if (u.r.bRequestType & USB_DIR_IN)
-				dev->ep0state = EP0_IN_DATA_PHASE;
-			else
-				dev->ep0state = EP0_OUT_DATA_PHASE;
-
-			i = dev->driver->setup(&dev->gadget, &u.r);
-			if (i < 0) {
-				/* hardware automagic preventing STALL... */
-				if (dev->req_config) {
-					/*
-					 * hardware sometimes neglects to tell
-					 * tell us about config change events,
-					 * so later ones may fail...
-					 */
-					printf("config change %02x fail %d?\n",
-						u.r.bRequest, i);
-					return;
-					/*
-					 * TODO experiment:  if has_cfr,
-					 * hardware didn't ACK; maybe we
-					 * could actually STALL!
-					 */
-				}
-				if (0) {
-stall:
-					/* uninitialized when goto stall */
-					i = 0;
-				}
-				debug("protocol STALL, "
-					"%02x err %d\n",
-					readl(&dev->regs->udccs[0]), i);
-
-				/*
-				 * the watchdog timer helps deal with cases
-				 * where udc seems to clear FST wrongly, and
-				 * then NAKs instead of STALLing.
-				 */
-				ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
-				start_watchdog(dev);
-				dev->ep0state = EP0_STALL;
-
-			/* deferred i/o == no response yet */
-			} else if (dev->req_pending) {
-				if (likely(dev->ep0state == EP0_IN_DATA_PHASE
-						|| dev->req_std || u.r.wLength))
-					ep0start(dev, 0, "defer");
-				else
-					ep0start(dev, UDCCS0_IPR, "defer/IPR");
-			}
-
-			/* expect at least one data or status stage irq */
-			return;
-
-		} else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
-				== (UDCCS0_OPR|UDCCS0_SA))) {
-			unsigned i;
-
-			/*
-			 * pxa210/250 erratum 131 for B0/B1 says RNE lies.
-			 * still observed on a pxa255 a0.
-			 */
-			debug("e131\n");
-			nuke(ep, -EPROTO);
-
-			/* read SETUP data, but don't trust it too much */
-			for (i = 0; i < 8; i++)
-				u.raw[i] = (u8)readb(&dev->regs->uddr0);
-			if ((u.r.bRequestType & USB_RECIP_MASK)
-					> USB_RECIP_OTHER)
-				goto stall;
-			if (u.word[0] == 0 && u.word[1] == 0)
-				goto stall;
-			goto got_setup;
-		} else {
-			/*
-			 * some random early IRQ:
-			 * - we acked FST
-			 * - IPR cleared
-			 * - OPR got set, without SA (likely status stage)
-			 */
-			debug("random IRQ %X %X\n", udccs0,
-				readl(&dev->regs->udccs[0]));
-			writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
-				&dev->regs->udccs[0]);
-		}
-		break;
-	case EP0_IN_DATA_PHASE:			/* GET_DESCRIPTOR etc */
-		if (udccs0 & UDCCS0_OPR) {
-			debug("ep0in premature status\n");
-			if (req)
-				done(ep, req, 0);
-			ep0_idle(dev);
-		} else /* irq was IPR clearing */ {
-			if (req) {
-				debug("next ep0 in packet\n");
-				/* this IN packet might finish the request */
-				(void) write_ep0_fifo(ep, req);
-			} /* else IN token before response was written */
-		}
-		break;
-	case EP0_OUT_DATA_PHASE:		/* SET_DESCRIPTOR etc */
-		if (udccs0 & UDCCS0_OPR) {
-			if (req) {
-				/* this OUT packet might finish the request */
-				if (read_ep0_fifo(ep, req))
-					done(ep, req, 0);
-				/* else more OUT packets expected */
-			} /* else OUT token before read was issued */
-		} else /* irq was IPR clearing */ {
-			debug("ep0out premature status\n");
-			if (req)
-				done(ep, req, 0);
-			ep0_idle(dev);
-		}
-		break;
-	case EP0_END_XFER:
-		if (req)
-			done(ep, req, 0);
-		/*
-		 * ack control-IN status (maybe in-zlp was skipped)
-		 * also appears after some config change events.
-		 */
-		if (udccs0 & UDCCS0_OPR)
-			writel(UDCCS0_OPR, &dev->regs->udccs[0]);
-		ep0_idle(dev);
-		break;
-	case EP0_STALL:
-		writel(UDCCS0_FST, &dev->regs->udccs[0]);
-		break;
-	}
-
-	writel(USIR0_IR0, &dev->regs->usir0);
-}
-
-static void handle_ep(struct pxa25x_ep *ep)
-{
-	struct pxa25x_request	*req;
-	int			is_in = ep->bEndpointAddress & USB_DIR_IN;
-	int			completed;
-	u32			udccs, tmp;
-
-	do {
-		completed = 0;
-		if (likely(!list_empty(&ep->queue)))
-			req = list_entry(ep->queue.next,
-					struct pxa25x_request, queue);
-		else
-			req = NULL;
-
-		/* TODO check FST handling */
-
-		udccs = readl(ep->reg_udccs);
-		if (unlikely(is_in)) {	/* irq from TPC, SST, or (ISO) TUR */
-			tmp = UDCCS_BI_TUR;
-			if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
-				tmp |= UDCCS_BI_SST;
-			tmp &= udccs;
-			if (likely(tmp))
-				writel(tmp, ep->reg_udccs);
-			if (req && likely((udccs & UDCCS_BI_TFS) != 0))
-				completed = write_fifo(ep, req);
-
-		} else {	/* irq from RPC (or for ISO, ROF) */
-			if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
-				tmp = UDCCS_BO_SST | UDCCS_BO_DME;
-			else
-				tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
-			tmp &= udccs;
-			if (likely(tmp))
-				writel(tmp, ep->reg_udccs);
-
-			/* fifos can hold packets, ready for reading... */
-			if (likely(req))
-				completed = read_fifo(ep, req);
-			else
-				pio_irq_disable(ep->bEndpointAddress);
-		}
-		ep->pio_irqs++;
-	} while (completed);
-}
-
-/*
- *	pxa25x_udc_irq - interrupt handler
- *
- * avoid delays in ep0 processing. the control handshaking isn't always
- * under software control (pxa250c0 and the pxa255 are better), and delays
- * could cause usb protocol errors.
- */
-static struct pxa25x_udc memory;
-static int
-pxa25x_udc_irq(void)
-{
-	struct pxa25x_udc *dev = &memory;
-	int handled;
-
-	test_watchdog(dev);
-
-	dev->stats.irqs++;
-	do {
-		u32 udccr = readl(&dev->regs->udccr);
-
-		handled = 0;
-
-		/* SUSpend Interrupt Request */
-		if (unlikely(udccr & UDCCR_SUSIR)) {
-			udc_ack_int_UDCCR(UDCCR_SUSIR);
-			handled = 1;
-			debug("USB suspend\n");
-
-			if (dev->gadget.speed != USB_SPEED_UNKNOWN
-					&& dev->driver
-					&& dev->driver->suspend)
-				dev->driver->suspend(&dev->gadget);
-			ep0_idle(dev);
-		}
-
-		/* RESume Interrupt Request */
-		if (unlikely(udccr & UDCCR_RESIR)) {
-			udc_ack_int_UDCCR(UDCCR_RESIR);
-			handled = 1;
-			debug("USB resume\n");
-
-			if (dev->gadget.speed != USB_SPEED_UNKNOWN
-					&& dev->driver
-					&& dev->driver->resume)
-				dev->driver->resume(&dev->gadget);
-		}
-
-		/* ReSeT Interrupt Request - USB reset */
-		if (unlikely(udccr & UDCCR_RSTIR)) {
-			udc_ack_int_UDCCR(UDCCR_RSTIR);
-			handled = 1;
-
-			if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
-				debug("USB reset start\n");
-
-				/*
-				 * reset driver and endpoints,
-				 * in case that's not yet done
-				 */
-				stop_activity(dev, dev->driver);
-
-			} else {
-				debug("USB reset end\n");
-				dev->gadget.speed = USB_SPEED_FULL;
-				memset(&dev->stats, 0, sizeof dev->stats);
-				/* driver and endpoints are still reset */
-			}
-
-		} else {
-			u32 uicr0 = readl(&dev->regs->uicr0);
-			u32 uicr1 = readl(&dev->regs->uicr1);
-			u32 usir0 = readl(&dev->regs->usir0);
-			u32 usir1 = readl(&dev->regs->usir1);
-
-			usir0 = usir0 & ~uicr0;
-			usir1 = usir1 & ~uicr1;
-			int i;
-
-			if (unlikely(!usir0 && !usir1))
-				continue;
-
-			debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
-
-			/* control traffic */
-			if (usir0 & USIR0_IR0) {
-				dev->ep[0].pio_irqs++;
-				handle_ep0(dev);
-				handled = 1;
-			}
-
-			/* endpoint data transfers */
-			for (i = 0; i < 8; i++) {
-				u32	tmp = 1 << i;
-
-				if (i && (usir0 & tmp)) {
-					handle_ep(&dev->ep[i]);
-					setbits_le32(&dev->regs->usir0, tmp);
-					handled = 1;
-				}
-#ifndef	CONFIG_USB_PXA25X_SMALL
-				if (usir1 & tmp) {
-					handle_ep(&dev->ep[i+8]);
-					setbits_le32(&dev->regs->usir1, tmp);
-					handled = 1;
-				}
-#endif
-			}
-		}
-
-		/* we could also ask for 1 msec SOF (SIR) interrupts */
-
-	} while (handled);
-	return IRQ_HANDLED;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * this uses load-time allocation and initialization (instead of
- * doing it at run-time) to save code, eliminate fault paths, and
- * be more obviously correct.
- */
-static struct pxa25x_udc memory = {
-	.regs = UDC_REGS,
-
-	.gadget = {
-		.ops		= &pxa25x_udc_ops,
-		.ep0		= &memory.ep[0].ep,
-		.name		= driver_name,
-	},
-
-	/* control endpoint */
-	.ep[0] = {
-		.ep = {
-			.name		= ep0name,
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= EP0_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.reg_udccs	= &UDC_REGS->udccs[0],
-		.reg_uddr	= &UDC_REGS->uddr0,
-	},
-
-	/* first group of endpoints */
-	.ep[1] = {
-		.ep = {
-			.name		= "ep1in-bulk",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= BULK_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= BULK_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 1,
-		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
-		.reg_udccs	= &UDC_REGS->udccs[1],
-		.reg_uddr	= &UDC_REGS->uddr1,
-	},
-	.ep[2] = {
-		.ep = {
-			.name		= "ep2out-bulk",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= BULK_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= BULK_FIFO_SIZE,
-		.bEndpointAddress = 2,
-		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
-		.reg_udccs	= &UDC_REGS->udccs[2],
-		.reg_ubcr	= &UDC_REGS->ubcr2,
-		.reg_uddr	= &UDC_REGS->uddr2,
-	},
-#ifndef CONFIG_USB_PXA25X_SMALL
-	.ep[3] = {
-		.ep = {
-			.name		= "ep3in-iso",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= ISO_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= ISO_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 3,
-		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
-		.reg_udccs	= &UDC_REGS->udccs[3],
-		.reg_uddr	= &UDC_REGS->uddr3,
-	},
-	.ep[4] = {
-		.ep = {
-			.name		= "ep4out-iso",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= ISO_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= ISO_FIFO_SIZE,
-		.bEndpointAddress = 4,
-		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
-		.reg_udccs	= &UDC_REGS->udccs[4],
-		.reg_ubcr	= &UDC_REGS->ubcr4,
-		.reg_uddr	= &UDC_REGS->uddr4,
-	},
-	.ep[5] = {
-		.ep = {
-			.name		= "ep5in-int",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= INT_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= INT_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 5,
-		.bmAttributes	= USB_ENDPOINT_XFER_INT,
-		.reg_udccs	= &UDC_REGS->udccs[5],
-		.reg_uddr	= &UDC_REGS->uddr5,
-	},
-
-	/* second group of endpoints */
-	.ep[6] = {
-		.ep = {
-			.name		= "ep6in-bulk",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= BULK_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= BULK_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 6,
-		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
-		.reg_udccs	= &UDC_REGS->udccs[6],
-		.reg_uddr	= &UDC_REGS->uddr6,
-	},
-	.ep[7] = {
-		.ep = {
-			.name		= "ep7out-bulk",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= BULK_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= BULK_FIFO_SIZE,
-		.bEndpointAddress = 7,
-		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
-		.reg_udccs	= &UDC_REGS->udccs[7],
-		.reg_ubcr	= &UDC_REGS->ubcr7,
-		.reg_uddr	= &UDC_REGS->uddr7,
-	},
-	.ep[8] = {
-		.ep = {
-			.name		= "ep8in-iso",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= ISO_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= ISO_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 8,
-		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
-		.reg_udccs	= &UDC_REGS->udccs[8],
-		.reg_uddr	= &UDC_REGS->uddr8,
-	},
-	.ep[9] = {
-		.ep = {
-			.name		= "ep9out-iso",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= ISO_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= ISO_FIFO_SIZE,
-		.bEndpointAddress = 9,
-		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
-		.reg_udccs	= &UDC_REGS->udccs[9],
-		.reg_ubcr	= &UDC_REGS->ubcr9,
-		.reg_uddr	= &UDC_REGS->uddr9,
-	},
-	.ep[10] = {
-		.ep = {
-			.name		= "ep10in-int",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= INT_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= INT_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 10,
-		.bmAttributes	= USB_ENDPOINT_XFER_INT,
-		.reg_udccs	= &UDC_REGS->udccs[10],
-		.reg_uddr	= &UDC_REGS->uddr10,
-	},
-
-	/* third group of endpoints */
-	.ep[11] = {
-		.ep = {
-			.name		= "ep11in-bulk",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= BULK_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= BULK_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 11,
-		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
-		.reg_udccs	= &UDC_REGS->udccs[11],
-		.reg_uddr	= &UDC_REGS->uddr11,
-	},
-	.ep[12] = {
-		.ep = {
-			.name		= "ep12out-bulk",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= BULK_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= BULK_FIFO_SIZE,
-		.bEndpointAddress = 12,
-		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
-		.reg_udccs	= &UDC_REGS->udccs[12],
-		.reg_ubcr	= &UDC_REGS->ubcr12,
-		.reg_uddr	= &UDC_REGS->uddr12,
-	},
-	.ep[13] = {
-		.ep = {
-			.name		= "ep13in-iso",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= ISO_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= ISO_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 13,
-		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
-		.reg_udccs	= &UDC_REGS->udccs[13],
-		.reg_uddr	= &UDC_REGS->uddr13,
-	},
-	.ep[14] = {
-		.ep = {
-			.name		= "ep14out-iso",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= ISO_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= ISO_FIFO_SIZE,
-		.bEndpointAddress = 14,
-		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
-		.reg_udccs	= &UDC_REGS->udccs[14],
-		.reg_ubcr	= &UDC_REGS->ubcr14,
-		.reg_uddr	= &UDC_REGS->uddr14,
-	},
-	.ep[15] = {
-		.ep = {
-			.name		= "ep15in-int",
-			.ops		= &pxa25x_ep_ops,
-			.maxpacket	= INT_FIFO_SIZE,
-		},
-		.dev		= &memory,
-		.fifo_size	= INT_FIFO_SIZE,
-		.bEndpointAddress = USB_DIR_IN | 15,
-		.bmAttributes	= USB_ENDPOINT_XFER_INT,
-		.reg_udccs	= &UDC_REGS->udccs[15],
-		.reg_uddr	= &UDC_REGS->uddr15,
-	},
-#endif /* !CONFIG_USB_PXA25X_SMALL */
-};
-
-static void udc_command(int cmd)
-{
-	switch (cmd) {
-	case PXA2XX_UDC_CMD_CONNECT:
-		setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
-			GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
-
-		/* enable pullup */
-		writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
-			GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
-
-		debug("Connected to USB\n");
-		break;
-
-	case PXA2XX_UDC_CMD_DISCONNECT:
-		/* disable pullup resistor */
-		writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
-			GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
-
-		/* setup pin as input, line will float */
-		clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
-			GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
-
-		debug("Disconnected from USB\n");
-		break;
-	}
-}
-
-static struct pxa2xx_udc_mach_info mach_info = {
-	.udc_command = udc_command,
-};
-
-/*
- * when a driver is successfully registered, it will receive
- * control requests including set_configuration(), which enables
- * non-control requests.  then usb traffic follows until a
- * disconnect is reported.  then a host may connect again, or
- * the driver might get unbound.
- */
-int usb_gadget_register_driver(struct usb_gadget_driver *driver)
-{
-	struct pxa25x_udc *dev = &memory;
-	int retval;
-	uint32_t chiprev;
-
-	if (!driver
-			|| driver->speed < USB_SPEED_FULL
-			|| !driver->disconnect
-			|| !driver->setup)
-		return -EINVAL;
-	if (!dev)
-		return -ENODEV;
-	if (dev->driver)
-		return -EBUSY;
-
-	/* Enable clock for usb controller */
-	setbits_le32(CKEN, CKEN11_USB);
-
-	/* first hook up the driver ... */
-	dev->driver = driver;
-	dev->pullup = 1;
-
-	/* trigger chiprev-specific logic */
-	switch ((chiprev = pxa_get_cpu_revision())) {
-	case PXA255_A0:
-		dev->has_cfr = 1;
-		break;
-	case PXA250_A0:
-	case PXA250_A1:
-		/* A0/A1 "not released"; ep 13, 15 unusable */
-		/* fall through */
-	case PXA250_B2: case PXA210_B2:
-	case PXA250_B1: case PXA210_B1:
-	case PXA250_B0: case PXA210_B0:
-		/* OUT-DMA is broken ... */
-		/* fall through */
-	case PXA250_C0: case PXA210_C0:
-		break;
-	default:
-		printf("%s: unrecognized processor: %08x\n",
-			DRIVER_NAME, chiprev);
-		return -ENODEV;
-	}
-
-	the_controller = dev;
-
-	/* prepare watchdog timer */
-	dev->watchdog.running = 0;
-	dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
-	dev->watchdog.function = udc_watchdog;
-
-	dev->mach = &mach_info;
-
-	udc_disable(dev);
-	udc_reinit(dev);
-
-	dev->gadget.name = "pxa2xx_udc";
-	retval = driver->bind(&dev->gadget);
-	if (retval) {
-		printf("bind to driver %s --> error %d\n",
-				DRIVER_NAME, retval);
-		dev->driver = NULL;
-		return retval;
-	}
-
-	/*
-	 * ... then enable host detection and ep0; and we're ready
-	 * for set_configuration as well as eventual disconnect.
-	 */
-	printf("registered gadget driver '%s'\n", DRIVER_NAME);
-
-	pullup(dev);
-	dump_state(dev);
-	return 0;
-}
-
-static void
-stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
-{
-	int i;
-
-	/* don't disconnect drivers more than once */
-	if (dev->gadget.speed == USB_SPEED_UNKNOWN)
-		driver = NULL;
-	dev->gadget.speed = USB_SPEED_UNKNOWN;
-
-	/* prevent new request submissions, kill any outstanding requests  */
-	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
-		struct pxa25x_ep *ep = &dev->ep[i];
-
-		ep->stopped = 1;
-		nuke(ep, -ESHUTDOWN);
-	}
-	stop_watchdog(dev);
-
-	/* report disconnect; the driver is already quiesced */
-	if (driver)
-		driver->disconnect(&dev->gadget);
-
-	/* re-init driver-visible data structures */
-	udc_reinit(dev);
-}
-
-int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
-{
-	struct pxa25x_udc	*dev = the_controller;
-
-	if (!dev)
-		return -ENODEV;
-	if (!driver || driver != dev->driver || !driver->unbind)
-		return -EINVAL;
-
-	local_irq_disable();
-	dev->pullup = 0;
-	pullup(dev);
-	stop_activity(dev, driver);
-	local_irq_enable();
-
-	driver->unbind(&dev->gadget);
-	dev->driver = NULL;
-
-	printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
-	dump_state(dev);
-
-	the_controller = NULL;
-
-	clrbits_le32(CKEN, CKEN11_USB);
-
-	return 0;
-}
-
-extern void udc_disconnect(void)
-{
-	setbits_le32(CKEN, CKEN11_USB);
-	udc_clear_mask_UDCCR(UDCCR_UDE);
-	udc_command(PXA2XX_UDC_CMD_DISCONNECT);
-	clrbits_le32(CKEN, CKEN11_USB);
-}
-
-/*-------------------------------------------------------------------------*/
-
-extern int
-usb_gadget_handle_interrupts(int index)
-{
-	return pxa25x_udc_irq();
-}
diff --git a/drivers/usb/gadget/pxa25x_udc.h b/drivers/usb/gadget/pxa25x_udc.h
deleted file mode 100644
index 7c3882a..0000000
--- a/drivers/usb/gadget/pxa25x_udc.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Intel PXA25x on-chip full speed USB device controller
- *
- * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2003 David Brownell
- * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
- */
-
-#ifndef __LINUX_USB_GADGET_PXA25X_H
-#define __LINUX_USB_GADGET_PXA25X_H
-
-#include <linux/types.h>
-#include <asm/arch/regs-usb.h>
-
-/*
- * Prefetching support - only ARMv5.
- */
-
-#ifdef ARCH_HAS_PREFETCH
-static inline void prefetch(const void *ptr)
-{
-	__asm__ __volatile__(
-		"pld\t%a0"
-		:
-		: "p" (ptr)
-		: "cc");
-}
-
-#define prefetchw(ptr)	prefetch(ptr)
-#endif /* ARCH_HAS_PREFETCH */
-
-/*-------------------------------------------------------------------------*/
-
-#define UDC_REGS	((struct pxa25x_udc_regs *)PXA25X_UDC_BASE)
-
-/*-------------------------------------------------------------------------*/
-
-struct pxa2xx_udc_mach_info {
-	int  (*udc_is_connected)(void);		/* do we see host? */
-	void (*udc_command)(int cmd);
-#define	PXA2XX_UDC_CMD_CONNECT		0	/* let host see us */
-#define	PXA2XX_UDC_CMD_DISCONNECT	1	/* so host won't see us */
-};
-
-struct pxa25x_udc;
-
-struct pxa25x_ep {
-	struct usb_ep				ep;
-	struct pxa25x_udc			*dev;
-
-	const struct usb_endpoint_descriptor	*desc;
-	struct list_head			queue;
-	unsigned long				pio_irqs;
-
-	unsigned short				fifo_size;
-	u8					bEndpointAddress;
-	u8					bmAttributes;
-
-	unsigned				stopped:1;
-
-	/* UDCCS = UDC Control/Status for this EP
-	 * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
-	 * UDDR = UDC Endpoint Data Register (the fifo)
-	 * DRCM = DMA Request Channel Map
-	 */
-	u32					*reg_udccs;
-	u32					*reg_ubcr;
-	u32					*reg_uddr;
-};
-
-struct pxa25x_request {
-	struct usb_request			req;
-	struct list_head			queue;
-};
-
-enum ep0_state {
-	EP0_IDLE,
-	EP0_IN_DATA_PHASE,
-	EP0_OUT_DATA_PHASE,
-	EP0_END_XFER,
-	EP0_STALL,
-};
-
-#define EP0_FIFO_SIZE	16U
-#define BULK_FIFO_SIZE	64U
-#define ISO_FIFO_SIZE	256U
-#define INT_FIFO_SIZE	8U
-
-struct udc_stats {
-	struct ep0stats {
-		unsigned long		ops;
-		unsigned long		bytes;
-	} read, write;
-	unsigned long			irqs;
-};
-
-#ifdef CONFIG_USB_PXA25X_SMALL
-/* when memory's tight, SMALL config saves code+data.  */
-#define	PXA_UDC_NUM_ENDPOINTS	3
-#endif
-
-#ifndef	PXA_UDC_NUM_ENDPOINTS
-#define	PXA_UDC_NUM_ENDPOINTS	16
-#endif
-
-struct pxa25x_watchdog {
-	unsigned				running:1;
-	ulong					period;
-	ulong					base;
-	struct pxa25x_udc			*udc;
-
-	void (*function)(struct pxa25x_udc *udc);
-};
-
-struct pxa25x_udc {
-	struct usb_gadget			gadget;
-	struct usb_gadget_driver		*driver;
-	struct pxa25x_udc_regs			*regs;
-
-	enum ep0_state				ep0state;
-	struct udc_stats			stats;
-	unsigned				got_irq:1,
-						pullup:1,
-						has_cfr:1,
-						req_pending:1,
-						req_std:1,
-						req_config:1,
-						active:1;
-
-	struct clk				*clk;
-	struct pxa2xx_udc_mach_info		*mach;
-	u64					dma_mask;
-	struct pxa25x_ep			ep[PXA_UDC_NUM_ENDPOINTS];
-
-	struct pxa25x_watchdog			watchdog;
-};
-
-/*-------------------------------------------------------------------------*/
-
-static struct pxa25x_udc *the_controller;
-
-/*-------------------------------------------------------------------------*/
-
-#ifndef DEBUG
-# define NOISY 0
-#endif
-
-#endif /* __LINUX_USB_GADGET_PXA25X_H */
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
deleted file mode 100644
index 583ceb4..0000000
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ /dev/null
@@ -1,703 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PXA27x USB device driver for u-boot.
- *
- * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
- * Copyright (C) 2007 Eurotech S.p.A.  <info@eurotech.it>
- * Copyright (C) 2008 Vivek Kutal      <vivek.kutal@azingo.com>
- */
-
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <usbdevice.h>
-#include <linux/delay.h>
-#include <usb/pxa27x_udc.h>
-#include <usb/udc.h>
-
-#include "ep0.h"
-
-/* number of endpoints on this UDC */
-#define UDC_MAX_ENDPOINTS	24
-
-static struct urb *ep0_urb;
-static struct usb_device_instance *udc_device;
-static int ep0state = EP0_IDLE;
-
-#ifdef USBDDBG
-static void udc_dump_buffer(char *name, u8 *buf, int len)
-{
-	usbdbg("%s - buf %p, len %d", name, buf, len);
-	print_buffer(0, buf, 1, len, 0);
-}
-#else
-#define udc_dump_buffer(name, buf, len)		/* void */
-#endif
-
-static inline void udc_ack_int_UDCCR(int mask)
-{
-	writel(readl(USIR1) | mask, USIR1);
-}
-
-/*
- * If the endpoint has an active tx_urb, then the next packet of data from the
- * URB is written to the tx FIFO.
- * The total amount of data in the urb is given by urb->actual_length.
- * The maximum amount of data that can be sent in any one packet is given by
- * endpoint->tx_packetSize.
- * The number of data bytes from this URB that have already been transmitted
- * is given by endpoint->sent.
- * endpoint->last is updated by this routine with the number of data bytes
- * transmitted in this packet.
- */
-static int udc_write_urb(struct usb_endpoint_instance *endpoint)
-{
-	struct urb *urb = endpoint->tx_urb;
-	int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK;
-	u32 *data32 = (u32 *) urb->buffer;
-	u8  *data8 = (u8 *) urb->buffer;
-	unsigned int i, n, w, b, is_short;
-	int timeout = 2000;	/* 2ms */
-
-	if (!urb || !urb->actual_length)
-		return -1;
-
-	n = min_t(unsigned int, urb->actual_length - endpoint->sent,
-		  endpoint->tx_packetSize);
-	if (n <= 0)
-		return -1;
-
-	usbdbg("write urb on ep %d", ep_num);
-#if defined(USBDDBG) && defined(USBDPARANOIA)
-	usbdbg("urb: buf %p, buf_len %d, actual_len %d",
-		urb->buffer, urb->buffer_length, urb->actual_length);
-	usbdbg("endpoint: sent %d, tx_packetSize %d, last %d",
-		endpoint->sent, endpoint->tx_packetSize, endpoint->last);
-#endif
-
-	is_short = n != endpoint->tx_packetSize;
-	w = n / 4;
-	b = n % 4;
-	usbdbg("n %d%s w %d b %d", n, is_short ? "-s" : "", w, b);
-	udc_dump_buffer("urb write", data8 + endpoint->sent, n);
-
-	/* Prepare for data send */
-	if (ep_num)
-		writel(UDCCSR_PC ,UDCCSN(ep_num));
-
-	for (i = 0; i < w; i++)
-		  writel(data32[endpoint->sent / 4 + i], UDCDN(ep_num));
-
-	for (i = 0; i < b; i++)
-		  writeb(data8[endpoint->sent + w * 4 + i], UDCDN(ep_num));
-
-	/* Set "Packet Complete" if less data then tx_packetSize */
-	if (is_short)
-		writel(ep_num ? UDCCSR_SP : UDCCSR0_IPR, UDCCSN(ep_num));
-
-	/* Wait for data sent */
-	if (ep_num) {
-		while (!(readl(UDCCSN(ep_num)) & UDCCSR_PC)) {
-			if (timeout-- == 0)
-				return -1;
-			else
-				udelay(1);
-		}
-	}
-
-	endpoint->last = n;
-
-	if (ep_num) {
-		usbd_tx_complete(endpoint);
-	} else {
-		endpoint->sent += n;
-		endpoint->last -= n;
-	}
-
-	if (endpoint->sent >= urb->actual_length) {
-		urb->actual_length = 0;
-		endpoint->sent = 0;
-		endpoint->last = 0;
-	}
-
-	if ((endpoint->sent >= urb->actual_length) && (!ep_num)) {
-		usbdbg("ep0 IN stage done");
-		if (is_short)
-			ep0state = EP0_IDLE;
-		else
-			ep0state = EP0_XFER_COMPLETE;
-	}
-
-	return 0;
-}
-
-static int udc_read_urb(struct usb_endpoint_instance *endpoint)
-{
-	struct urb *urb = endpoint->rcv_urb;
-	int ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK;
-	u32 *data32 = (u32 *) urb->buffer;
-	unsigned int i, n;
-
-	usbdbg("read urb on ep %d", ep_num);
-#if defined(USBDDBG) && defined(USBDPARANOIA)
-	usbdbg("urb: buf %p, buf_len %d, actual_len %d",
-		urb->buffer, urb->buffer_length, urb->actual_length);
-	usbdbg("endpoint: rcv_packetSize %d",
-		endpoint->rcv_packetSize);
-#endif
-
-	if (readl(UDCCSN(ep_num)) & UDCCSR_BNE)
-		n = readl(UDCBCN(ep_num)) & 0x3ff;
-	else /* zlp */
-		n = 0;
-
-	usbdbg("n %d%s", n, n != endpoint->rcv_packetSize ? "-s" : "");
-	for (i = 0; i < n; i += 4)
-		data32[urb->actual_length / 4 + i / 4] = readl(UDCDN(ep_num));
-
-	udc_dump_buffer("urb read", (u8 *) data32, urb->actual_length + n);
-	usbd_rcv_complete(endpoint, n, 0);
-
-	return 0;
-}
-
-static int udc_read_urb_ep0(void)
-{
-	u32 *data32 = (u32 *) ep0_urb->buffer;
-	u8 *data8 = (u8 *) ep0_urb->buffer;
-	unsigned int i, n, w, b;
-
-	usbdbg("read urb on ep 0");
-#if defined(USBDDBG) && defined(USBDPARANOIA)
-	usbdbg("urb: buf %p, buf_len %d, actual_len %d",
-		ep0_urb->buffer, ep0_urb->buffer_length, ep0_urb->actual_length);
-#endif
-
-	n = readl(UDCBCR0);
-	w = n / 4;
-	b = n % 4;
-
-	for (i = 0; i < w; i++) {
-		data32[ep0_urb->actual_length / 4 + i] = readl(UDCDN(0));
-		/* ep0_urb->actual_length += 4; */
-	}
-
-	for (i = 0; i < b; i++) {
-		data8[ep0_urb->actual_length + w * 4 + i] = readb(UDCDN(0));
-		/* ep0_urb->actual_length++; */
-	}
-
-	ep0_urb->actual_length += n;
-
-	udc_dump_buffer("urb read", (u8 *) data32, ep0_urb->actual_length);
-
-	writel(UDCCSR0_OPC | UDCCSR0_IPR, UDCCSR0);
-	if (ep0_urb->actual_length == ep0_urb->device_request.wLength)
-		return 1;
-
-	return 0;
-}
-
-static void udc_handle_ep0(struct usb_endpoint_instance *endpoint)
-{
-	u32 udccsr0 = readl(UDCCSR0);
-	u32 *data = (u32 *) &ep0_urb->device_request;
-	int i;
-
-	usbdbg("udccsr0 %x", udccsr0);
-
-	/* Clear stall status */
-	if (udccsr0 & UDCCSR0_SST) {
-		usberr("clear stall status");
-		writel(UDCCSR0_SST, UDCCSR0);
-		ep0state = EP0_IDLE;
-	}
-
-	/* previous request unfinished?  non-error iff back-to-back ... */
-	if ((udccsr0 & UDCCSR0_SA) != 0 && ep0state != EP0_IDLE)
-		ep0state = EP0_IDLE;
-
-	switch (ep0state) {
-
-	case EP0_IDLE:
-		udccsr0 = readl(UDCCSR0);
-		/* Start control request? */
-		if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE))
-			== (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)) {
-
-			/* Read SETUP packet.
-			 * SETUP packet size is 8 bytes (aka 2 words)
-			 */
-			usbdbg("try reading SETUP packet");
-			for (i = 0; i < 2; i++) {
-				if ((readl(UDCCSR0) & UDCCSR0_RNE) == 0) {
-					usberr("setup packet too short:%d", i);
-					goto stall;
-				}
-				data[i] = readl(UDCDR0);
-			}
-
-			writel(readl(UDCCSR0) | UDCCSR0_OPC | UDCCSR0_SA, UDCCSR0);
-			if ((readl(UDCCSR0) & UDCCSR0_RNE) != 0) {
-				usberr("setup packet too long");
-				goto stall;
-			}
-
-			udc_dump_buffer("ep0 setup read", (u8 *) data, 8);
-
-			if (ep0_urb->device_request.wLength == 0) {
-				usbdbg("Zero Data control Packet\n");
-				if (ep0_recv_setup(ep0_urb)) {
-					usberr("Invalid Setup Packet\n");
-					udc_dump_buffer("ep0 setup read",
-								(u8 *)data, 8);
-					goto stall;
-				}
-				writel(UDCCSR0_IPR, UDCCSR0);
-				ep0state = EP0_IDLE;
-			} else {
-				/* Check direction */
-				if ((ep0_urb->device_request.bmRequestType &
-						USB_REQ_DIRECTION_MASK)
-						== USB_REQ_HOST2DEVICE) {
-					ep0state = EP0_OUT_DATA;
-					ep0_urb->buffer =
-						(u8 *)ep0_urb->buffer_data;
-					ep0_urb->buffer_length =
-						sizeof(ep0_urb->buffer_data);
-					ep0_urb->actual_length = 0;
-					writel(UDCCSR0_IPR, UDCCSR0);
-				} else {
-					/* The ep0_recv_setup function has
-					 * already placed our response packet
-					 * data in ep0_urb->buffer and the
-					 * packet length in
-					 * ep0_urb->actual_length.
-					 */
-					if (ep0_recv_setup(ep0_urb)) {
-stall:
-						usberr("Invalid setup packet");
-						udc_dump_buffer("ep0 setup read"
-							, (u8 *) data, 8);
-						ep0state = EP0_IDLE;
-
-						writel(UDCCSR0_SA |
-						UDCCSR0_OPC | UDCCSR0_FST |
-						UDCCS0_FTF, UDCCSR0);
-
-						return;
-					}
-
-					endpoint->tx_urb = ep0_urb;
-					endpoint->sent = 0;
-					usbdbg("EP0_IN_DATA");
-					ep0state = EP0_IN_DATA;
-					if (udc_write_urb(endpoint) < 0)
-						goto stall;
-
-				}
-			}
-			return;
-		} else if ((udccsr0 & (UDCCSR0_OPC | UDCCSR0_SA))
-			== (UDCCSR0_OPC|UDCCSR0_SA)) {
-			usberr("Setup Active but no data. Stalling ....\n");
-			goto stall;
-		} else {
-			usbdbg("random early IRQs");
-			/* Some random early IRQs:
-			 * - we acked FST
-			 * - IPR cleared
-			 * - OPC got set, without SA (likely status stage)
-			 */
-			writel(udccsr0 & (UDCCSR0_SA | UDCCSR0_OPC), UDCCSR0);
-		}
-		break;
-
-	case EP0_OUT_DATA:
-
-		if ((udccsr0 & UDCCSR0_OPC) && !(udccsr0 & UDCCSR0_SA)) {
-			if (udc_read_urb_ep0()) {
-read_complete:
-				ep0state = EP0_IDLE;
-				if (ep0_recv_setup(ep0_urb)) {
-					/* Not a setup packet, stall next
-					 * EP0 transaction
-					 */
-					udc_dump_buffer("ep0 setup read",
-							(u8 *) data, 8);
-					usberr("can't parse setup packet\n");
-					goto stall;
-				}
-			}
-		} else if (!(udccsr0 & UDCCSR0_OPC) &&
-				!(udccsr0 & UDCCSR0_IPR)) {
-			if (ep0_urb->device_request.wLength ==
-				ep0_urb->actual_length)
-				goto read_complete;
-
-			usberr("Premature Status\n");
-			ep0state = EP0_IDLE;
-		}
-		break;
-
-	case EP0_IN_DATA:
-		/* GET_DESCRIPTOR etc */
-		if (udccsr0 & UDCCSR0_OPC) {
-			writel(UDCCSR0_OPC | UDCCSR0_FTF, UDCCSR0);
-			usberr("ep0in premature status");
-			ep0state = EP0_IDLE;
-		} else {
-			/* irq was IPR clearing */
-			if (udc_write_urb(endpoint) < 0) {
-				usberr("ep0_write_error\n");
-				goto stall;
-			}
-		}
-		break;
-
-	case EP0_XFER_COMPLETE:
-		writel(UDCCSR0_IPR, UDCCSR0);
-		ep0state = EP0_IDLE;
-		break;
-
-	default:
-		usbdbg("Default\n");
-	}
-	writel(USIR0_IR0, USIR0);
-}
-
-static void udc_handle_ep(struct usb_endpoint_instance *endpoint)
-{
-	int ep_addr = endpoint->endpoint_address;
-	int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
-	int ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT;
-
-	u32 flags = readl(UDCCSN(ep_num)) & (UDCCSR_SST | UDCCSR_TRN);
-	if (flags)
-		writel(flags, UDCCSN(ep_num));
-
-	if (ep_isout)
-		udc_read_urb(endpoint);
-	else
-		udc_write_urb(endpoint);
-
-	writel(UDCCSR_PC, UDCCSN(ep_num));
-}
-
-static void udc_state_changed(void)
-{
-
-	writel(readl(UDCCR) | UDCCR_SMAC, UDCCR);
-
-	usbdbg("New UDC settings are: conf %d - inter %d - alter %d",
-	       (readl(UDCCR) & UDCCR_ACN) >> UDCCR_ACN_S,
-	       (readl(UDCCR) & UDCCR_AIN) >> UDCCR_AIN_S,
-	       (readl(UDCCR) & UDCCR_AAISN) >> UDCCR_AAISN_S);
-
-	usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
-	writel(UDCISR1_IRCC, UDCISR1);
-}
-
-void udc_irq(void)
-{
-	int handled;
-	struct usb_endpoint_instance *endpoint;
-	int ep_num, i;
-	u32 udcisr0;
-
-	do {
-		handled = 0;
-		/* Suspend Interrupt Request */
-		if (readl(USIR1) & UDCCR_SUSIR) {
-			usbdbg("Suspend\n");
-			udc_ack_int_UDCCR(UDCCR_SUSIR);
-			handled = 1;
-			ep0state = EP0_IDLE;
-		}
-
-		/* Resume Interrupt Request */
-		if (readl(USIR1) & UDCCR_RESIR) {
-			udc_ack_int_UDCCR(UDCCR_RESIR);
-			handled = 1;
-			usbdbg("USB resume\n");
-		}
-
-		if (readl(USIR1) & (1<<31)) {
-			handled = 1;
-			udc_state_changed();
-		}
-
-		/* Reset Interrupt Request */
-		if (readl(USIR1) & UDCCR_RSTIR) {
-			udc_ack_int_UDCCR(UDCCR_RSTIR);
-			handled = 1;
-			usbdbg("Reset\n");
-			usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
-		} else {
-			if (readl(USIR0))
-				usbdbg("UISR0: %x \n", readl(USIR0));
-
-			if (readl(USIR0) & 0x2)
-				writel(0x2, USIR0);
-
-			/* Control traffic */
-			if (readl(USIR0)  & USIR0_IR0) {
-				handled = 1;
-				writel(USIR0_IR0, USIR0);
-				udc_handle_ep0(udc_device->bus->endpoint_array);
-			}
-
-			endpoint = udc_device->bus->endpoint_array;
-			for (i = 0; i < udc_device->bus->max_endpoints; i++) {
-				ep_num = (endpoint[i].endpoint_address) &
-						USB_ENDPOINT_NUMBER_MASK;
-				if (!ep_num)
-					continue;
-				udcisr0 = readl(UDCISR0);
-				if (udcisr0 &
-					UDCISR_INT(ep_num, UDC_INT_PACKETCMP)) {
-					writel(UDCISR_INT(ep_num, UDC_INT_PACKETCMP),
-					       UDCISR0);
-					udc_handle_ep(&endpoint[i]);
-				}
-			}
-		}
-
-	} while (handled);
-}
-
-/* The UDCCR reg contains mask and interrupt status bits,
- * so using '|=' isn't safe as it may ack an interrupt.
- */
-#define UDCCR_OEN		(1 << 31)   /* On-the-Go Enable */
-#define UDCCR_MASK_BITS		(UDCCR_OEN | UDCCR_UDE)
-
-static inline void udc_set_mask_UDCCR(int mask)
-{
-    writel((readl(UDCCR) & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR);
-}
-
-static inline void udc_clear_mask_UDCCR(int mask)
-{
-    writel((readl(UDCCR) & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR);
-}
-
-static void pio_irq_enable(int ep_num)
-{
-	if (ep_num < 16)
-		writel(readl(UDCICR0) | 3 << (ep_num * 2), UDCICR0);
-	else {
-		ep_num -= 16;
-		writel(readl(UDCICR1) | 3 << (ep_num * 2), UDCICR1);
-	}
-}
-
-/*
- * udc_set_nak
- *
- * Allow upper layers to signal lower layers should not accept more RX data
- */
-void udc_set_nak(int ep_num)
-{
-	/* TODO */
-}
-
-/*
- * udc_unset_nak
- *
- * Suspend sending of NAK tokens for DATA OUT tokens on a given endpoint.
- * Switch off NAKing on this endpoint to accept more data output from host.
- */
-void udc_unset_nak(int ep_num)
-{
-	/* TODO */
-}
-
-int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
-{
-	return udc_write_urb(endpoint);
-}
-
-/* Associate a physical endpoint with endpoint instance */
-void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
-				struct usb_endpoint_instance *endpoint)
-{
-	int ep_num, ep_addr, ep_isout, ep_type, ep_size;
-	int config, interface, alternate;
-	u32 tmp;
-
-	usbdbg("setting up endpoint id %d", id);
-
-	if (!endpoint) {
-		usberr("endpoint void!");
-		return;
-	}
-
-	ep_num = endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK;
-	if (ep_num >= UDC_MAX_ENDPOINTS) {
-		usberr("unable to setup ep %d!", ep_num);
-		return;
-	}
-
-	pio_irq_enable(ep_num);
-	if (ep_num == 0) {
-		/* Done for ep0 */
-		return;
-	}
-
-	config = 1;
-	interface = 0;
-	alternate = 0;
-
-	usbdbg("config %d - interface %d - alternate %d",
-		config, interface, alternate);
-
-	ep_addr = endpoint->endpoint_address;
-	ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
-	ep_isout = (ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT;
-	ep_type = ep_isout ? endpoint->rcv_attributes : endpoint->tx_attributes;
-	ep_size = ep_isout ? endpoint->rcv_packetSize : endpoint->tx_packetSize;
-
-	usbdbg("addr %x, num %d, dir %s, type %s, packet size %d",
-		ep_addr, ep_num,
-		ep_isout ? "out" : "in",
-		ep_type == USB_ENDPOINT_XFER_ISOC ? "isoc" :
-		ep_type == USB_ENDPOINT_XFER_BULK ? "bulk" :
-		ep_type == USB_ENDPOINT_XFER_INT ? "int" : "???",
-		ep_size
-		);
-
-	/* Configure UDCCRx */
-	tmp = 0;
-	tmp |= (config << UDCCONR_CN_S) & UDCCONR_CN;
-	tmp |= (interface << UDCCONR_IN_S) & UDCCONR_IN;
-	tmp |= (alternate << UDCCONR_AISN_S) & UDCCONR_AISN;
-	tmp |= (ep_num << UDCCONR_EN_S) & UDCCONR_EN;
-	tmp |= (ep_type << UDCCONR_ET_S) & UDCCONR_ET;
-	tmp |= ep_isout ? 0 : UDCCONR_ED;
-	tmp |= (ep_size << UDCCONR_MPS_S) & UDCCONR_MPS;
-	tmp |= UDCCONR_EE;
-
-	writel(tmp, UDCCN(ep_num));
-
-	usbdbg("UDCCR%c = %x", 'A' + ep_num-1, readl(UDCCN(ep_num)));
-	usbdbg("UDCCSR%c = %x", 'A' + ep_num-1, readl(UDCCSN(ep_num)));
-}
-
-/* Connect the USB device to the bus */
-void udc_connect(void)
-{
-	usbdbg("UDC connect");
-
-#ifdef CONFIG_USB_DEV_PULLUP_GPIO
-	/* Turn on the USB connection by enabling the pullup resistor */
-	writel(readl(GPDR(CONFIG_USB_DEV_PULLUP_GPIO))
-		     | GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
-	       GPDR(CONFIG_USB_DEV_PULLUP_GPIO));
-	writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
-#else
-	/* Host port 2 transceiver D+ pull up enable */
-	writel(readl(UP2OCR) | UP2OCR_DPPUE, UP2OCR);
-#endif
-}
-
-/* Disconnect the USB device to the bus */
-void udc_disconnect(void)
-{
-	usbdbg("UDC disconnect");
-
-#ifdef CONFIG_USB_DEV_PULLUP_GPIO
-	/* Turn off the USB connection by disabling the pullup resistor */
-	writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO), GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
-#else
-	/* Host port 2 transceiver D+ pull up disable */
-	writel(readl(UP2OCR) & ~UP2OCR_DPPUE, UP2OCR);
-#endif
-}
-
-/* Switch on the UDC */
-void udc_enable(struct usb_device_instance *device)
-{
-
-	ep0state = EP0_IDLE;
-
-	/* enable endpoint 0, A, B's Packet Complete Interrupt. */
-	writel(0xffffffff, UDCICR0);
-	writel(0xa8000000, UDCICR1);
-
-	/* clear the interrupt status/control registers */
-	writel(0xffffffff, UDCISR0);
-	writel(0xffffffff, UDCISR1);
-
-	/* set UDC-enable */
-	udc_set_mask_UDCCR(UDCCR_UDE);
-
-	udc_device = device;
-	if (!ep0_urb)
-		ep0_urb = usbd_alloc_urb(udc_device,
-				udc_device->bus->endpoint_array);
-	else
-		usbinfo("ep0_urb %p already allocated", ep0_urb);
-
-	usbdbg("UDC Enabled\n");
-}
-
-/* Need to check this again */
-void udc_disable(void)
-{
-	usbdbg("disable UDC");
-
-	udc_clear_mask_UDCCR(UDCCR_UDE);
-
-	/* Disable clock for USB device */
-	writel(readl(CKEN) & ~CKEN11_USB, CKEN);
-
-	/* Free ep0 URB */
-	if (ep0_urb) {
-		usbd_dealloc_urb(ep0_urb);
-		ep0_urb = NULL;
-	}
-
-	/* Reset device pointer */
-	udc_device = NULL;
-}
-
-/* Allow udc code to do any additional startup */
-void udc_startup_events(struct usb_device_instance *device)
-{
-	/* The DEVICE_INIT event puts the USB device in the state STATE_INIT */
-	usbd_device_event_irq(device, DEVICE_INIT, 0);
-
-	/* The DEVICE_CREATE event puts the USB device in the state
-	 * STATE_ATTACHED */
-	usbd_device_event_irq(device, DEVICE_CREATE, 0);
-
-	/* Some USB controller driver implementations signal
-	 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
-	 * DEVICE_HUB_CONFIGURED causes a transition to the state
-	 * STATE_POWERED, and DEVICE_RESET causes a transition to
-	 * the state STATE_DEFAULT.
-	 */
-	udc_enable(device);
-}
-
-/* Initialize h/w stuff */
-int udc_init(void)
-{
-	udc_device = NULL;
-	usbdbg("PXA27x usbd start");
-
-	/* Enable clock for USB device */
-	writel(readl(CKEN) | CKEN11_USB, CKEN);
-
-	/* Disable the UDC */
-	udc_clear_mask_UDCCR(UDCCR_UDE);
-
-	/* Disable IRQs: we don't use them */
-	writel(0, UDCICR0);
-	writel(0, UDCICR1);
-
-	return 0;
-}
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 8f77412..31ae9f7 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -32,6 +32,14 @@ config USB_XHCI_DWC3_OF_SIMPLE
 	  Support USB2/3 functionality in simple SoC integrations with
 	  USB controller based on the DesignWare USB3 IP Core.
 
+config USB_XHCI_EXYNOS
+	bool "Support for Samsung Exynos5 family on-chip xHCI USB controller"
+	depends on ARCH_EXYNOS5
+	default y
+	help
+	  Enables support for he on-chip xHCI controller on Samsung Exynos5
+	  SoCs.
+
 config USB_XHCI_MTK
 	bool "Support for MediaTek on-chip xHCI USB controller"
 	depends on ARCH_MEDIATEK
@@ -116,11 +124,19 @@ config USB_XHCI_BRCM
 
 endif # USB_XHCI_HCD
 
+config EHCI_DESC_BIG_ENDIAN
+	bool
+
+config EHCI_MMIO_BIG_ENDIAN
+	bool
+
 config USB_EHCI_HCD
 	bool "EHCI HCD (USB 2.0) support"
 	default y if ARCH_MX5 || ARCH_MX6
 	depends on DM && OF_CONTROL
 	select USB_HOST
+	select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN
+	select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN
 	---help---
 	  The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
 	  "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
@@ -149,6 +165,14 @@ config USB_EHCI_ATMEL
 	---help---
 	  Enables support for the on-chip EHCI controller on Atmel chips.
 
+config USB_EHCI_EXYNOS
+	bool "Support for Samsung Exynos EHCI USB controller"
+	depends on ARCH_EXYNOS
+	default y
+	---help---
+	  Enables support for the on-chip EHCI controller on Samsung Exynos
+	  SoCs.
+
 config USB_EHCI_MARVELL
 	bool "Support for Marvell on-chip EHCI USB controller"
 	depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
@@ -166,6 +190,7 @@ config USB_EHCI_MX5
 config USB_EHCI_MX6
 	bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
 	depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
+	select EHCI_HCD_INIT_AFTER_RESET
 	default y
 	---help---
 	  Enables support for the on-chip EHCI controller on i.MX6 SoCs.
@@ -173,6 +198,7 @@ config USB_EHCI_MX6
 config USB_EHCI_MX7
 	bool "Support for i.MX7 on-chip EHCI USB controller"
 	depends on ARCH_MX7 || IMX8M
+	select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7
 	select PHY if IMX8M
 	select NOP_PHY if IMX8M
 	default y
@@ -250,17 +276,38 @@ config USB_EHCI_GENERIC
 	---help---
 	  Enables support for generic EHCI controller.
 
+config EHCI_HCD_INIT_AFTER_RESET
+	bool
+
 config USB_EHCI_FSL
 	bool  "Support for FSL on-chip EHCI USB controller"
-	select  CONFIG_EHCI_HCD_INIT_AFTER_RESET
+	select EHCI_HCD_INIT_AFTER_RESET
 	---help---
 	  Enables support for the on-chip EHCI controller on FSL chips.
+
+config USB_EHCI_TXFIFO_THRESH
+	hex
+	depends on USB_EHCI_TEGRA
+	default 0x10
+	help
+	  This parameter affects a TXFILLTUNING field that controls how much
+	  data is sent to the latency fifo before it is sent to the wire.
+	  Without this parameter, the default (2) causes occasional Data Buffer
+	  Errors in OUT packets depending on the buffer address and size.
+
 endif # USB_EHCI_HCD
 
+config USB_OHCI_NEW
+	bool
+
+config SYS_USB_OHCI_CPU_INIT
+	bool
+
 config USB_OHCI_HCD
 	bool "OHCI HCD (USB 1.1) support"
 	depends on DM && OF_CONTROL
 	select USB_HOST
+	select USB_OHCI_NEW
 	---help---
 	  The Open Host Controller Interface (OHCI) is a standard for accessing
 	  USB 1.1 host controller hardware.  It does more in hardware than Intel's
@@ -292,6 +339,19 @@ config USB_OHCI_DA8XX
 
 endif # USB_OHCI_HCD
 
+config SYS_USB_OHCI_SLOT_NAME
+	string "Display name for the OHCI controller"
+	depends on USB_OHCI_NEW && !DM_USB
+
+config SYS_USB_OHCI_MAX_ROOT_PORTS
+	int "Maximal number of ports of the root hub"
+	depends on USB_OHCI_NEW
+	default 1 if ARCH_SUNXI
+
+config SYS_OHCI_SWAP_REG_ACCESS
+	bool "Perform byte swapping on OHCI controller register accesses"
+	depends on USB_OHCI_NEW
+
 config USB_UHCI_HCD
 	bool "UHCI HCD (most Intel and VIA) support"
 	select USB_HOST
@@ -340,3 +400,33 @@ config USB_R8A66597_HCD
 	---help---
 	  This enables support for the on-chip Renesas R8A66597 USB 2.0
 	  controller, present in various RZ and SH SoCs.
+
+config USB_ATMEL
+	bool "AT91 OHCI USB support"
+	depends on ARCH_AT91
+	select SYS_USB_OHCI_CPU_INIT
+	select USB_OHCI_NEW
+
+choice
+	prompt "Clock for OHCI"
+	depends on USB_ATMEL
+
+config USB_ATMEL_CLK_SEL_PLLB
+	bool "PLLB"
+
+config USB_ATMEL_CLK_SEL_UPLL
+	bool "UPLL"
+
+endchoice
+
+config USB_OHCI_LPC32XX
+	bool "LPC32xx USB OHCI support"
+	depends on ARCH_LPC32XX
+	select SYS_USB_OHCI_CPU_INIT
+	select USB_OHCI_NEW
+
+config USB_MAX_CONTROLLER_COUNT
+	int "Maximum number of USB host controllers"
+	depends on USB_EHCI_FSL || USB_XHCI_FSL || \
+		(SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB)
+	default 1
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7785b37..5fdb804 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -30,7 +30,6 @@ obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
 obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
 obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o
 obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
-obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
 obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
 obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index cf1f882..0569dd5 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -25,26 +25,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
-#if CONFIG_IS_ENABLED(DM_USB)
 struct ehci_fsl_priv {
 	struct ehci_ctrl ehci;
 	fdt_addr_t hcd_base;
 	char *phy_type;
 };
-#endif
 
 static void set_txfifothresh(struct usb_ehci *, u32);
-#if CONFIG_IS_ENABLED(DM_USB)
 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
 		  struct ehci_hccr *hccr, struct ehci_hcor *hcor);
-#else
-static int ehci_fsl_init(int index, struct usb_ehci *ehci,
-			 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
-#endif
 
 /* Check USB PHY clock valid */
 static int usb_phy_clk_valid(struct usb_ehci *ehci)
@@ -58,7 +47,6 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci)
 	}
 }
 
-#if CONFIG_IS_ENABLED(DM_USB)
 static int ehci_fsl_of_to_plat(struct udevice *dev)
 {
 	struct ehci_fsl_priv *priv = dev_get_priv(dev);
@@ -150,64 +138,11 @@ U_BOOT_DRIVER(ehci_fsl) = {
 	.priv_auto	= sizeof(struct ehci_fsl_priv),
 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
 };
-#else
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- *
- * Excerpts from linux ehci fsl driver.
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	struct ehci_ctrl *ehci_ctrl = container_of(hccr,
-					struct ehci_ctrl, hccr);
-	struct usb_ehci *ehci = NULL;
-
-	switch (index) {
-	case 0:
-		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
-		break;
-	case 1:
-		ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
-		break;
-	default:
-		printf("ERROR: wrong controller index!!\n");
-		return -EINVAL;
-	};
-
-	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
-	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
-	ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
-
-	return ehci_fsl_init(index, ehci, *hccr, *hcor);
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
-	return 0;
-}
-#endif
-
-#if CONFIG_IS_ENABLED(DM_USB)
 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
 		  struct ehci_hccr *hccr, struct ehci_hcor *hcor)
-#else
-static int ehci_fsl_init(int index, struct usb_ehci *ehci,
-			 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
-#endif
 {
 	const char *phy_type = NULL;
-#if !CONFIG_IS_ENABLED(DM_USB)
-	size_t len;
-	char current_usb_controller[5];
-#endif
 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 	char usb_phy[5];
 
@@ -230,18 +165,8 @@ static int ehci_fsl_init(int index, struct usb_ehci *ehci,
 	out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
 
 	/* Init phy */
-#if CONFIG_IS_ENABLED(DM_USB)
 	if (priv->phy_type)
 		phy_type = priv->phy_type;
-#else
-	memset(current_usb_controller, '\0', 5);
-	snprintf(current_usb_controller, sizeof(current_usb_controller),
-		 "usb%d", index+1);
-
-	if (hwconfig_sub(current_usb_controller, "phy_type"))
-		phy_type = hwconfig_subarg(current_usb_controller,
-				"phy_type", &len);
-#endif
 	else
 		phy_type = env_get("usb_phy_type");
 
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index e635526..f033198 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -25,10 +25,6 @@
 
 #include "ehci.h"
 
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
 /*
  * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
  * Let's time out after 8 to have a little safety margin on top of that.
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index ab863f4..964a53b 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -228,52 +228,6 @@ __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
 	mdelay(50);
 }
 
-#if !CONFIG_IS_ENABLED(DM_USB)
-static const struct ehci_ops mx5_ehci_ops = {
-	.powerup_fixup		= mx5_ehci_powerup_fixup,
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	struct usb_ehci *ehci;
-
-	/* The only user for this is efikamx-usb */
-	ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
-	set_usboh3_clk();
-	enable_usboh3_clk(true);
-	set_usb_phy_clk();
-	enable_usb_phy1_clk(true);
-	enable_usb_phy2_clk(true);
-	mdelay(1);
-
-	/* Do board specific initialization */
-	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
-
-	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
-		(0x200 * CONFIG_MXC_USB_PORT));
-	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
-	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-	setbits_le32(&ehci->usbmode, CM_HOST);
-
-	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
-	setbits_le32(&ehci->portsc, USB_EN);
-
-	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
-	mdelay(10);
-
-	/* Do board specific post-initialization */
-	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
-
-	return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
-	return 0;
-}
-#else /* CONFIG_IS_ENABLED(DM_USB) */
 struct ehci_mx5_priv_data {
 	struct ehci_ctrl ctrl;
 	struct usb_ehci *ehci;
@@ -372,4 +326,3 @@ U_BOOT_DRIVER(usb_mx5) = {
 	.priv_auto	= sizeof(struct ehci_mx5_priv_data),
 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
 };
-#endif /* !CONFIG_IS_ENABLED(DM_USB) */
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
deleted file mode 100644
index 1fb685e..0000000
--- a/drivers/usb/host/ehci-mxc.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- */
-
-
-#include <common.h>
-#include <usb.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <linux/delay.h>
-#include <usb/ehci-ci.h>
-#include <errno.h>
-
-#include "ehci.h"
-
-#define USBCTRL_OTGBASE_OFFSET	0x600
-
-#define MX25_OTG_SIC_SHIFT	29
-#define MX25_OTG_SIC_MASK	(0x3 << MX25_OTG_SIC_SHIFT)
-#define MX25_OTG_PM_BIT		(1 << 24)
-#define MX25_OTG_PP_BIT		(1 << 11)
-#define MX25_OTG_OCPOL_BIT	(1 << 3)
-
-#define MX25_H1_SIC_SHIFT	21
-#define MX25_H1_SIC_MASK	(0x3 << MX25_H1_SIC_SHIFT)
-#define MX25_H1_PP_BIT		(1 << 18)
-#define MX25_H1_PM_BIT		(1 << 16)
-#define MX25_H1_IPPUE_UP_BIT	(1 << 7)
-#define MX25_H1_IPPUE_DOWN_BIT	(1 << 6)
-#define MX25_H1_TLL_BIT		(1 << 5)
-#define MX25_H1_USBTE_BIT	(1 << 4)
-#define MX25_H1_OCPOL_BIT	(1 << 2)
-
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
-
-#define MX31_H2_SIC_SHIFT	21
-#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT		(1 << 16)
-#define MX31_H2_DT_BIT		(1 << 5)
-
-#define MX31_H1_SIC_SHIFT	13
-#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT		(1 << 8)
-#define MX31_H1_DT_BIT		(1 << 4)
-
-#define MX35_OTG_SIC_SHIFT	29
-#define MX35_OTG_SIC_MASK	(0x3 << MX35_OTG_SIC_SHIFT)
-#define MX35_OTG_PM_BIT		(1 << 24)
-#define MX35_OTG_PP_BIT		(1 << 11)
-#define MX35_OTG_OCPOL_BIT	(1 << 3)
-
-#define MX35_H1_SIC_SHIFT	21
-#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)
-#define MX35_H1_PP_BIT		(1 << 18)
-#define MX35_H1_PM_BIT		(1 << 16)
-#define MX35_H1_IPPUE_UP_BIT	(1 << 7)
-#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)
-#define MX35_H1_TLL_BIT		(1 << 5)
-#define MX35_H1_USBTE_BIT	(1 << 4)
-#define MX35_H1_OCPOL_BIT	(1 << 2)
-
-static int mxc_set_usbcontrol(int port, unsigned int flags)
-{
-	unsigned int v;
-
-	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-#if defined(CONFIG_MX31)
-	switch (port) {
-	case 0:	/* OTG port */
-		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX31_OTG_PM_BIT;
-
-		break;
-	case 1: /* H1 port */
-		v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX31_H1_PM_BIT;
-
-		if (!(flags & MXC_EHCI_TTL_ENABLED))
-			v |= MX31_H1_DT_BIT;
-
-		break;
-	case 2:	/* H2 port */
-		v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX31_H2_PM_BIT;
-
-		if (!(flags & MXC_EHCI_TTL_ENABLED))
-			v |= MX31_H2_DT_BIT;
-
-		break;
-	default:
-		return -EINVAL;
-	}
-#else
-#error MXC EHCI USB driver not supported on this platform
-#endif
-	writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-
-	return 0;
-}
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	struct usb_ehci *ehci;
-#ifdef CONFIG_MX31
-	struct clock_control_regs *sc_regs =
-		(struct clock_control_regs *)CCM_BASE;
-
-	__raw_readl(&sc_regs->ccmr);
-	__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
-#endif
-
-	udelay(80);
-
-	ehci = (struct usb_ehci *)(IMX_USB_BASE +
-			IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
-	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
-	*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
-			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
-	setbits_le32(&ehci->usbmode, CM_HOST);
-	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
-	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
-
-	udelay(10000);
-
-	return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
- */
-int ehci_hcd_stop(int index)
-{
-	return 0;
-}
diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c
index 9a61495..147b2fa 100644
--- a/drivers/usb/host/ehci-mxs.c
+++ b/drivers/usb/host/ehci-mxs.c
@@ -112,82 +112,6 @@ static int __ehci_hcd_stop(struct ehci_mxs_port *port)
 	return ehci_mxs_toggle_clock(port, 0);
 }
 
-#if !CONFIG_IS_ENABLED(DM_USB)
-static const struct ehci_mxs_port mxs_port[] = {
-#ifdef CONFIG_EHCI_MXS_PORT0
-	{
-		MXS_USBCTRL0_BASE,
-		(struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
-		(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
-			offsetof(struct mxs_clkctrl_regs,
-			hw_clkctrl_pll0ctrl0_reg)),
-		CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
-		CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
-		HW_DIGCTL_CTRL_USB0_CLKGATE,
-	},
-#endif
-#ifdef CONFIG_EHCI_MXS_PORT1
-	{
-		MXS_USBCTRL1_BASE,
-		(struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
-		(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
-			offsetof(struct mxs_clkctrl_regs,
-			hw_clkctrl_pll1ctrl0_reg)),
-		CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
-		CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
-		HW_DIGCTL_CTRL_USB1_CLKGATE,
-	},
-#endif
-};
-
-int __weak board_ehci_hcd_init(int port)
-{
-	return 0;
-}
-
-int __weak board_ehci_hcd_exit(int port)
-{
-	return 0;
-}
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-
-	int ret;
-	const struct ehci_mxs_port *port;
-
-	if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
-		printf("Invalid port index (index = %d)!\n", index);
-		return -EINVAL;
-	}
-
-	ret = board_ehci_hcd_init(index);
-	if (ret)
-		return ret;
-
-	port = &mxs_port[index];
-	return __ehci_hcd_init(port, init, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
-	int ret;
-	const struct ehci_mxs_port *port;
-
-	if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
-		printf("Invalid port index (index = %d)!\n", index);
-		return -EINVAL;
-	}
-
-	port = &mxs_port[index];
-
-	ret = __ehci_hcd_stop(port);
-	board_ehci_hcd_exit(index);
-
-	return ret;
-}
-#else /* CONFIG_IS_ENABLED(DM_USB) */
 struct ehci_mxs_priv_data {
 	struct ehci_ctrl ctrl;
 	struct usb_ehci *ehci;
@@ -367,4 +291,3 @@ U_BOOT_DRIVER(usb_mxs) = {
 	.priv_auto = sizeof(struct ehci_mxs_priv_data),
 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
 };
-#endif /* !CONFIG_IS_ENABLED(DM_USB) */
diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c
index 8ceabaf..9b955c1 100644
--- a/drivers/usb/host/ohci-at91.c
+++ b/drivers/usb/host/ohci-at91.c
@@ -5,9 +5,6 @@
  */
 
 #include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-
 #include <asm/arch/clk.h>
 
 int usb_cpu_init(void)
@@ -65,5 +62,3 @@ int usb_cpu_init_fail(void)
 {
 	return usb_cpu_stop();
 }
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c
index 163f0ef..5d23058 100644
--- a/drivers/usb/host/ohci-generic.c
+++ b/drivers/usb/host/ohci-generic.c
@@ -14,10 +14,6 @@
 #include <reset.h>
 #include "ohci.h"
 
-#if !defined(CONFIG_USB_OHCI_NEW)
-# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW"
-#endif
-
 struct generic_ohci {
 	ohci_t ohci;
 	struct clk *clocks;	/* clock list */
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index fedf0db..9acef5e 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -35,13 +35,6 @@
 #include <asm/cache.h>
 #include <linux/delay.h>
 
-#if defined(CONFIG_PCI_OHCI)
-# include <pci.h>
-#if !defined(CONFIG_PCI_OHCI_DEVNO)
-#define CONFIG_PCI_OHCI_DEVNO	0
-#endif
-#endif
-
 #include <malloc.h>
 #include <memalign.h>
 #include <usb.h>
@@ -53,7 +46,6 @@
 #endif
 
 #if defined(CONFIG_CPU_ARM920T) || \
-	defined(CONFIG_PCI_OHCI) || \
 	defined(CONFIG_PCI) || \
 	defined(CONFIG_SYS_OHCI_USE_NPS)
 # define OHCI_USE_NPS		/* force NoPowerSwitching mode */
@@ -68,26 +60,6 @@
 #define OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
 
-#if !CONFIG_IS_ENABLED(DM_USB)
-#ifdef CONFIG_PCI_OHCI
-static struct pci_device_id ohci_pci_ids[] = {
-	{0x10b9, 0x5237},	/* ULI1575 PCI OHCI module ids */
-	{0x1033, 0x0035},	/* NEC PCI OHCI module ids */
-	{0x1131, 0x1561},	/* Philips 1561 PCI OHCI module ids */
-	/* Please add supported PCI OHCI controller ids here */
-	{0, 0}
-};
-#endif
-#endif
-
-#ifdef CONFIG_PCI_EHCI_DEVNO
-static struct pci_device_id ehci_pci_ids[] = {
-	{0x1131, 0x1562},	/* Philips 1562 PCI EHCI module ids */
-	/* Please add supported PCI EHCI controller ids here */
-	{0, 0}
-};
-#endif
-
 #ifdef DEBUG
 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
 #else
@@ -2007,21 +1979,6 @@ static char ohci_inited = 0;
 
 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
-#ifdef CONFIG_PCI_OHCI
-	pci_dev_t pdev;
-#endif
-
-#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
-	/* cpu dependant init */
-	if (usb_cpu_init())
-		return -1;
-#endif
-
-#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
-	/*  board dependant init */
-	if (board_usb_init(index, USB_INIT_HOST))
-		return -1;
-#endif
 	memset(&gohci, 0, sizeof(ohci_t));
 
 	/* align the storage */
@@ -2036,28 +1993,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 	gohci.disabled = 1;
 	gohci.sleeping = 0;
 	gohci.irq = -1;
-#ifdef CONFIG_PCI_OHCI
-	pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
-
-	if (pdev != -1) {
-		u16 vid, did;
-		u32 base;
-		pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
-		pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
-		printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
-				vid, did, (pdev >> 16) & 0xff,
-				(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
-		pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
-		printf("OHCI regs address 0x%08x\n", base);
-		gohci.regs = (struct ohci_regs *)base;
-	} else {
-		printf("%s: OHCI devnr: %d not found\n", __func__,
-		       CONFIG_PCI_OHCI_DEVNO);
-		return -1;
-	}
-#else
 	gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
-#endif
 
 	gohci.flags = 0;
 	gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
@@ -2065,15 +2001,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 	if (hc_reset (&gohci) < 0) {
 		hc_release_ohci (&gohci);
 		err ("can't reset usb-%s", gohci.slot_name);
-#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
-		/* board dependant cleanup */
-		board_usb_cleanup(index, USB_INIT_HOST);
-#endif
-
-#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
-		/* cpu dependant cleanup */
-		usb_cpu_init_fail();
-#endif
 		return -1;
 	}
 
@@ -2081,15 +2008,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 		err("can't start usb-%s", gohci.slot_name);
 		hc_release_ohci(&gohci);
 		/* Initialization failed */
-#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
-		/* board dependant cleanup */
-		usb_board_stop();
-#endif
-
-#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
-		/* cpu dependant cleanup */
-		usb_cpu_stop();
-#endif
 		return -1;
 	}
 
@@ -2112,17 +2030,6 @@ int usb_lowlevel_stop(int index)
 	/* call hc_release_ohci() here ? */
 	hc_reset(&gohci);
 
-#ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
-	/* board dependant cleanup */
-	if (usb_board_stop())
-		return -1;
-#endif
-
-#ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
-	/* cpu dependant cleanup */
-	if (usb_cpu_stop())
-		return -1;
-#endif
 	/* This driver is no longer initialised. It needs a new low-level
 	 * init (board/cpu) before it can be used again. */
 	ohci_inited = 0;
diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
index a38cd25..7699f2e 100644
--- a/drivers/usb/host/ohci.h
+++ b/drivers/usb/host/ohci.h
@@ -151,7 +151,7 @@ struct ohci_hcca {
  * Maximum number of root hub ports.
  */
 #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
-# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
 #endif
 
 /*
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index 8087190..e67e09e 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -20,16 +20,11 @@
 #include <dm.h>
 
 /* Declare global data pointer */
-#if !CONFIG_IS_ENABLED(DM_USB)
-static struct fsl_xhci fsl_xhci;
-unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
-#else
 struct xhci_fsl_priv {
 	struct xhci_ctrl xhci;
 	fdt_addr_t hcd_base;
 	struct fsl_xhci ctx;
 };
-#endif
 
 __weak int __board_usb_init(int index, enum usb_init_type init)
 {
@@ -108,7 +103,6 @@ static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(DM_USB)
 static int xhci_fsl_probe(struct udevice *dev)
 {
 	struct xhci_fsl_priv *priv = dev_get_priv(dev);
@@ -174,44 +168,3 @@ U_BOOT_DRIVER(xhci_fsl) = {
 	.priv_auto	= sizeof(struct xhci_fsl_priv),
 	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
 };
-#else
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
-{
-	struct fsl_xhci *ctx = &fsl_xhci;
-	int ret = 0;
-
-	ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
-	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
-
-	ret = board_usb_init(index, USB_INIT_HOST);
-	if (ret != 0) {
-		puts("Failed to initialize board for USB\n");
-		return ret;
-	}
-
-	fsl_apply_xhci_errata();
-
-	ret = fsl_xhci_core_init(ctx);
-	if (ret < 0) {
-		puts("Failed to initialize xhci\n");
-		return ret;
-	}
-
-	*hccr = (struct xhci_hccr *)ctx->hcd;
-	*hcor = (struct xhci_hcor *)((uintptr_t) *hccr
-				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
-
-	debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
-	      (uintptr_t)*hccr, (uintptr_t)*hcor,
-	      (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
-
-	return ret;
-}
-
-void xhci_hcd_stop(int index)
-{
-	struct fsl_xhci *ctx = &fsl_xhci;
-
-	fsl_xhci_core_exit(ctx);
-}
-#endif
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index ad73ba1..dbeb88a 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -37,10 +37,6 @@
 #include <linux/errno.h>
 #include <linux/iopoll.h>
 
-#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#endif
-
 static struct descriptor {
 	struct usb_hub_descriptor hub;
 	struct usb_device_descriptor device;
@@ -115,13 +111,8 @@ static struct descriptor {
 	},
 };
 
-#if !CONFIG_IS_ENABLED(DM_USB)
-static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
-#endif
-
 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
 {
-#if CONFIG_IS_ENABLED(DM_USB)
 	struct udevice *dev;
 
 	/* Find the USB controller */
@@ -130,9 +121,6 @@ struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
 	     dev = dev->parent)
 		;
 	return dev_get_priv(dev);
-#else
-	return udev->controller;
-#endif
 }
 
 /**
@@ -752,13 +740,6 @@ static int _xhci_alloc_device(struct usb_device *udev)
 	return 0;
 }
 
-#if !CONFIG_IS_ENABLED(DM_USB)
-int usb_alloc_device(struct usb_device *udev)
-{
-	return _xhci_alloc_device(udev);
-}
-#endif
-
 /*
  * Full speed devices may have a max packet size greater than 8 bytes, but the
  * USB core doesn't know that until it reads the first 8 bytes of the
@@ -1267,95 +1248,6 @@ static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
 	return 0;
 }
 
-#if !CONFIG_IS_ENABLED(DM_USB)
-int submit_control_msg(struct usb_device *udev, unsigned long pipe,
-		       void *buffer, int length, struct devrequest *setup)
-{
-	struct usb_device *hop = udev;
-
-	if (hop->parent)
-		while (hop->parent->parent)
-			hop = hop->parent;
-
-	return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
-					hop->portnr);
-}
-
-int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
-		    int length)
-{
-	return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
-}
-
-int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
-		   int length, int interval, bool nonblock)
-{
-	return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
-				    nonblock);
-}
-
-/**
- * Intialises the XHCI host controller
- * and allocates the necessary data structures
- *
- * @param index	index to the host controller data structure
- * Return: pointer to the intialised controller
- */
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
-	struct xhci_hccr *hccr;
-	struct xhci_hcor *hcor;
-	struct xhci_ctrl *ctrl;
-	int ret;
-
-	*controller = NULL;
-
-	if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
-		return -ENODEV;
-
-	if (xhci_reset(hcor) != 0)
-		return -ENODEV;
-
-	ctrl = &xhcic[index];
-
-	ctrl->hccr = hccr;
-	ctrl->hcor = hcor;
-
-	ret = xhci_lowlevel_init(ctrl);
-
-	if (ret) {
-		ctrl->hccr = NULL;
-		ctrl->hcor = NULL;
-	} else {
-		*controller = &xhcic[index];
-	}
-
-	return ret;
-}
-
-/**
- * Stops the XHCI host controller
- * and cleans up all the related data structures
- *
- * @param index	index to the host controller data structure
- * Return: none
- */
-int usb_lowlevel_stop(int index)
-{
-	struct xhci_ctrl *ctrl = (xhcic + index);
-
-	if (ctrl->hcor) {
-		xhci_lowlevel_stop(ctrl);
-		xhci_hcd_stop(index);
-		xhci_cleanup(ctrl);
-	}
-
-	return 0;
-}
-#endif /* CONFIG_IS_ENABLED(DM_USB) */
-
-#if CONFIG_IS_ENABLED(DM_USB)
-
 static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
 				   unsigned long pipe, void *buffer, int length,
 				   struct devrequest *setup)
@@ -1546,5 +1438,3 @@ struct dm_usb_ops xhci_usb_ops = {
 	.update_hub_device = xhci_update_hub_device,
 	.get_max_xfer_size  = xhci_get_max_xfer_size,
 };
-
-#endif
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 965b587..4ecc158 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -583,6 +583,8 @@ config ATMEL_HLCD
 
 source "drivers/video/ti/Kconfig"
 
+source "drivers/video/exynos/Kconfig"
+
 config LOGICORE_DP_TX
 	bool "Enable Logicore DP TX driver"
 	depends on DISPLAY
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 2596580..7019b26 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -36,9 +36,7 @@ obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o
 obj-$(CONFIG_NXP_TDA19988) += tda19988.o
 obj-$(CONFIG_OSD) += video_osd-uclass.o
-obj-$(CONFIG_PXA_LCD) += pxa_lcd.o
 obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o
-obj-$(CONFIG_S6E8AX0) += s6e8ax0.o
 obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o
 obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o
 obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig
new file mode 100644
index 0000000..37e661b
--- /dev/null
+++ b/drivers/video/exynos/Kconfig
@@ -0,0 +1,20 @@
+
+menuconfig VIDEO_EXYNOS
+	bool "Enable Exynos video support"
+	depends on DM_VIDEO
+	help
+	  Enable support for various video output options on Exynos SoCs.
+
+if VIDEO_EXYNOS
+
+config EXYNOS_DP
+	bool "Exynos Display Port support"
+
+config EXYNOS_FB
+	bool "Exynos FIMD support"
+
+config EXYNOS_MIPI_DSIM
+	bool "Exynos MIPI DSI support"
+	depends on EXYNOS_FB
+
+endif
diff --git a/drivers/video/exynos/exynos_pwm_bl.c b/drivers/video/exynos/exynos_pwm_bl.c
deleted file mode 100644
index a3d467a..0000000
--- a/drivers/video/exynos/exynos_pwm_bl.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PWM BACKLIGHT driver for Board based on EXYNOS.
- *
- * Author: Donghwa Lee  <dh09.lee@samsung.com>
- *
- * Derived from linux/drivers/video/backlight/pwm_backlight.c
- */
-
-#include <common.h>
-#include <pwm.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pwm.h>
-#include <asm/arch/pwm_backlight.h>
-
-static struct pwm_backlight_data *pwm;
-
-static int exynos_pwm_backlight_update_status(void)
-{
-	int brightness = pwm->brightness;
-	int max = pwm->max_brightness;
-
-	if (brightness == 0) {
-		pwm_config(pwm->pwm_id, 0, pwm->period);
-		pwm_disable(pwm->pwm_id);
-	} else {
-		pwm_config(pwm->pwm_id,
-			brightness * pwm->period / max, pwm->period);
-		pwm_enable(pwm->pwm_id);
-	}
-	return 0;
-}
-
-int exynos_pwm_backlight_init(struct pwm_backlight_data *pd)
-{
-	pwm = pd;
-
-	exynos_pwm_backlight_update_status();
-
-	return 0;
-}
diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
deleted file mode 100644
index 21ade8d..0000000
--- a/drivers/video/pxa_lcd.c
+++ /dev/null
@@ -1,549 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * PXA LCD Controller
- *
- * (C) Copyright 2001-2002
- * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
- */
-
-/************************************************************************/
-/* ** HEADER FILES							*/
-/************************************************************************/
-
-#include <common.h>
-#include <log.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/io.h>
-#include <lcd.h>
-#include <linux/types.h>
-#include <stdarg.h>
-#include <stdio_dev.h>
-
-/* #define DEBUG */
-
-#ifdef CONFIG_LCD
-
-/*----------------------------------------------------------------------*/
-/*
- * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
- * your display.
- */
-
-#ifdef CONFIG_PXA_VGA
-/* LCD outputs connected to a video DAC  */
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF01
-
-/* 640x480x16 @ 61 Hz */
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 640,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 40,
-	.vl_blw		= 56,
-	.vl_elw		= 56,
-	.vl_vpw		= 20,
-	.vl_bfw		= 8,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_PXA_VIDEO */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_SHARP_LM8V31
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS	/* Needed for colors to be correct, but why?	*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x0030087C
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 3,
-	.vl_elw		= 3,
-	.vl_vpw		= 1,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_SHARP_LM8V31 */
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_VOIPAC_LCD
-
-# define LCD_BPP	LCD_COLOR8
-# define LCD_INVERT_COLORS
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x0340FF08
-
-vidinfo_t panel_info = {
-	.vl_col		= 640,
-	.vl_row		= 480,
-	.vl_width	= 157,
-	.vl_height	= 118,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 32,
-	.vl_blw		= 144,
-	.vl_elw		= 32,
-	.vl_vpw		= 2,
-	.vl_bfw		= 13,
-	.vl_efw		= 30,
-};
-#endif /* CONFIG_VOIPAC_LCD */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_HITACHI_SX14
-/* Hitachi SX14Q004-ZZA color STN LCD */
-#define LCD_BPP		LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-#define REG_LCCR0	0x00301079
-#define REG_LCCR3	0x0340FF20
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 240,
-	.vl_width	= 167,
-	.vl_height	= 109,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 1,
-	.vl_splt	= 0,
-	.vl_clor	= 1,
-	.vl_tft		= 0,
-	.vl_hpw		= 1,
-	.vl_blw		= 1,
-	.vl_elw		= 1,
-	.vl_vpw		= 7,
-	.vl_bfw		= 0,
-	.vl_efw		= 0,
-};
-#endif /* CONFIG_HITACHI_SX14 */
-
-/*----------------------------------------------------------------------*/
-#ifdef CONFIG_LMS283GF05
-
-# define LCD_BPP	LCD_COLOR8
-/*# define LCD_INVERT_COLORS*/
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x043008f8
-# define REG_LCCR3	0x03b00009
-
-vidinfo_t panel_info = {
-	.vl_col		= 240,
-	.vl_row		= 320,
-	.vl_rot		= 3,
-	.vl_width	= 240,
-	.vl_height	= 320,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 4,
-	.vl_blw		= 4,
-	.vl_elw		= 8,
-	.vl_vpw		= 4,
-	.vl_bfw		= 4,
-	.vl_efw		= 8,
-};
-#endif /* CONFIG_LMS283GF05 */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LQ038J7DH53
-
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f9
-# define REG_LCCR3	0x03700004
-
-vidinfo_t panel_info = {
-	.vl_col		= 320,
-	.vl_row		= 480,
-	.vl_width	= 320,
-	.vl_height	= 480,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_LOW,
-	.vl_hsp		= CONFIG_SYS_LOW,
-	.vl_vsp		= CONFIG_SYS_LOW,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 1,
-	.vl_clor	= 1,
-	.vl_tft		= 1,
-	.vl_hpw		= 0x04,
-	.vl_blw		= 0x20,
-	.vl_elw		= 0x01,
-	.vl_vpw		= 0x01,
-	.vl_bfw		= 0x04,
-	.vl_efw		= 0x01,
-};
-#endif /* CONFIG_LQ038J7DH53 */
-
-/*----------------------------------------------------------------------*/
-
-#ifdef CONFIG_LITTLETON_LCD
-# define LCD_BPP	LCD_COLOR8
-
-/* you have to set lccr0 and lccr3 (including pcd) */
-# define REG_LCCR0	0x003008f8
-# define REG_LCCR3	0x0300FF04
-
-vidinfo_t panel_info = {
-	.vl_col		= 480,
-	.vl_row		= 640,
-	.vl_width	= 480,
-	.vl_height	= 640,
-	.vl_clkp	= CONFIG_SYS_HIGH,
-	.vl_oep		= CONFIG_SYS_HIGH,
-	.vl_hsp		= CONFIG_SYS_HIGH,
-	.vl_vsp		= CONFIG_SYS_HIGH,
-	.vl_dp		= CONFIG_SYS_HIGH,
-	.vl_bpix	= LCD_BPP,
-	.vl_lbw		= 0,
-	.vl_splt	= 0,
-	.vl_clor	= 0,
-	.vl_tft		= 1,
-	.vl_hpw		= 9,
-	.vl_blw		= 8,
-	.vl_elw		= 24,
-	.vl_vpw		= 2,
-	.vl_bfw		= 2,
-	.vl_efw		= 4,
-};
-#endif /* CONFIG_LITTLETON_LCD */
-
-/*----------------------------------------------------------------------*/
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
-static void pxafb_setup_gpio (vidinfo_t *vid);
-static void pxafb_enable_controller (vidinfo_t *vid);
-static int pxafb_init (vidinfo_t *vid);
-
-/************************************************************************/
-/* ---------------  PXA chipset specific functions  ------------------- */
-/************************************************************************/
-
-ushort *configuration_get_cmap(void)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	return (ushort *)fbi->palette;
-}
-
-void lcd_ctrl_init (void *lcdbase)
-{
-	pxafb_init_mem(lcdbase, &panel_info);
-	pxafb_init(&panel_info);
-	pxafb_setup_gpio(&panel_info);
-	pxafb_enable_controller(&panel_info);
-}
-
-/*----------------------------------------------------------------------*/
-#if LCD_BPP == LCD_COLOR8
-void
-lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
-{
-	struct pxafb_info *fbi = &panel_info.pxa;
-	unsigned short *palette = (unsigned short *)fbi->palette;
-	u_int val;
-
-	if (regno < fbi->palette_size) {
-		val = ((red << 8) & 0xf800);
-		val |= ((green << 4) & 0x07e0);
-		val |= (blue & 0x001f);
-
-#ifdef LCD_INVERT_COLORS
-		palette[regno] = ~val;
-#else
-		palette[regno] = val;
-#endif
-	}
-
-	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
-		regno, &palette[regno],
-		red, green, blue,
-		palette[regno]);
-}
-#endif /* LCD_COLOR8 */
-
-/*----------------------------------------------------------------------*/
-__weak void lcd_enable(void)
-{
-}
-
-/************************************************************************/
-/* ** PXA255 specific routines						*/
-/************************************************************************/
-
-/*
- * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
- * descriptors and palette areas.
- */
-ulong calc_fbsize (void)
-{
-	ulong size;
-	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
-
-	size = line_length * panel_info.vl_row;
-	size += PAGE_SIZE;
-
-	return size;
-}
-
-static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
-{
-	u_long palette_mem_size;
-	struct pxafb_info *fbi = &vid->pxa;
-	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
-
-	fbi->screen = (u_long)lcdbase;
-
-	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-	palette_mem_size = fbi->palette_size * sizeof(u16);
-
-	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
-	/* locate palette and descs at end of page following fb */
-	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
-
-	return 0;
-}
-#ifdef	CONFIG_CPU_MONAHANS
-static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
-#else
-static void pxafb_setup_gpio (vidinfo_t *vid)
-{
-	u_long lccr0;
-
-	/*
-	 * setup is based on type of panel supported
-	 */
-
-	lccr0 = vid->pxa.reg_lccr0;
-
-	/* 4 bit interface */
-	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
-	{
-		debug("Setting GPIO for 4 bit data\n");
-		/* bits 58-61 */
-		writel(readl(GPDR1) | (0xf << 26), GPDR1);
-		writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR1_U);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 8 bit interface */
-	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
-		(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
-	{
-		debug("Setting GPIO for 8 bit data\n");
-		/* bits 58-65 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | (0x3), GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
-
-		/* bits 74-77 */
-		writel(readl(GPDR2) | (0xf << 10), GPDR2);
-		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
-			GAFR2_L);
-	}
-
-	/* 16 bit interface */
-	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
-	{
-		debug("Setting GPIO for 16 bit data\n");
-		/* bits 58-77 */
-		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
-		writel(readl(GPDR2) | 0x00003fff, GPDR2);
-
-		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
-			GAFR1_U);
-		writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
-	}
-	else
-	{
-		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
-	}
-}
-#endif
-
-static void pxafb_enable_controller (vidinfo_t *vid)
-{
-	debug("Enabling LCD controller\n");
-
-	/* Sequence from 11.7.10 */
-	writel(vid->pxa.reg_lccr3, LCCR3);
-	writel(vid->pxa.reg_lccr2, LCCR2);
-	writel(vid->pxa.reg_lccr1, LCCR1);
-	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
-	writel(vid->pxa.fdadr0, FDADR0);
-	writel(vid->pxa.fdadr1, FDADR1);
-	writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
-
-#ifdef	CONFIG_CPU_MONAHANS
-	writel(readl(CKENA) | CKENA_1_LCD, CKENA);
-#else
-	writel(readl(CKEN) | CKEN16_LCD, CKEN);
-#endif
-
-	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
-	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
-	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
-	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
-	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
-	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
-}
-
-static int pxafb_init (vidinfo_t *vid)
-{
-	struct pxafb_info *fbi = &vid->pxa;
-
-	debug("Configuring PXA LCD\n");
-
-	fbi->reg_lccr0 = REG_LCCR0;
-	fbi->reg_lccr3 = REG_LCCR3;
-
-	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
-		vid->vl_col, vid->vl_hpw,
-		vid->vl_blw, vid->vl_elw);
-	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
-		vid->vl_row, vid->vl_vpw,
-		vid->vl_bfw, vid->vl_efw);
-
-	fbi->reg_lccr1 =
-		LCCR1_DisWdth(vid->vl_col) +
-		LCCR1_HorSnchWdth(vid->vl_hpw) +
-		LCCR1_BegLnDel(vid->vl_blw) +
-		LCCR1_EndLnDel(vid->vl_elw);
-
-	fbi->reg_lccr2 =
-		LCCR2_DisHght(vid->vl_row) +
-		LCCR2_VrtSnchWdth(vid->vl_vpw) +
-		LCCR2_BegFrmDel(vid->vl_bfw) +
-		LCCR2_EndFrmDel(vid->vl_efw);
-
-	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
-	fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
-			| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
-
-
-	/* setup dma descriptors */
-	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
-	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
-	fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
-
-	#define BYTES_PER_PANEL	((fbi->reg_lccr0 & LCCR0_SDS) ? \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
-		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
-
-	/* populate descriptors */
-	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
-	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
-	fbi->dmadesc_fblow->fidr  = 0;
-	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
-
-	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
-
-	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
-	fbi->dmadesc_fbhigh->fidr = 0;
-	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
-
-	fbi->dmadesc_palette->fsadr = fbi->palette;
-	fbi->dmadesc_palette->fidr  = 0;
-	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
-
-	if( NBITS(vid->vl_bpix) < 12)
-	{
-		/* assume any mode with <12 bpp is palette driven */
-		fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
-		/* flips back and forth between pal and fbhigh */
-		fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
-	}
-	else
-	{
-		/* palette shouldn't be loaded in true-color mode */
-		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
-		fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
-	}
-
-	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
-	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
-	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
-
-	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
-	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
-	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
-
-	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
-	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
-	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
-
-	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
-	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
-	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
-
-	return 0;
-}
-
-/************************************************************************/
-/************************************************************************/
-
-#endif /* CONFIG_LCD */
diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c
deleted file mode 100644
index 497258f..0000000
--- a/drivers/video/s6e8ax0.c
+++ /dev/null
@@ -1,265 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- */
-
-#include <common.h>
-#include <asm/arch/mipi_dsim.h>
-#include <linux/delay.h>
-
-#include "exynos/exynos_mipi_dsi_lowlevel.h"
-#include "exynos/exynos_mipi_dsi_common.h"
-
-static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	int reverse = dsim_dev->dsim_lcd_dev->reverse_panel;
-	static const unsigned char data_to_send[] = {
-		0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c,
-		0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20,
-		0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
-		0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3,
-		0xff, 0xff, 0xc8
-	};
-
-	static const unsigned char data_to_send_reverse[] = {
-		0xf8, 0x19, 0x35, 0x00, 0x00, 0x00, 0x93, 0x00, 0x3c,
-		0x7d, 0x08, 0x27, 0x7d, 0x3f, 0x00, 0x00, 0x00, 0x20,
-		0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
-		0x23, 0x23, 0xc0, 0xc1, 0x01, 0x41, 0xc1, 0x00, 0xc1,
-		0xf6, 0xf6, 0xc1
-	};
-
-	if (reverse) {
-		ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send_reverse,
-			ARRAY_SIZE(data_to_send_reverse));
-	} else {
-		ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-	}
-}
-
-static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf2, 0x80, 0x03, 0x0d
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	/* 7500K 2.2 Set : 30cd */
-	static const unsigned char data_to_send[] = {
-		0xfa, 0x01, 0x60, 0x10, 0x60, 0xf5, 0x00, 0xff, 0xad,
-		0xaf, 0xba, 0xc3, 0xd8, 0xc5, 0x9f, 0xc6, 0x9e, 0xc1,
-		0xdc, 0xc0, 0x00, 0x61, 0x00, 0x5a, 0x00, 0x74,
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf7, 0x03
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
-			ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf6, 0x00, 0x02, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0,
-		0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe3, 0x40
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
-		       ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xb1, 0x04, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-			data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0x29, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
-		       ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0x11, 0x00
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
-		       ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf0, 0x5a, 0x5a
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev)
-{
-	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
-	static const unsigned char data_to_send[] = {
-		0xf1, 0x5a, 0x5a
-	};
-
-	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
-		data_to_send, ARRAY_SIZE(data_to_send));
-}
-
-static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev)
-{
-	/*
-	 * in case of setting gamma and panel condition at first,
-	 * it shuold be setting like below.
-	 * set_gamma() -> set_panel_condition()
-	 */
-
-	s6e8ax0_apply_level1_key(dsim_dev);
-	s6e8ax0_apply_mtp_key(dsim_dev);
-
-	s6e8ax0_sleep_out(dsim_dev);
-	mdelay(5);
-	s6e8ax0_panel_cond(dsim_dev);
-	s6e8ax0_display_cond(dsim_dev);
-	s6e8ax0_gamma_cond(dsim_dev);
-	s6e8ax0_gamma_update(dsim_dev);
-
-	s6e8ax0_etc_source_control(dsim_dev);
-	s6e8ax0_elvss_set(dsim_dev);
-	s6e8ax0_etc_pentile_control(dsim_dev);
-	s6e8ax0_etc_mipi_control1(dsim_dev);
-	s6e8ax0_etc_mipi_control2(dsim_dev);
-	s6e8ax0_etc_power_control(dsim_dev);
-	s6e8ax0_etc_mipi_control3(dsim_dev);
-	s6e8ax0_etc_mipi_control4(dsim_dev);
-}
-
-static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev)
-{
-	s6e8ax0_panel_init(dsim_dev);
-
-	return 0;
-}
-
-static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev)
-{
-	s6e8ax0_display_on(dsim_dev);
-}
-
-static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = {
-	.name = "s6e8ax0",
-	.id = -1,
-
-	.mipi_panel_init = s6e8ax0_panel_set,
-	.mipi_display_on = s6e8ax0_display_enable,
-};
-
-void s6e8ax0_init(void)
-{
-	exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver);
-}
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 7f1cbc5..f71bab7 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -16,21 +16,40 @@
 #include <linux/bug.h>
 #include <linux/compat.h>
 
+static unsigned int virtqueue_attach_desc(struct virtqueue *vq, unsigned int i,
+					  struct virtio_sg *sg, u16 flags)
+{
+	struct vring_desc_shadow *desc_shadow = &vq->vring_desc_shadow[i];
+	struct vring_desc *desc = &vq->vring.desc[i];
+
+	/* Update the shadow descriptor. */
+	desc_shadow->addr = (u64)(uintptr_t)sg->addr;
+	desc_shadow->len = sg->length;
+	desc_shadow->flags = flags;
+
+	/* Update the shared descriptor to match the shadow. */
+	desc->addr = cpu_to_virtio64(vq->vdev, desc_shadow->addr);
+	desc->len = cpu_to_virtio32(vq->vdev, desc_shadow->len);
+	desc->flags = cpu_to_virtio16(vq->vdev, desc_shadow->flags);
+	desc->next = cpu_to_virtio16(vq->vdev, desc_shadow->next);
+
+	return desc_shadow->next;
+}
+
 int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[],
 		  unsigned int out_sgs, unsigned int in_sgs)
 {
 	struct vring_desc *desc;
-	unsigned int total_sg = out_sgs + in_sgs;
-	unsigned int i, n, avail, descs_used, uninitialized_var(prev);
+	unsigned int descs_used = out_sgs + in_sgs;
+	unsigned int i, n, avail, uninitialized_var(prev);
 	int head;
 
-	WARN_ON(total_sg == 0);
+	WARN_ON(descs_used == 0);
 
 	head = vq->free_head;
 
 	desc = vq->vring.desc;
 	i = head;
-	descs_used = total_sg;
 
 	if (vq->num_free < descs_used) {
 		debug("Can't add buf len %i - avail = %i\n",
@@ -45,30 +64,17 @@ int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[],
 		return -ENOSPC;
 	}
 
-	for (n = 0; n < out_sgs; n++) {
-		struct virtio_sg *sg = sgs[n];
-
-		desc[i].flags = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT);
-		desc[i].addr = cpu_to_virtio64(vq->vdev, (u64)(size_t)sg->addr);
-		desc[i].len = cpu_to_virtio32(vq->vdev, sg->length);
-
-		prev = i;
-		i = virtio16_to_cpu(vq->vdev, desc[i].next);
-	}
-	for (; n < (out_sgs + in_sgs); n++) {
-		struct virtio_sg *sg = sgs[n];
-
-		desc[i].flags = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT |
-						VRING_DESC_F_WRITE);
-		desc[i].addr = cpu_to_virtio64(vq->vdev,
-					       (u64)(uintptr_t)sg->addr);
-		desc[i].len = cpu_to_virtio32(vq->vdev, sg->length);
+	for (n = 0; n < descs_used; n++) {
+		u16 flags = VRING_DESC_F_NEXT;
 
+		if (n >= out_sgs)
+			flags |= VRING_DESC_F_WRITE;
 		prev = i;
-		i = virtio16_to_cpu(vq->vdev, desc[i].next);
+		i = virtqueue_attach_desc(vq, i, sgs[n], flags);
 	}
 	/* Last one doesn't continue */
-	desc[prev].flags &= cpu_to_virtio16(vq->vdev, ~VRING_DESC_F_NEXT);
+	vq->vring_desc_shadow[prev].flags &= ~VRING_DESC_F_NEXT;
+	desc[prev].flags = cpu_to_virtio16(vq->vdev, vq->vring_desc_shadow[prev].flags);
 
 	/* We're using some buffers from the free list. */
 	vq->num_free -= descs_used;
@@ -76,6 +82,9 @@ int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[],
 	/* Update free pointer */
 	vq->free_head = i;
 
+	/* Mark the descriptor as the head of a chain. */
+	vq->vring_desc_shadow[head].chain_head = true;
+
 	/*
 	 * Put entry in available array (but don't update avail->idx
 	 * until they do sync).
@@ -137,17 +146,19 @@ void virtqueue_kick(struct virtqueue *vq)
 static void detach_buf(struct virtqueue *vq, unsigned int head)
 {
 	unsigned int i;
-	__virtio16 nextflag = cpu_to_virtio16(vq->vdev, VRING_DESC_F_NEXT);
+
+	/* Unmark the descriptor as the head of a chain. */
+	vq->vring_desc_shadow[head].chain_head = false;
 
 	/* Put back on free list: unmap first-level descriptors and find end */
 	i = head;
 
-	while (vq->vring.desc[i].flags & nextflag) {
-		i = virtio16_to_cpu(vq->vdev, vq->vring.desc[i].next);
+	while (vq->vring_desc_shadow[i].flags & VRING_DESC_F_NEXT) {
+		i = vq->vring_desc_shadow[i].next;
 		vq->num_free++;
 	}
 
-	vq->vring.desc[i].next = cpu_to_virtio16(vq->vdev, vq->free_head);
+	vq->vring_desc_shadow[i].next = vq->free_head;
 	vq->free_head = head;
 
 	/* Plus final descriptor */
@@ -189,6 +200,12 @@ void *virtqueue_get_buf(struct virtqueue *vq, unsigned int *len)
 		return NULL;
 	}
 
+	if (unlikely(!vq->vring_desc_shadow[i].chain_head)) {
+		printf("(%s.%d): id %u is not a head\n",
+		       vq->vdev->name, vq->index, i);
+		return NULL;
+	}
+
 	detach_buf(vq, i);
 	vq->last_used_idx++;
 	/*
@@ -200,8 +217,7 @@ void *virtqueue_get_buf(struct virtqueue *vq, unsigned int *len)
 		virtio_store_mb(&vring_used_event(&vq->vring),
 				cpu_to_virtio16(vq->vdev, vq->last_used_idx));
 
-	return (void *)(uintptr_t)virtio64_to_cpu(vq->vdev,
-						  vq->vring.desc[i].addr);
+	return (void *)(uintptr_t)vq->vring_desc_shadow[i].addr;
 }
 
 static struct virtqueue *__vring_new_virtqueue(unsigned int index,
@@ -210,6 +226,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index,
 {
 	unsigned int i;
 	struct virtqueue *vq;
+	struct vring_desc_shadow *vring_desc_shadow;
 	struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
 	struct udevice *vdev = uc_priv->vdev;
 
@@ -217,10 +234,17 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index,
 	if (!vq)
 		return NULL;
 
+	vring_desc_shadow = calloc(vring.num, sizeof(struct vring_desc_shadow));
+	if (!vring_desc_shadow) {
+		free(vq);
+		return NULL;
+	}
+
 	vq->vdev = vdev;
 	vq->index = index;
 	vq->num_free = vring.num;
 	vq->vring = vring;
+	vq->vring_desc_shadow = vring_desc_shadow;
 	vq->last_used_idx = 0;
 	vq->avail_flags_shadow = 0;
 	vq->avail_idx_shadow = 0;
@@ -238,7 +262,7 @@ static struct virtqueue *__vring_new_virtqueue(unsigned int index,
 	/* Put everything in free lists */
 	vq->free_head = 0;
 	for (i = 0; i < vring.num - 1; i++)
-		vq->vring.desc[i].next = cpu_to_virtio16(vdev, i + 1);
+		vq->vring_desc_shadow[i].next = i + 1;
 
 	return vq;
 }
@@ -291,6 +315,7 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num,
 void vring_del_virtqueue(struct virtqueue *vq)
 {
 	free(vq->vring.desc);
+	free(vq->vring_desc_shadow);
 	list_del(&vq->list);
 	free(vq);
 }
@@ -336,11 +361,12 @@ void virtqueue_dump(struct virtqueue *vq)
 	printf("\tlast_used_idx %u, avail_flags_shadow %u, avail_idx_shadow %u\n",
 	       vq->last_used_idx, vq->avail_flags_shadow, vq->avail_idx_shadow);
 
-	printf("Descriptor dump:\n");
+	printf("Shadow descriptor dump:\n");
 	for (i = 0; i < vq->vring.num; i++) {
-		printf("\tdesc[%u] = { 0x%llx, len %u, flags %u, next %u }\n",
-		       i, vq->vring.desc[i].addr, vq->vring.desc[i].len,
-		       vq->vring.desc[i].flags, vq->vring.desc[i].next);
+		struct vring_desc_shadow *desc = &vq->vring_desc_shadow[i];
+
+		printf("\tdesc_shadow[%u] = { 0x%llx, len %u, flags %u, next %u }\n",
+		       i, desc->addr, desc->len, desc->flags, desc->next);
 	}
 
 	printf("Avail ring dump:\n");
diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c
index 9314c0a..b85545c 100644
--- a/drivers/virtio/virtio_rng.c
+++ b/drivers/virtio/virtio_rng.c
@@ -41,6 +41,9 @@ static int virtio_rng_read(struct udevice *dev, void *data, size_t len)
 		while (!virtqueue_get_buf(priv->rng_vq, &rsize))
 			;
 
+		if (rsize > sg.length)
+			return -EIO;
+
 		memcpy(ptr, buf, rsize);
 		len -= rsize;
 		ptr += rsize;
diff --git a/drivers/virtio/virtio_sandbox.c b/drivers/virtio/virtio_sandbox.c
index aafb7be..5484ae3 100644
--- a/drivers/virtio/virtio_sandbox.c
+++ b/drivers/virtio/virtio_sandbox.c
@@ -160,8 +160,8 @@ static int virtio_sandbox_probe(struct udevice *udev)
 	struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
 
 	/* fake some information for testing */
-	priv->device_features = VIRTIO_F_VERSION_1;
-	uc_priv->device = VIRTIO_ID_BLOCK;
+	priv->device_features = BIT_ULL(VIRTIO_F_VERSION_1);
+	uc_priv->device = VIRTIO_ID_RNG;
 	uc_priv->vendor = ('u' << 24) | ('b' << 16) | ('o' << 8) | 't';
 
 	return 0;
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c3eb8a8..532ada8 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -64,8 +64,8 @@ config ULP_WATCHDOG
 
 config DESIGNWARE_WATCHDOG
 	bool "Designware watchdog timer support"
-	select HW_WATCHDOG if !WDT
-	default y if WDT && ROCKCHIP_RK3399
+	depends on WDT
+	default y if ROCKCHIP_RK3399
 	help
 	  Enable this to support Designware Watchdog Timer IP, present e.g.
 	  on Altera SoCFPGA SoCs.
diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c
index cfec29b..cad756a 100644
--- a/drivers/watchdog/designware_wdt.c
+++ b/drivers/watchdog/designware_wdt.c
@@ -60,26 +60,6 @@ static void designware_wdt_reset_common(void __iomem *base)
 		writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
 }
 
-#if !CONFIG_IS_ENABLED(WDT)
-void hw_watchdog_reset(void)
-{
-	designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
-}
-
-void hw_watchdog_init(void)
-{
-	/* reset to disable the watchdog */
-	hw_watchdog_reset();
-	/* set timer in miliseconds */
-	designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
-				  CONFIG_DW_WDT_CLOCK_KHZ,
-				  CONFIG_WATCHDOG_TIMEOUT_MSECS);
-	/* enable the watchdog */
-	designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
-	/* reset the watchdog */
-	hw_watchdog_reset();
-}
-#else
 static int designware_wdt_reset(struct udevice *dev)
 {
 	struct designware_wdt_priv *priv = dev_get_priv(dev);
@@ -195,4 +175,3 @@ U_BOOT_DRIVER(designware_wdt) = {
 	.ops = &designware_wdt_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
-#endif