diff options
author | Stefano Babic <sbabic@denx.de> | 2010-03-13 21:09:00 +0100 |
---|---|---|
committer | Wolfgang Denk <wd@denx.de> | 2010-03-21 22:22:52 +0100 |
commit | 99c006a320ceb9ea19135ac1512e4a81e8bebb72 (patch) | |
tree | f1eb5327d1c8dcbc6f336f30a2352f56596c55b1 /drivers | |
parent | c96f86eefc215b67dd222694ce2b6f60e6a42b0b (diff) | |
download | u-boot-99c006a320ceb9ea19135ac1512e4a81e8bebb72.zip u-boot-99c006a320ceb9ea19135ac1512e4a81e8bebb72.tar.gz u-boot-99c006a320ceb9ea19135ac1512e4a81e8bebb72.tar.bz2 |
mxcmmc: fix warnings due to access 32 bit registers with 16 bit accessors
Some registers of the mxcmmc driver were accessed using
16 bit accessor functions, because only the LSB is
significant. This is not needed and generates
warnings.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mmc/mxcmmc.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index d307176..5963953 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -136,14 +136,14 @@ static void mxcmci_softreset(struct mxcmci_host *host) int i; /* reset sequence */ - writew(STR_STP_CLK_RESET, &host->base->str_stp_clk); - writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, + writel(STR_STP_CLK_RESET, &host->base->str_stp_clk); + writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, &host->base->str_stp_clk); for (i = 0; i < 8; i++) - writew(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); + writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); - writew(0xff, &host->base->res_to); + writel(0xff, &host->base->res_to); } static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) @@ -154,8 +154,8 @@ static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) host->data = data; - writew(nob, &host->base->nob); - writew(blksz, &host->base->blk_len); + writel(nob, &host->base->nob); + writel(blksz, &host->base->blk_len); host->datasize = datasize; } @@ -185,9 +185,9 @@ static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd, return -EINVAL; } - writew(cmd->cmdidx, &host->base->cmd); + writel(cmd->cmdidx, &host->base->cmd); writel(cmd->cmdarg, &host->base->arg); - writew(cmdat, &host->base->cmd_dat_cont); + writel(cmdat, &host->base->cmd_dat_cont); return 0; } @@ -247,14 +247,14 @@ static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) if (cmd->resp_type & MMC_RSP_PRESENT) { if (cmd->resp_type & MMC_RSP_136) { for (i = 0; i < 4; i++) { - a = readw(&host->base->res_fifo); - b = readw(&host->base->res_fifo); + a = readl(&host->base->res_fifo) & 0xFFFF; + b = readl(&host->base->res_fifo) & 0xFFFF; resp[i] = a << 16 | b; } } else { - a = readw(&host->base->res_fifo); - b = readw(&host->base->res_fifo); - c = readw(&host->base->res_fifo); + a = readl(&host->base->res_fifo) & 0xFFFF; + b = readl(&host->base->res_fifo) & 0xFFFF; + c = readl(&host->base->res_fifo) & 0xFFFF; resp[0] = a << 24 | b << 8 | c >> 8; } } @@ -445,7 +445,7 @@ static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) prescaler <<= 1; } - writew((prescaler << 4) | divider, &host->base->clk_rate); + writel((prescaler << 4) | divider, &host->base->clk_rate); } static void mxcmci_set_ios(struct mmc *mmc) @@ -458,9 +458,9 @@ static void mxcmci_set_ios(struct mmc *mmc) if (mmc->clock) { mxcmci_set_clk_rate(host, mmc->clock); - writew(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); + writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); } else { - writew(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk); + writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk); } host->clock = mmc->clock; @@ -472,7 +472,7 @@ static int mxcmci_init(struct mmc *mmc) mxcmci_softreset(host); - host->rev_no = readw(&host->base->rev_no); + host->rev_no = readl(&host->base->rev_no); if (host->rev_no != 0x400) { printf("wrong rev.no. 0x%08x. aborting.\n", host->rev_no); @@ -480,7 +480,7 @@ static int mxcmci_init(struct mmc *mmc) } /* recommended in data sheet */ - writew(0x2db4, &host->base->read_to); + writel(0x2db4, &host->base->read_to); writel(0, &host->base->int_cntr); |