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| author | Samuel Holland <samuel@sholland.org> | 2020-05-07 18:10:50 -0500 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-06-01 22:38:22 +0530 |
| commit | abdbefba2a4e9666f798de13b4b88021f23b19f3 (patch) | |
| tree | e1be5220d85b0de508af1bc05ff484d14f31cb2b /drivers | |
| parent | 5cfeeacaea24329625e6538345fcc3a8546c53f9 (diff) | |
| download | u-boot-abdbefba2a4e9666f798de13b4b88021f23b19f3.zip u-boot-abdbefba2a4e9666f798de13b4b88021f23b19f3.tar.gz u-boot-abdbefba2a4e9666f798de13b4b88021f23b19f3.tar.bz2 | |
net: sun8i_emac: Use consistent clock bitfield definitions
While the R40 uses a different register for EMAC clock configuration
than other chips, the register has a very similar layout. Reuse the
existing bitfield definitions in this file, since they match.
This allows the driver to compile on the H6 platform, where the
CCM_GMAC_CTRL definitions are not present.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/sun8i_emac.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 99e24c6..edbec9f 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -300,9 +300,9 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, if (priv->variant == R40_GMAC) { /* Select RGMII for R40 */ reg = readl(priv->sysctl_reg + 0x164); - reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | - CCM_GMAC_CTRL_GPIT_RGMII | - CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY); + reg |= SC_ETCS_INT_GMII | + SC_EPIT | + (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET); writel(reg, priv->sysctl_reg + 0x164); return 0; |