diff options
| author | Wenyou Yang <wenyou.yang@microchip.com> | 2017-11-17 14:50:22 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-11-29 22:30:50 -0500 |
| commit | 63a80b8d03744c48c188e6bc6f7f69813507cfdb (patch) | |
| tree | 11fcc1284861932a86d332dd5eaabf9ed13fbfed /drivers | |
| parent | eb1ed2b19befecdfeddb394e6174bb2198f2a49b (diff) | |
| download | u-boot-63a80b8d03744c48c188e6bc6f7f69813507cfdb.zip u-boot-63a80b8d03744c48c188e6bc6f7f69813507cfdb.tar.gz u-boot-63a80b8d03744c48c188e6bc6f7f69813507cfdb.tar.bz2 | |
clk: at91: clk-generated: fix incorrect index of clk source
Differentiate the generic clock source selection value from the parent
clock index to fix the incorrect assignment of the generic clock
source selection.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/at91/clk-generated.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 461b5b2..2aacbae 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -53,16 +53,17 @@ static ulong generic_clk_get_rate(struct clk *clk) struct clk parent; ulong clk_rate; u32 tmp, gckdiv; - u8 parent_id; + u8 clock_source, parent_index; int ret; writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); tmp = readl(&pmc->pcr); - parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) & + clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) & AT91_PMC_PCR_GCKCSS_MASK; gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK; - ret = clk_get_by_index(dev_get_parent(clk->dev), parent_id, &parent); + parent_index = clock_source - 1; + ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent); if (ret) return 0; @@ -82,7 +83,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate) ulong tmp_rate, best_rate = rate, parent_rate; int tmp_diff, best_diff = -1; u32 div, best_div = 0; - u8 best_parent_id = 0; + u8 best_parent_index, best_clock_source = 0; u8 i; u32 tmp; int ret; @@ -106,7 +107,8 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate) best_div = div - 1; best_parent = parent; - best_parent_id = i; + best_parent_index = i; + best_clock_source = best_parent_index + 1; } if (!best_diff || tmp_rate < rate) @@ -127,7 +129,7 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate) writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); tmp = readl(&pmc->pcr); tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS); - tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) | + tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) | AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_GCKDIV_(best_div) | AT91_PMC_PCR_GCKEN; |