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| author | Peng Fan <Peng.Fan@freescale.com> | 2014-12-31 11:01:39 +0800 |
|---|---|---|
| committer | Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> | 2014-12-31 14:52:32 +0530 |
| commit | ba4dc8ab7260b2afb0f9d5de0ae9c3723e699df0 (patch) | |
| tree | 26217f9066b3ee0d27e1ecb1d3981f8f6c4df763 /drivers | |
| parent | b93ab2ee751a4a0231330a89e2f2f29963b434d0 (diff) | |
| download | u-boot-ba4dc8ab7260b2afb0f9d5de0ae9c3723e699df0.zip u-boot-ba4dc8ab7260b2afb0f9d5de0ae9c3723e699df0.tar.gz u-boot-ba4dc8ab7260b2afb0f9d5de0ae9c3723e699df0.tar.bz2 | |
imx:qspi add 4K erase support
Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/fsl_qspi.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e9c45de..d12f420 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -32,12 +32,14 @@ #define SEQID_CHIP_ERASE 5 #define SEQID_PP 6 #define SEQID_RDID 7 +#define SEQID_BE_4K 8 /* QSPI CMD */ #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ #define QSPI_CMD_RDSR 0x05 /* Read status register */ #define QSPI_CMD_WREN 0x06 /* Write enable */ #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define QSPI_CMD_BE_4K 0x20 /* 4K erase */ #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ @@ -192,6 +194,12 @@ static void qspi_set_lut(struct fsl_qspi *qspi) qspi_write32(®s->lut[lut_base + 2], 0); qspi_write32(®s->lut[lut_base + 3], 0); + /* SUB SECTOR 4K ERASE */ + lut_base = SEQID_BE_4K * 4; + qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + /* Lock the LUT */ qspi_write32(®s->lutkey, LUT_KEY_VALUE); qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK); @@ -450,7 +458,7 @@ static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf) qspi_write32(®s->mcr, mcr_reg); } -static void qspi_op_se(struct fsl_qspi *qspi) +static void qspi_op_erase(struct fsl_qspi *qspi) { struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base; u32 mcr_reg; @@ -469,8 +477,13 @@ static void qspi_op_se(struct fsl_qspi *qspi) while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) ; - qspi_write32(®s->ipcr, - (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); + if (qspi->cur_seqid == QSPI_CMD_SE) { + qspi_write32(®s->ipcr, + (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); + } else if (qspi->cur_seqid == QSPI_CMD_BE_4K) { + qspi_write32(®s->ipcr, + (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0); + } while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK) ; @@ -497,9 +510,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, if (qspi->cur_seqid == QSPI_CMD_FAST_READ) { qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; - } else if (qspi->cur_seqid == QSPI_CMD_SE) { + } else if ((qspi->cur_seqid == QSPI_CMD_SE) || + (qspi->cur_seqid == QSPI_CMD_BE_4K)) { qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; - qspi_op_se(qspi); + qspi_op_erase(qspi); } else if (qspi->cur_seqid == QSPI_CMD_PP) { pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; } |