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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2017-07-18 11:29:12 +0800
committerYork Sun <york.sun@nxp.com>2017-08-09 09:57:32 -0700
commit89d8e1313f18131a5c451f094bad89ba35ed2120 (patch)
treefa8a75907c042f5226ae4cca7d1ce8933014b159 /drivers
parent563ac65a1ad2e0f97d1b7c3a9b91d18dddc1bd3d (diff)
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PCI: layerscape: Fix assigning wrong address to LS2088A pcie cfg1 space
This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add LS2088A series SoC pcie support), which only updated cfg_res.start and did not update the .end field. This causes fdt_resource_size() getting wrong value when calculate the cfg1 space address. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [YS: Revise subject and commit message] Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pcie_layerscape.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 78cde21..610f85c 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -478,6 +478,7 @@ static int ls_pcie_probe(struct udevice *dev)
bool ep_mode;
uint svr;
int ret;
+ fdt_size_t cfg_size;
pcie->bus = dev;
@@ -539,8 +540,10 @@ static int ls_pcie_probe(struct udevice *dev)
if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
svr == SVR_LS2048A || svr == SVR_LS2044A ||
svr == SVR_LS2081A || svr == SVR_LS2041A) {
+ cfg_size = fdt_resource_size(&pcie->cfg_res);
pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+ pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
pcie->ctrl = pcie->lut + 0x40000;
}