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| author | Simon Glass <sjg@chromium.org> | 2016-01-30 16:38:00 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2016-02-16 09:17:53 -0700 |
| commit | 41fa035ce1480aa87d42e4af0ed8ea841944c2c9 (patch) | |
| tree | d25e795428627e6511d287e22ba23a986da8280b /drivers | |
| parent | f5acf91f6f956c81489db283d55ec83ab780e5a3 (diff) | |
| download | u-boot-41fa035ce1480aa87d42e4af0ed8ea841944c2c9.zip u-boot-41fa035ce1480aa87d42e4af0ed8ea841944c2c9.tar.gz u-boot-41fa035ce1480aa87d42e4af0ed8ea841944c2c9.tar.bz2 | |
tegra: Convert CONFIG_PWM_TEGRA to Kconfig
Move this option to Kconfig and clean up the header files. Adjust the only
user (the LCD driver) to work with the new driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pwm/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cd8f357..e5880ac 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -17,3 +17,11 @@ config PWM_ROCKCHIP programmable period and duty cycle. A 32-bit counter is used. Various options provided in the hardware (such as capture mode and continuous/single-shot) are not supported by the driver. + +config PWM_TEGRA + bool "Enable support for the Tegra PWM" + help + This PWM is found on Tegra 20 and other Nvidia SoCs. It supports + four channels with a programmable period and duty cycle. Only a + 32KHz clock is supported by the driver but the duty cycle is + configurable. |