diff options
| author | Joel Stanley <joel@jms.id.au> | 2021-10-27 14:17:26 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-11-17 17:05:00 -0500 |
| commit | 4080714f5ee9253715ce72ebb4da4a02f4a9b3a0 (patch) | |
| tree | e6a0ed4085985cad925e166389d19ddadb4589fd /drivers | |
| parent | 3d99be97f1193c6b08f1498f02f390d4884af3d1 (diff) | |
| download | u-boot-4080714f5ee9253715ce72ebb4da4a02f4a9b3a0.zip u-boot-4080714f5ee9253715ce72ebb4da4a02f4a9b3a0.tar.gz u-boot-4080714f5ee9253715ce72ebb4da4a02f4a9b3a0.tar.bz2 | |
clk: ast2600: Add YCLK control for HACE
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/aspeed/clk_ast2600.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 3a92739..9871a6b 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1013,6 +1013,25 @@ static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) return 0; } +static ulong ast2600_enable_haceclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_HACE); + clkgate_bit = SCU_CLKGATE1_HACE; + + /* + * we don't do reset assertion here as HACE + * shares the same reset control with ACRY + */ + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(20); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + static int ast2600_clk_enable(struct clk *clk) { struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); @@ -1051,6 +1070,9 @@ static int ast2600_clk_enable(struct clk *clk) case ASPEED_CLK_GATE_USBPORT2CLK: ast2600_enable_usbbhclk(priv->scu); break; + case ASPEED_CLK_GATE_YCLK: + ast2600_enable_haceclk(priv->scu); + break; default: pr_err("can't enable clk\n"); return -ENOENT; |