clk: microchip: mpfs: fix reference clock handling

The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.

As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>

3 files changed, 149 insertions, 1 deletions

diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index 7ba1218..f16f716 100644
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -20,10 +20,12 @@ static int mpfs_clk_probe(struct udevice *dev)
 {
 	struct clk *parent_clk = dev_get_priv(dev);
 	struct clk clk_ahb = { .id = CLK_AHB };
+	struct clk clk_msspll = { .id = CLK_MSSPLL };
 	void __iomem *base;
+	void __iomem *msspll_base;
 	int ret;
 
-	base = dev_read_addr_ptr(dev);
+	base = dev_read_addr_index_ptr(dev, 0);
 	if (!base)
 		return -EINVAL;
 
@@ -31,6 +33,25 @@ static int mpfs_clk_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
+	/*
+	 * The original devicetrees for mpfs messed up & defined the msspll's
+	 * output as a fixed-frequency, 600 MHz clock & used that as the input
+	 * for the clock controller node. The msspll is however not a fixed
+	 * frequency clock and later devicetrees handled this properly. Check
+	 * the devicetree & if it is one of the fixed ones, register the msspll.
+	 * Otherwise, skip registering it & pass the reference clock directly
+	 * to the cfg clock registration function.
+	 */
+	msspll_base = dev_read_addr_index_ptr(dev, 1);
+	if (msspll_base) {
+		ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
+		if (ret)
+			return ret;
+
+		clk_request(dev, &clk_msspll);
+		parent_clk = &clk_msspll;
+	}
+
 	ret = mpfs_clk_register_cfgs(base, parent_clk);
 	if (ret)
 		return ret;
diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h
index 35cfeac..cb7d303 100644
--- a/drivers/clk/microchip/mpfs_clk.h
+++ b/drivers/clk/microchip/mpfs_clk.h
@@ -16,6 +16,14 @@
  */
 int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
 /**
+ * mpfs_clk_register_msspll() - register the mss pll
+ *
+ * @base: base address of the mpfs system register.
+ * @parent: a pointer to parent clock.
+ * Return: zero on success, or a negative error code.
+ */
+int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent);
+/**
  * mpfs_clk_register_periphs() - register peripheral clocks
  *
  * @base: base address of the mpfs system register.
diff --git a/drivers/clk/microchip/mpfs_clk_msspll.c b/drivers/clk/microchip/mpfs_clk_msspll.c
new file mode 100644
index 0000000..f37c0d8
--- /dev/null
+++ b/drivers/clk/microchip/mpfs_clk_msspll.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Microchip Technology Inc.
+ */
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <dm/devres.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/microchip-mpfs-clock.h>
+#include <linux/err.h>
+
+#include "mpfs_clk.h"
+
+#define MPFS_MSSPLL_CLOCK "mpfs_msspll_clock"
+
+/* address offset of control registers */
+#define REG_MSSPLL_REF_CR	0x08u
+#define REG_MSSPLL_POSTDIV_CR	0x10u
+#define REG_MSSPLL_SSCG_2_CR	0x2Cu
+
+#define MSSPLL_FBDIV_SHIFT	0x00u
+#define MSSPLL_FBDIV_WIDTH	0x0Cu
+#define MSSPLL_REFDIV_SHIFT	0x08u
+#define MSSPLL_REFDIV_WIDTH	0x06u
+#define MSSPLL_POSTDIV_SHIFT	0x08u
+#define MSSPLL_POSTDIV_WIDTH	0x07u
+#define MSSPLL_FIXED_DIV	4u
+
+/**
+ * struct mpfs_msspll_hw_clock
+ * @id: index of the msspll clock
+ * @name: the msspll clocks name
+ * @reg_offset: offset to the core complex's output of the msspll
+ * @shift: shift to the divider bit field of a msspll clock output
+ * @width: width of the divider bit field of the msspll clock output
+ * @flags: common clock framework flags
+ * @prate: the reference clock rate
+ * @hw: clock instance
+ */
+struct mpfs_msspll_hw_clock {
+	void __iomem *base;
+	unsigned int id;
+	const char *name;
+	u32 reg_offset;
+	u32 shift;
+	u32 width;
+	u32 flags;
+	u32 prate;
+	struct clk hw;
+};
+
+#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
+
+static unsigned long mpfs_clk_msspll_recalc_rate(struct clk *hw)
+{
+	struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
+	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
+	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
+	void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
+	u32 mult, ref_div, postdiv;
+	unsigned long temp;
+
+	mult = readl(mult_addr) >> MSSPLL_FBDIV_SHIFT;
+	mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
+	ref_div = readl(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
+	ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
+	postdiv = readl(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
+	postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
+
+	temp = msspll_hw->prate / (ref_div * MSSPLL_FIXED_DIV * postdiv);
+	return temp * mult;
+}
+
+#define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) {	\
+	.id = _id,							\
+	.name = _name,							\
+	.shift = _shift,						\
+	.width = _width,						\
+	.reg_offset = _reg_offset,					\
+	.flags = _flags,						\
+}
+
+static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
+	CLK_PLL(CLK_MSSPLL, "clk_msspll", MSSPLL_FBDIV_SHIFT,
+		MSSPLL_FBDIV_WIDTH, REG_MSSPLL_SSCG_2_CR, 0),
+};
+
+int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent)
+{
+	int id, ret;
+	const char *name;
+	struct clk *hw;
+
+	hw = &mpfs_msspll_clks[0].hw;
+	mpfs_msspll_clks[0].base = base;
+	mpfs_msspll_clks[0].prate = clk_get_rate(parent);
+	name = mpfs_msspll_clks[0].name;
+	ret = clk_register(hw, MPFS_MSSPLL_CLOCK, name, parent->dev->name);
+	if (ret)
+		ERR_PTR(ret);
+	id = mpfs_msspll_clks[0].id;
+	clk_dm(id, hw);
+
+	return 0;
+}
+
+const struct clk_ops mpfs_msspll_clk_ops = {
+	.get_rate = mpfs_clk_msspll_recalc_rate,
+};
+
+U_BOOT_DRIVER(mpfs_msspll_clock) = {
+	.name	= MPFS_MSSPLL_CLOCK,
+	.id	= UCLASS_CLK,
+	.ops	= &mpfs_msspll_clk_ops,
+};
+