Merge tag 'u-boot-imx-20211020' of https://source.denx.de/u-boot/custodians/u-boot-imxWIP/20Oct2021

u-boot-imx-20211020
-------------------

First PR from u-boot-imx for 2022.01

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535

- new board: kontron-sl-mx8mm
- imx8m:
	- fix secure boot
- imx ESDHC: fixes
- i.MX53: Support thum2, bmode and fixes for Menlo board
	  usbarmory switch to Ethernet driver model
- imx6 :
	- DDR calibration for Toradex boards
- imx7:
	- Fixes
- Updated gateworks boards (ventana / venice)

# gpg verification failed.

6 files changed, 32 insertions, 6 deletions

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 099ff29..3bae072 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -233,6 +233,15 @@ config MXC_OCOTP
 	  Programmable memory pages that are stored on the some
 	  Freescale i.MX processors.
 
+config SPL_MXC_OCOTP
+	bool "Enable MXC OCOTP driver in SPL"
+	depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
+	default y
+	help
+	  If you say Y here, you will get support for the One Time
+	  Programmable memory pages, that are stored on some
+	  Freescale i.MX processors, in SPL.
+
 config NUVOTON_NCT6102D
 	bool "Enable Nuvoton NCT6102D Super I/O driver"
 	help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index c16a77c..f9826d2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -50,7 +50,7 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
-obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
+obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
 obj-$(CONFIG_P2SB) += p2sb-uclass.o
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 5dfd484..4c06361 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -727,17 +727,20 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
 
 	if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
 		esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
+		/* clear the reset bit on strobe dll before any setting */
+		esdhc_write32(&regs->strobe_dllctrl, 0);
 
 		/*
 		 * enable strobe dll ctrl and adjust the delay target
 		 * for the uSDHC loopback read clock
 		 */
 		val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+			ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
 			(priv->strobe_dll_delay_target <<
 			 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
 		esdhc_write32(&regs->strobe_dllctrl, val);
-		/* wait 1us to make sure strobe dll status register stable */
-		mdelay(1);
+		/* wait 5us to make sure strobe dll status register stable */
+		mdelay(5);
 		val = esdhc_read32(&regs->strobe_dllstat);
 		if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
 			pr_warn("HS400 strobe DLL status REF not lock!\n");
@@ -971,7 +974,6 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 	if (priv->clock != clock)
 		set_sysctl(priv, mmc, clock);
 
-#ifdef MMC_SUPPORTS_TUNING
 	if (mmc->clk_disable) {
 #ifdef CONFIG_FSL_USDHC
 		esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
@@ -987,6 +989,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 #endif
 	}
 
+#ifdef MMC_SUPPORTS_TUNING
 	/*
 	 * For HS400/HS400ES mode, make sure set the strobe dll in the
 	 * target clock rate. So call esdhc_set_strobe_dll() after the
@@ -1707,6 +1710,12 @@ static struct esdhc_soc_data usdhc_imx7d_data = {
 			| ESDHC_FLAG_HS400,
 };
 
+static struct esdhc_soc_data usdhc_imx7ulp_data = {
+	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+			| ESDHC_FLAG_HS400,
+};
+
 static struct esdhc_soc_data usdhc_imx8qm_data = {
 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
 		ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
@@ -1721,7 +1730,7 @@ static const struct udevice_id fsl_esdhc_ids[] = {
 	{ .compatible = "fsl,imx6sl-usdhc", },
 	{ .compatible = "fsl,imx6q-usdhc", },
 	{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
-	{ .compatible = "fsl,imx7ulp-usdhc", },
+	{ .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,},
 	{ .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
 	{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
 	{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 332f9d7..cb0c0a1 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -369,7 +369,7 @@ config NAND_MXC
 	imply CMD_NAND
 	help
 	  This enables the NAND driver for the NAND flash controller on the
-	  i.MX27 / i.MX31 / i.MX5 rocessors.
+	  i.MX27 / i.MX31 / i.MX5 processors.
 
 config NAND_MXS
 	bool "MXS NAND support"
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 6b70d68..9e0b8afb 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -296,3 +296,9 @@ int nand_default_bbt(struct mtd_info *mtd)
 void nand_deselect(void)
 {
 }
+
+u32 nand_spl_adjust_offset(u32 sector, u32 offs)
+{
+	/* Handle the offset adjust in nand_spl_load_image,*/
+	return offs;
+}
diff --git a/drivers/rtc/rv8803.c b/drivers/rtc/rv8803.c
index acd50c6..5bae39d 100644
--- a/drivers/rtc/rv8803.c
+++ b/drivers/rtc/rv8803.c
@@ -157,6 +157,8 @@ static const struct rtc_ops rv8803_rtc_ops = {
 
 static const struct udevice_id rv8803_rtc_ids[] = {
 	{ .compatible = "microcrystal,rv8803", },
+	{ .compatible = "epson,rx8803" },
+	{ .compatible = "epson,rx8900" },
 	{ }
 };