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authorTom Rini <trini@konsulko.com>2019-05-22 12:58:58 -0400
committerTom Rini <trini@konsulko.com>2019-05-22 12:58:58 -0400
commit40920bdecc4e1b7096de6f546d7b5c2185554ba6 (patch)
treeaa3c93ff5606eaed9c93618c2691697b0da483cc /drivers
parent7e090b466c5ba874d31c1bf22c3a130d516cdc32 (diff)
parentee730a7cd2afe445e53e92b5c37396a5b118f7af (diff)
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Merge tag 'dm-pull-22may19' of git://git.denx.de/u-boot-dm
Various DM fixes Addition of ofnode_get_addr_size_index()
Diffstat (limited to 'drivers')
-rw-r--r--drivers/core/ofnode.c15
-rw-r--r--drivers/core/root.c2
-rw-r--r--drivers/misc/Kconfig72
-rw-r--r--drivers/misc/Makefile8
4 files changed, 89 insertions, 8 deletions
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index cc0c031..c72c6e2 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -39,7 +39,7 @@ int ofnode_read_u32(ofnode node, const char *propname, u32 *outp)
return 0;
}
-int ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
+u32 ofnode_read_u32_default(ofnode node, const char *propname, u32 def)
{
assert(ofnode_valid(node));
ofnode_read_u32(node, propname, &def);
@@ -251,7 +251,7 @@ int ofnode_read_size(ofnode node, const char *propname)
return -EINVAL;
}
-fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
{
int na, ns;
@@ -260,7 +260,7 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
uint flags;
prop_val = of_get_address(ofnode_to_np(node), index,
- NULL, &flags);
+ (u64 *)size, &flags);
if (!prop_val)
return FDT_ADDR_T_NONE;
@@ -277,12 +277,19 @@ fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
ns = ofnode_read_simple_size_cells(ofnode_get_parent(node));
return fdtdec_get_addr_size_fixed(gd->fdt_blob,
ofnode_to_offset(node), "reg",
- index, na, ns, NULL, true);
+ index, na, ns, size, true);
}
return FDT_ADDR_T_NONE;
}
+fdt_addr_t ofnode_get_addr_index(ofnode node, int index)
+{
+ fdt_size_t size;
+
+ return ofnode_get_addr_size_index(node, index, &size);
+}
+
fdt_addr_t ofnode_get_addr(ofnode node)
{
return ofnode_get_addr_index(node, 0);
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 8fa0966..aa5ca40 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -342,7 +342,7 @@ int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only)
{
int ret;
- ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only);
+ ret = dm_scan_fdt(blob, pre_reloc_only);
if (ret) {
debug("dm_scan_fdt() failed: %d\n", ret);
return ret;
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 0e645f5..cb8b5c0 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -13,6 +13,24 @@ config MISC
set of generic read, write and ioctl methods may be used to
access the device.
+config SPL_MISC
+ bool "Enable Driver Model for Misc drivers in SPL"
+ depends on SPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
+config TPL_MISC
+ bool "Enable Driver Model for Misc drivers in TPL"
+ depends on TPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
@@ -68,6 +86,24 @@ config CROS_EC
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
+config SPL_CROS_EC
+ bool "Enable Chrome OS EC in SPL"
+ help
+ Enable access to the Chrome OS EC in SPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
+config TPL_CROS_EC
+ bool "Enable Chrome OS EC in TPL"
+ help
+ Enable access to the Chrome OS EC in TPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
config CROS_EC_I2C
bool "Enable Chrome OS EC I2C driver"
depends on CROS_EC
@@ -86,6 +122,24 @@ config CROS_EC_LPC
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
+config SPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in SPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
+config TPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in TPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
config CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver"
depends on CROS_EC && SANDBOX
@@ -95,6 +149,24 @@ config CROS_EC_SANDBOX
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
+config SPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in SPL"
+ depends on SPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
+config TPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in TPL"
+ depends on TPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
config CROS_EC_SPI
bool "Enable Chrome OS EC SPI driver"
depends on CROS_EC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 6bdf505..509c588 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -4,11 +4,13 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_MISC) += misc-uclass.o
+
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC) += cros_ec.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
+obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
+
ifndef CONFIG_SPL_BUILD
-obj-$(CONFIG_CROS_EC) += cros_ec.o
-obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
-obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
endif