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author | Samuel Holland <samuel@sholland.org> | 2022-03-17 23:52:36 -0500 |
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committer | Andre Przywara <andre.przywara@arm.com> | 2022-04-04 23:24:17 +0100 |
commit | f5bfe1575078cea8de0fa4affb529b360a511094 (patch) | |
tree | 6bb5ef2d41bfe29c1f1a85087d3e4a0329d10f43 /drivers | |
parent | c9dd3caae3119c9f77081b5c1ef42553b44ddf20 (diff) | |
download | u-boot-f5bfe1575078cea8de0fa4affb529b360a511094.zip u-boot-f5bfe1575078cea8de0fa4affb529b360a511094.tar.gz u-boot-f5bfe1575078cea8de0fa4affb529b360a511094.tar.bz2 |
i2c: sun8i_rsb: Add support for DM clocks and resets
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.
This also has the added benefit of picking the right clock/reset
bits for H6 and new SoCs that have a rearranged PRCM MMIO space.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/i2c/sun8i_rsb.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c index 38d6e87..47fa05b 100644 --- a/drivers/i2c/sun8i_rsb.c +++ b/drivers/i2c/sun8i_rsb.c @@ -9,10 +9,12 @@ */ #include <axp_pmic.h> +#include <clk.h> #include <common.h> #include <dm.h> #include <errno.h> #include <i2c.h> +#include <reset.h> #include <time.h> #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> @@ -235,9 +237,19 @@ static int sun8i_rsb_probe_chip(struct udevice *bus, uint chip_addr, static int sun8i_rsb_probe(struct udevice *bus) { struct sun8i_rsb_priv *priv = dev_get_priv(bus); + struct reset_ctl *reset; + struct clk *clk; priv->base = dev_read_addr_ptr(bus); + reset = devm_reset_control_get(bus, NULL); + if (!IS_ERR(reset)) + reset_deassert(reset); + + clk = devm_clk_get(bus, NULL); + if (!IS_ERR(clk)) + clk_enable(clk); + return sun8i_rsb_init(priv->base); } |