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| author | Tom Rini <trini@konsulko.com> | 2020-01-16 09:40:09 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-01-16 09:40:09 -0500 |
| commit | f47704d4ae494ebc8a25c95202e548ea32f98955 (patch) | |
| tree | 1fe12b692cf15f97aafb17ab4261e8d8106a797a /drivers | |
| parent | 9d5d74c3ccdc78bac969d25e98eab96872e33b5c (diff) | |
| parent | 7b2e07ad34170c82a098b47a756311dec5e8e04a (diff) | |
| download | u-boot-f47704d4ae494ebc8a25c95202e548ea32f98955.zip u-boot-f47704d4ae494ebc8a25c95202e548ea32f98955.tar.gz u-boot-f47704d4ae494ebc8a25c95202e548ea32f98955.tar.bz2 | |
Merge branch '2020-01-15-master-imports'
- MediaTek improvements
- Some generic clk improvements
- A few assorted bugfixes
Diffstat (limited to 'drivers')
23 files changed, 3116 insertions, 92 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index e7b5d22..23501fd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -45,7 +45,7 @@ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ obj-$(CONFIG_SPL_DM_RESET) += reset/ -obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ +obj-$(CONFIG_SPL_DMA) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USB_ETHER) += net/phy/ diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 9aa8537..93cb490 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -344,6 +344,34 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) return clk_get_by_index(dev, index, clk); } +int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) +{ + int index; + + debug("%s(node=%p, name=%s, clk=%p)\n", __func__, + ofnode_get_name(node), name, clk); + clk->dev = NULL; + + index = ofnode_stringlist_search(node, "clock-names", name); + if (index < 0) { + debug("fdt_stringlist_search() failed: %d\n", index); + return index; + } + + return clk_get_by_index_nodev(node, index, clk); +} + +int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk) +{ + int ret; + + ret = clk_get_by_name_nodev(node, name, clk); + if (ret == -ENODATA) + return 0; + + return ret; +} + int clk_release_all(struct clk *clk, int count) { int i, ret; @@ -391,7 +419,7 @@ int clk_free(struct clk *clk) const struct clk_ops *ops; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -406,7 +434,7 @@ ulong clk_get_rate(struct clk *clk) const struct clk_ops *ops; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -422,7 +450,7 @@ struct clk *clk_get_parent(struct clk *clk) struct clk *pclk; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return NULL; pdev = dev_get_parent(clk->dev); @@ -439,7 +467,7 @@ long long clk_get_parent_rate(struct clk *clk) struct clk *pclk; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; pclk = clk_get_parent(clk); @@ -462,7 +490,7 @@ ulong clk_set_rate(struct clk *clk, ulong rate) const struct clk_ops *ops; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -477,7 +505,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) const struct clk_ops *ops; debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -494,7 +522,7 @@ int clk_enable(struct clk *clk) int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -554,7 +582,7 @@ int clk_disable(struct clk *clk) int ret; debug("%s(clk=%p)\n", __func__, clk); - if (!clk) + if (!clk_valid(clk)) return 0; ops = clk_dev_ops(clk->dev); @@ -678,7 +706,7 @@ struct clk *devm_clk_get_optional(struct udevice *dev, const char *id) { struct clk *clk = devm_clk_get(dev, id); - if (IS_ERR(clk)) + if (PTR_ERR(clk) == -ENODATA) return NULL; return clk; diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index f511267..2c20edd 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -13,8 +13,15 @@ static ulong clk_fixed_rate_get_rate(struct clk *clk) return to_clk_fixed_rate(clk->dev)->fixed_rate; } +/* avoid clk_enable() return -ENOSYS */ +static int dummy_enable(struct clk *clk) +{ + return 0; +} + const struct clk_ops clk_fixed_rate_ops = { .get_rate = clk_fixed_rate_get_rate, + .enable = dummy_enable, }; static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e92bcd4..237fd17 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,7 +3,9 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o # SoC Drivers +obj-$(CONFIG_MT8512) += clk-mt8512.o obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o +obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c new file mode 100644 index 0000000..a5b61a1 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7622 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/arch-mediatek/reset.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt7622-clk.h> + +#include "clk-mtk.h" + +#define MT7622_CLKSQ_STB_CON0 0x20 +#define MT7622_PLL_ISO_CON0 0x2c +#define MT7622_PLL_FMAX (2500UL * MHZ) +#define MT7622_CON0_RST_BAR BIT(24) + +#define MCU_AXI_DIV 0x640 +#define AXI_DIV_MSK GENMASK(4, 0) +#define AXI_DIV_SEL(x) (x) + +#define MCU_BUS_MUX 0x7c0 +#define MCU_BUS_MSK GENMASK(10, 9) +#define MCU_BUS_SEL(x) ((x) << 9) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT7622_CON0_RST_BAR, \ + .fmax = MT7622_PLL_FMAX, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, + 21, 0x204, 24, 0x204, 0), + PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, + 21, 0x214, 24, 0x214, 0), + PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, + 7, 0x224, 24, 0x224, 14), + PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, + 21, 0x300, 1, 0x304, 0), + PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, + 21, 0x314, 1, 0x318, 0), + PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0, + 31, 0x324, 1, 0x328, 0), + PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0, + 31, 0x334, 1, 0x338, 0), + PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0, + 21, 0x344, 1, 0x348, 0), + PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0, + 21, 0x358, 1, 0x35c, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000), + FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000), + FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000), + FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333), + FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000), + FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4), + FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125), + FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500), + FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1), + FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024), + FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1), + FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1), + FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2), + FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10), + FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28), + FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112), + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2), + FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), + FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48), + FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), + FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80), + FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7), + FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320), + FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25), + FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1), + FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2), + FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1), + FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1), + FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2), + FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4), + FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), + FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1), + FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1), +}; + +static const int axi_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL_D7 +}; + +static const int mem_parents[] = { + CLK_XTAL, + CLK_TOP_DMPLL +}; + +static const int ddrphycfg_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D8 +}; + +static const int eth_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + -1, + CLK_TOP_UNIVPLL_D7 +}; + +static const int pwm_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int f10m_ref_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL4_D16 +}; + +static const int nfi_infra_parents[] = { + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D4 +}; + +static const int flash_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL_D80_D4, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int uart_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi0_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int spi1_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D2, + CLK_XTAL, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_XTAL +}; + +static const int msdc30_0_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL2_D16, + CLK_TOP_UNIV48M +}; + +static const int a1sys_hp_parents[] = { + CLK_XTAL, + CLK_TOP_AUD1PLL, + CLK_TOP_AUD2PLL, + CLK_XTAL +}; + +static const int intdir_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL_D2, + CLK_TOP_SGMIIPLL +}; + +static const int aud_intbus_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL3_D2 +}; + +static const int pmicspi_parents[] = { + CLK_XTAL, + -1, + -1, + -1, + -1, + CLK_TOP_UNIVPLL2_D16 +}; + +static const int atb_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int audio_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_SYSPLL4_D4, + CLK_TOP_UNIVPLL1_D16 +}; + +static const int usb20_parents[] = { + CLK_XTAL, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_XTAL +}; + +static const int aud1_parents[] = { + CLK_XTAL, + CLK_TOP_AUD1PLL +}; + +static const int asm_l_parents[] = { + CLK_XTAL, + CLK_TOP_SYSPLL_D5, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int apll1_ck_parents[] = { + CLK_TOP_AUD1_SEL, + CLK_TOP_AUD2_SEL +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), + MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15), + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23), + MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31), + + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), + MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), + MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), + + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7), + MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15), + MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31), + + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15), + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23), + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31), + + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15), + MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23), + MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31), + + /* CLK_CFG_5 */ + MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7), + MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15, + CLK_DOMAIN_SCPSYS), + MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23), + MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31), + + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7), + MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15), + MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23), + MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31), + + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7), + MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15), + MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23), + + /* CLK_AUDDIV_0 */ + MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1), + MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1), + MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1), + MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1), + MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1), + MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1), +}; + +/* infracfg */ +static const struct mtk_gate_regs infra_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +#define GATE_INFRA(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_cgs[] = { + GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0), + GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), + GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5), + GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16), + GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18), + GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22), +}; + +/* pericfg */ +static const struct mtk_gate_regs peri0_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x10, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs peri1_cg_regs = { + .set_ofs = 0xC, + .clr_ofs = 0x14, + .sta_ofs = 0x1C, +}; + +#define GATE_PERI0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_PERI1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &peri1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate peri_cgs[] = { + /* PERI0 */ + GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), + GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2), + GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3), + GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4), + GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5), + GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6), + GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7), + GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8), + GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), + GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), + GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), + GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17), + GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), + GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), + GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22), + GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23), + GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), + GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), + GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), + GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), + GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), + GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), + GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31), + + /* PERI1 */ + GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1), + GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2), +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .sta_ofs = 0x30, +}; + +#define GATE_ETH(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = ð_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5), + GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6), + GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7), + GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8), + GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9), +}; + +static const struct mtk_gate_regs sgmii_cg_regs = { + .sta_ofs = 0xE4, +}; + +#define GATE_SGMII(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &sgmii_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + +static const struct mtk_gate sgmii_cgs[] = { + GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2), + GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4), + GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), +}; + +static const struct mtk_clk_tree mt7622_clk_tree = { + .xtal_rate = 25 * MHZ, + .xtal2_rate = 25 * MHZ, + .fdivs_offs = CLK_TOP_TO_USB3_SYS, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt7622_mcucfg_probe(struct udevice *dev) +{ + void __iomem *base; + + base = dev_read_addr_ptr(dev); + if (!base) + return -ENOENT; + + clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK, + AXI_DIV_SEL(0x12)); + clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK, + MCU_BUS_SEL(0x1)); + + return 0; +} + +static int mt7622_apmixedsys_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + int ret; + + ret = mtk_common_clk_init(dev, &mt7622_clk_tree); + if (ret) + return ret; + + /* reduce clock square disable time */ + // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0); + writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0); + + /* extend pwr/iso control timing to 1us */ + writel(0x80008, priv->base + MT7622_PLL_ISO_CON0); + + return 0; +} + +static int mt7622_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7622_clk_tree); +} + +static int mt7622_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs); +} + +static int mt7622_pericfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs); +} + +static int mt7622_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); +} + +static int mt7622_ethsys_bind(struct udevice *dev) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(RESET_MEDIATEK) + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); +#endif + + return ret; +} + +static int mt7622_sgmiisys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs); +} + +static const struct udevice_id mt7622_apmixed_compat[] = { + { .compatible = "mediatek,mt7622-apmixedsys" }, + { } +}; + +static const struct udevice_id mt7622_topckgen_compat[] = { + { .compatible = "mediatek,mt7622-topckgen" }, + { } +}; + +static const struct udevice_id mt7622_infracfg_compat[] = { + { .compatible = "mediatek,mt7622-infracfg", }, + { } +}; + +static const struct udevice_id mt7622_pericfg_compat[] = { + { .compatible = "mediatek,mt7622-pericfg", }, + { } +}; + +static const struct udevice_id mt7622_ethsys_compat[] = { + { .compatible = "mediatek,mt7622-ethsys", }, + { } +}; + +static const struct udevice_id mt7622_sgmiisys_compat[] = { + { .compatible = "mediatek,mt7622-sgmiisys", }, + { } +}; + +static const struct udevice_id mt7622_mcucfg_compat[] = { + { .compatible = "mediatek,mt7622-mcucfg" }, + { } +}; + +U_BOOT_DRIVER(mtk_mcucfg) = { + .name = "mt7622-mcucfg", + .id = UCLASS_SYSCON, + .of_match = mt7622_mcucfg_compat, + .probe = mt7622_mcucfg_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7622-clock-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt7622_apmixed_compat, + .probe = mt7622_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7622-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7622_topckgen_compat, + .probe = mt7622_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7622-clock-infracfg", + .id = UCLASS_CLK, + .of_match = mt7622_infracfg_compat, + .probe = mt7622_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_pericfg) = { + .name = "mt7622-clock-pericfg", + .id = UCLASS_CLK, + .of_match = mt7622_pericfg_compat, + .probe = mt7622_pericfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7622-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7622_ethsys_compat, + .probe = mt7622_ethsys_probe, + .bind = mt7622_ethsys_bind, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + +U_BOOT_DRIVER(mtk_clk_sgmiisys) = { + .name = "mt7622-clock-sgmiisys", + .id = UCLASS_CLK, + .of_match = mt7622_sgmiisys_compat, + .probe = mt7622_sgmiisys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 30a919f..858be85 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -539,6 +539,29 @@ static const struct mtk_gate sgmii_cgs[] = { GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5), }; +static const struct mtk_gate_regs ssusb_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_SSUSB(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &ssusb_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ +} + +static const struct mtk_gate ssusb_cgs[] = { + GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0), + GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1), + GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5), + GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6), + GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7), + GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8), +}; + static const struct mtk_clk_tree mt7629_clk_tree = { .xtal_rate = 40 * MHZ, .xtal2_rate = 20 * MHZ, @@ -621,6 +644,11 @@ static int mt7629_sgmiisys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs); } +static int mt7629_ssusbsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs); +} + static const struct udevice_id mt7629_apmixed_compat[] = { { .compatible = "mediatek,mt7629-apmixedsys" }, { } @@ -651,6 +679,11 @@ static const struct udevice_id mt7629_sgmiisys_compat[] = { { } }; +static const struct udevice_id mt7629_ssusbsys_compat[] = { + { .compatible = "mediatek,mt7629-ssusbsys" }, + { } +}; + static const struct udevice_id mt7629_mcucfg_compat[] = { { .compatible = "mediatek,mt7629-mcucfg" }, { } @@ -722,3 +755,12 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = { .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, }; + +U_BOOT_DRIVER(mtk_clk_ssusbsys) = { + .name = "mt7629-clock-ssusbsys", + .id = UCLASS_CLK, + .of_match = mt7629_ssusbsys_compat, + .probe = mt7629_ssusbsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c new file mode 100644 index 0000000..cb168f1 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8512.c @@ -0,0 +1,873 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT8512 SoC + * + * Copyright (C) 2019 BayLibre, SAS + * Author: Chen Zhong <chen.zhong@mediatek.com> + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <dt-bindings/clock/mt8512-clk.h> + +#include "clk-mtk.h" + +#define MT8512_PLL_FMAX (3800UL * MHZ) +#define MT8512_PLL_FMIN (1500UL * MHZ) +#define MT8512_CON0_RST_BAR BIT(23) + +/* apmixedsys */ +#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ + _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \ + .id = _id, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .rst_bar_mask = MT8512_CON0_RST_BAR, \ + .fmax = MT8512_PLL_FMAX, \ + .fmin = MT8512_PLL_FMIN, \ + .flags = _flags, \ + .pcwbits = _pcwbits, \ + .pcwibits = 8, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + } + +static const struct mtk_pll_data apmixed_plls[] = { + PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001, + 0, 22, 0x0310, 24, 0x0310, 0, 0), + PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001, + HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0), + PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001, + HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0), + PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001, + 0, 22, 0x0354, 24, 0x0354, 0, 0), + PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001, + 0, 32, 0x0320, 24, 0x0324, 0, 0x0320), + PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001, + 0, 32, 0x0364, 24, 0x0368, 0, 0x0364), + PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001, + 0, 22, 0x0378, 24, 0x0378, 0, 0), + PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001, + 0, 22, 0x0394, 24, 0x0394, 0, 0), + PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001, + 0, 22, 0x03A4, 24, 0x03A4, 0, 0), +}; + +/* topckgen */ +#define FACTOR0(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define FACTOR1(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define FACTOR2(_id, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, 0) + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000), + FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000), +}; + +static const struct mtk_fixed_factor top_fixed_divs[] = { + FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4), + FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8), + FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16), + FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32), + FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), + FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6), + FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12), + FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24), + FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), + FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20), + FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), + FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14), + FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2), + FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4), + FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8), + FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16), + FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3), + FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6), + FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12), + FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24), + FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5), + FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10), + FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20), + FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2), + FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4), + FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8), + FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16), + FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32), + FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64), + FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13), + FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2), + FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4), + FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1), + FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2), + FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3), + FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4), + FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8), + FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16), + FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1), + FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2), + FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3), + FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4), + FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8), + FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16), + FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), + FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2), + FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1), + FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2), + FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1), + FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2), + FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4), + FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8), + FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1), + FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2), + FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2), +}; + +static const int axi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int mem_parents[] = { + CLK_TOP_DSPPLL, + CLK_TOP_IPPLL, + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3 +}; + +static const int uart_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int spi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int spis_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYSPLL4_D2 +}; + +static const int msdc50_0_hc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL2_D2 +}; + +static const int msdc50_0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int msdc50_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_MSDCPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int audio_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL2_D4 +}; + +static const int aud_intbus_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_APLL2_D8, + CLK_TOP_SYS_26M_D2, + CLK_TOP_APLL1_D8, + CLK_TOP_UNIVPLL3_D4 +}; + +static const int hapll1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1, + CLK_TOP_APLL1_D2, + CLK_TOP_APLL1_D3, + CLK_TOP_APLL1_D4, + CLK_TOP_APLL1_D8, + CLK_TOP_APLL1_D16, + CLK_TOP_SYS_26M_D2 +}; + +static const int hapll2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2, + CLK_TOP_APLL2_D2, + CLK_TOP_APLL2_D3, + CLK_TOP_APLL2_D4, + CLK_TOP_APLL2_D8, + CLK_TOP_APLL2_D16, + CLK_TOP_SYS_26M_D2 +}; + +static const int asm_l_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL_D5 +}; + +static const int aud_spdif_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D2, + CLK_TOP_DSPPLL +}; + +static const int aud_1_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL1 +}; + +static const int aud_2_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_APLL2 +}; + +static const int ssusb_sys_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2 +}; + +static const int spm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D8 +}; + +static const int i2c_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYS_26M_D2, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL3_D2, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_CLK32K +}; + +static const int pwm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int dsp_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_DSPPLL_D2, + CLK_TOP_DSPPLL_D4, + CLK_TOP_DSPPLL_D8, + CLK_TOP_APLL2_D4, + CLK_TOP_SYS_26M_D2, + CLK_TOP_CLK32K +}; + +static const int nfi2x_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_SYSPLL_D7, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_MSDCPLL_D2, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5 +}; + +static const int spinfi_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D8, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL4_D2, + CLK_TOP_SYSPLL2_D4, + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL3_D2 +}; + +static const int ecc_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL_D3 +}; + +static const int gcpu_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_UNIVPLL2_D2 +}; + +static const int gcpu_cpm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4 +}; + +static const int mbist_diag_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYS_26M_D2 +}; + +static const int ip0_nna_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_DSPPLL_D2, + CLK_TOP_DSPPLL_D4, + CLK_TOP_IPPLL, + CLK_TOP_SYS_26M_D2, + CLK_TOP_IPPLL_D2, + CLK_TOP_MSDCPLL_D2 +}; + +static const int ip2_wfst_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL2_D2, + CLK_TOP_IPPLL, + CLK_TOP_IPPLL_D2, + CLK_TOP_SYS_26M_D2, + CLK_TOP_MSDCPLL +}; + +static const int sflash_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL1_D16, + CLK_TOP_SYSPLL2_D8, + CLK_TOP_SYSPLL3_D4, + CLK_TOP_UNIVPLL3_D4, + CLK_TOP_UNIVPLL1_D8, + CLK_TOP_USB20_192M_D2, + CLK_TOP_UNIVPLL2_D4 +}; + +static const int sram_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_DSPPLL, + CLK_TOP_UNIVPLL_D3, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_APLL1, + CLK_TOP_APLL2, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_SYS_26M_D2 +}; + +static const int mm_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_SYSPLL_D3, + CLK_TOP_SYSPLL1_D2, + CLK_TOP_SYSPLL_D5, + CLK_TOP_SYSPLL1_D4, + CLK_TOP_UNIVPLL_D5, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D3 +}; + +static const int dpi0_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_TCONPLL_D2, + CLK_TOP_TCONPLL_D4, + CLK_TOP_TCONPLL_D8, + CLK_TOP_TCONPLL_D16, + CLK_TOP_TCONPLL_D32, + CLK_TOP_TCONPLL_D64 +}; + +static const int dbg_atclk_parents[] = { + CLK_TOP_CLK26M, + CLK_TOP_UNIVPLL1_D2, + CLK_TOP_UNIVPLL_D5 +}; + +static const int occ_104m_parents[] = { + CLK_TOP_UNIVPLL2_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int occ_68m_parents[] = { + CLK_TOP_SYSPLL1_D8, + CLK_TOP_UNIVPLL2_D8 +}; + +static const int occ_182m_parents[] = { + CLK_TOP_SYSPLL2_D2, + CLK_TOP_UNIVPLL1_D4, + CLK_TOP_UNIVPLL2_D8 +}; + +static const struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, + 0x040, 0x044, 0x048, 0, 3, 7, + 0x4, 0, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents, + 0x040, 0x044, 0x048, 8, 2, 15, + 0x4, 1, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents, + 0x040, 0x044, 0x048, 16, 1, 23, + 0x4, 2, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents, + 0x040, 0x044, 0x048, 24, 3, 31, + 0x4, 3, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_1 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents, + 0x050, 0x054, 0x058, 0, 3, 7, + 0x4, 4, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents, + 0x050, 0x054, 0x058, 8, 2, 15, + 0x4, 5, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents, + 0x050, 0x054, 0x058, 16, 2, 23, + 0x4, 6, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents, + 0x050, 0x054, 0x058, 24, 3, 31, + 0x4, 7, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_2 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents, + 0x060, 0x064, 0x068, 0, 3, 7, + 0x4, 8, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents, + 0x060, 0x064, 0x068, 8, 3, 15, + 0x4, 9, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents, + 0x060, 0x064, 0x068, 16, 2, 23, + 0x4, 10, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, + 0x060, 0x064, 0x068, 24, 3, 31, + 0x4, 11, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_3 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents, + 0x070, 0x074, 0x078, 0, 3, 7, + 0x4, 12, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents, + 0x070, 0x074, 0x078, 8, 3, 15, + 0x4, 13, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents, + 0x070, 0x074, 0x078, 16, 3, 23, + 0x4, 14, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents, + 0x070, 0x074, 0x078, 24, 3, 31, + 0x4, 15, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_4 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 0, 2, 7, + 0x4, 16, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 8, 2, 15, + 0x4, 17, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents, + 0x080, 0x084, 0x088, 16, 2, 23, + 0x4, 18, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents, + 0x080, 0x084, 0x088, 24, 2, 31, + 0x4, 19, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_5 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents, + 0x090, 0x094, 0x098, 0, 1, 7, + 0x4, 20, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents, + 0x090, 0x094, 0x098, 8, 1, 15, + 0x4, 21, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents, + 0x090, 0x094, 0x098, 16, 2, 23, + 0x4, 22, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents, + 0x090, 0x094, 0x098, 24, 2, 31, + 0x4, 23, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_6 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents, + 0x0a0, 0x0a4, 0x0a8, 0, 1, 7, + 0x4, 24, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents, + 0x0a0, 0x0a4, 0x0a8, 8, 3, 15, + 0x4, 25, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents, + 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, + 0x4, 26, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents, + 0x0a0, 0x0a4, 0x0a8, 24, 3, 31, + 0x4, 27, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_7 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents, + 0x0b0, 0x0b4, 0x0b8, 0, 3, 7, + 0x4, 28, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents, + 0x0b0, 0x0b4, 0x0b8, 8, 3, 15, + 0x4, 29, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents, + 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, + 0x4, 30, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents, + 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, + 0x4, 31, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_8 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents, + 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, + 0x8, 0, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents, + 0x0c0, 0x0c4, 0x0c8, 8, 1, 15, + 0x8, 1, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents, + 0x0c0, 0x0c4, 0x0c8, 16, 3, 23, + 0x8, 2, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents, + 0x0c0, 0x0c4, 0x0c8, 24, 3, 31, + 0x8, 3, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_9 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents, + 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, + 0x8, 4, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents, + 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, + 0x8, 5, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents, + 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, + 0x8, 6, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents, + 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, + 0x8, 7, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_10 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents, + 0x0e0, 0x0e4, 0x0e8, 0, 3, 7, + 0x8, 8, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, + 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, + 0x8, 9, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents, + 0x0e0, 0x0e4, 0x0e8, 16, 1, 23, + 0x8, 10, CLK_MUX_SETCLR_UPD), + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents, + 0x0e0, 0x0e4, 0x0e8, 24, 1, 31, + 0x8, 11, CLK_MUX_SETCLR_UPD), + /* CLK_CFG_11 */ + MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents, + 0x0ec, 0x0f0, 0x0f4, 0, 2, 7, + 0x8, 12, CLK_MUX_SETCLR_UPD), +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x104, + .sta_ofs = 0x104, +}; + +#define GATE_TOP0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_TOP1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &top1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate top_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10), + GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11), + GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16), + GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17), + /* TOP1 */ + GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9), + GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22), + GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x294, + .clr_ofs = 0x294, + .sta_ofs = 0x294, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs infra3_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs infra4_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +static const struct mtk_gate_regs infra5_cg_regs = { + .set_ofs = 0xd0, + .clr_ofs = 0xd4, + .sta_ofs = 0xd8, +}; + +#define GATE_INFRA0(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra0_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA1(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra1_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA2(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra2_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA3(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra3_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA4(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra4_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +#define GATE_INFRA5(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &infra5_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6), + GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8), + GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9), + GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10), + GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15), + GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16), + GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17), + GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18), + GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19), + GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20), + GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21), + GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22), + GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23), + GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24), + GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26), + GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27), + GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28), + GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1), + GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2), + GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4), + GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7), + GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8), + GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9), + GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10), + GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14), + GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18), + GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24), + GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25), + GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29), + /* INFRA3 */ + GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0), + GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1), + GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3), + GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4), + GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6), + GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27), + /* INFRA4 */ + GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7), + GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8), + GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9), + GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10), + GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22), + GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23), + GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24), + GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25), + GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26), + /* INFRA5 */ + GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1), + GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2), + GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3), + GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7), + GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9), + GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11), +}; + +static const struct mtk_clk_tree mt8512_clk_tree = { + .xtal_rate = 26 * MHZ, + .xtal2_rate = 26 * MHZ, + .fdivs_offs = CLK_TOP_SYSPLL1_D2, + .muxes_offs = CLK_TOP_AXI_SEL, + .plls = apmixed_plls, + .fclks = top_fixed_clks, + .fdivs = top_fixed_divs, + .muxes = top_muxes, +}; + +static int mt8512_apmixedsys_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8512_clk_tree); +} + +static int mt8512_topckgen_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt8512_clk_tree); +} + +static int mt8512_topckgen_cg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks); +} + +static int mt8512_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks); +} + +static const struct udevice_id mt8512_apmixed_compat[] = { + { .compatible = "mediatek,mt8512-apmixedsys", }, + { } +}; + +static const struct udevice_id mt8512_topckgen_compat[] = { + { .compatible = "mediatek,mt8512-topckgen", }, + { } +}; + +static const struct udevice_id mt8512_topckgen_cg_compat[] = { + { .compatible = "mediatek,mt8512-topckgen-cg", }, + { } +}; + +static const struct udevice_id mt8512_infracfg_compat[] = { + { .compatible = "mediatek,mt8512-infracfg", }, + { } +}; + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt8512-apmixedsys", + .id = UCLASS_CLK, + .of_match = mt8512_apmixed_compat, + .probe = mt8512_apmixedsys_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_apmixedsys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt8512-topckgen", + .id = UCLASS_CLK, + .of_match = mt8512_topckgen_compat, + .probe = mt8512_topckgen_probe, + .priv_auto_alloc_size = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { + .name = "mt8512-topckgen-cg", + .id = UCLASS_CLK, + .of_match = mt8512_topckgen_cg_compat, + .probe = mt8512_topckgen_cg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt8512-infracfg", + .id = UCLASS_CLK, + .of_match = mt8512_infracfg_compat, + .probe = mt8512_infracfg_probe, + .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 6c6b500..09ae2d4 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -39,7 +39,7 @@ * this function is recursively called to find the parent to calculate * the accurate frequency. */ -static int mtk_clk_find_parent_rate(struct clk *clk, int id, +static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, const struct driver *drv) { struct clk parent = { .id = id, }; @@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent, if (++index == mux->num_parents) return -EINVAL; - /* switch mux to a select parent */ - val = readl(base + mux->mux_reg); - val &= ~(mux->mux_mask << mux->mux_shift); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = (mux->mux_mask << mux->mux_shift); + writel(val, base + mux->mux_clr_reg); - val |= index << mux->mux_shift; - writel(val, base + mux->mux_reg); + val = (index << mux->mux_shift); + writel(val, base + mux->mux_set_reg); + + if (mux->upd_shift >= 0) + writel(BIT(mux->upd_shift), base + mux->upd_reg); + } else { + /* switch mux to a select parent */ + val = readl(base + mux->mux_reg); + val &= ~(mux->mux_mask << mux->mux_shift); + + val |= index << mux->mux_shift; + writel(val, base + mux->mux_reg); + } return 0; } @@ -84,11 +95,13 @@ static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, { int pcwbits = pll->pcwbits; int pcwfbits; + int ibits; u64 vco; u8 c = 0; /* The fractional part of the PLL divider. */ - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; + ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; vco = (u64)fin * pcw; @@ -113,7 +126,7 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; - u32 val; + u32 val, chg; /* set postdiv */ val = readl(priv->base + pll->pd_reg); @@ -129,11 +142,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) /* set pcw */ val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); val |= pcw << pll->pcw_shift; - val &= ~CON1_PCW_CHG; - writel(val, priv->base + pll->pcw_reg); - val |= CON1_PCW_CHG; - writel(val, priv->base + pll->pcw_reg); + if (pll->pcw_chg_reg) { + chg = readl(priv->base + pll->pcw_chg_reg); + chg |= CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + writel(chg, priv->base + pll->pcw_chg_reg); + } else { + val |= CON1_PCW_CHG; + writel(val, priv->base + pll->pcw_reg); + } udelay(20); } @@ -150,8 +168,9 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_pll_data *pll = &priv->tree->plls[clk->id]; - unsigned long fmin = 1000 * MHZ; + unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ; u64 _pcw; + int ibits; u32 val; if (freq > pll->fmax) @@ -164,7 +183,8 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, } /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */ - _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS); + ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; + _pcw = ((u64)freq << val) << (pll->pcwbits - ibits); do_div(_pcw, priv->tree->xtal2_rate); *pcw = (u32)_pcw; @@ -265,7 +285,7 @@ static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, return rate; } -static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; @@ -287,7 +307,7 @@ static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off) return mtk_factor_recalc_rate(fdiv, rate); } -static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) +static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux = &priv->tree->muxes[off]; @@ -332,9 +352,14 @@ static int mtk_topckgen_enable(struct clk *clk) return 0; /* enable clock gate */ - val = readl(priv->base + mux->gate_reg); - val &= ~BIT(mux->gate_shift); - writel(val, priv->base + mux->gate_reg); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = BIT(mux->gate_shift); + writel(val, priv->base + mux->mux_clr_reg); + } else { + val = readl(priv->base + mux->gate_reg); + val &= ~BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + } if (mux->flags & CLK_DOMAIN_SCPSYS) { /* enable scpsys clock off control */ @@ -360,9 +385,14 @@ static int mtk_topckgen_disable(struct clk *clk) return 0; /* disable clock gate */ - val = readl(priv->base + mux->gate_reg); - val |= BIT(mux->gate_shift); - writel(val, priv->base + mux->gate_reg); + if (mux->flags & CLK_MUX_SETCLR_UPD) { + val = BIT(mux->gate_shift); + writel(val, priv->base + mux->mux_set_reg); + } else { + val = readl(priv->base + mux->gate_reg); + val |= BIT(mux->gate_shift); + writel(val, priv->base + mux->gate_reg); + } return 0; } diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index dce9325..c7dc980 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -12,6 +12,7 @@ #define HAVE_RST_BAR BIT(0) #define CLK_DOMAIN_SCPSYS BIT(0) +#define CLK_MUX_SETCLR_UPD BIT(1) #define CLK_GATE_SETCLR BIT(0) #define CLK_GATE_SETCLR_INV BIT(1) @@ -36,9 +37,12 @@ struct mtk_pll_data { u32 flags; u32 rst_bar_mask; u64 fmax; + u64 fmin; int pcwbits; + int pcwibits; u32 pcw_reg; int pcw_shift; + u32 pcw_chg_reg; }; /** @@ -102,9 +106,13 @@ struct mtk_composite { const int id; const int *parent; u32 mux_reg; + u32 mux_set_reg; + u32 mux_clr_reg; + u32 upd_reg; u32 gate_reg; u32 mux_mask; signed char mux_shift; + signed char upd_shift; signed char gate_shift; signed char num_parents; u16 flags; @@ -137,6 +145,24 @@ struct mtk_composite { .flags = 0, \ } +#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ + _mux_clr_ofs, _shift, _width, _gate, \ + _upd_ofs, _upd, _flags) { \ + .id = _id, \ + .mux_reg = _mux_ofs, \ + .mux_set_reg = _mux_set_ofs, \ + .mux_clr_reg = _mux_clr_ofs, \ + .upd_reg = _upd_ofs, \ + .upd_shift = _upd, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _mux_ofs, \ + .gate_shift = _gate, \ + .parent = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = _flags, \ + } + struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index eaa584a..d487081 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -12,8 +12,8 @@ #include <mmc.h> #include <errno.h> #include <malloc.h> +#include <mapmem.h> #include <stdbool.h> -#include <watchdog.h> #include <asm/gpio.h> #include <dm/pinctrl.h> #include <linux/bitops.h> @@ -135,6 +135,25 @@ #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) +/* EMMC_TOP_CONTROL mask */ +#define PAD_RXDLY_SEL BIT(0) +#define DELAY_EN BIT(1) +#define PAD_DAT_RD_RXDLY2 (0x1f << 2) +#define PAD_DAT_RD_RXDLY (0x1f << 7) +#define PAD_DAT_RD_RXDLY_S 7 +#define PAD_DAT_RD_RXDLY2_SEL BIT(12) +#define PAD_DAT_RD_RXDLY_SEL BIT(13) +#define DATA_K_VALUE_SEL BIT(14) +#define SDC_RX_ENH_EN BIT(15) + +/* EMMC_TOP_CMD mask */ +#define PAD_CMD_RXDLY2 (0x1f << 0) +#define PAD_CMD_RXDLY (0x1f << 5) +#define PAD_CMD_RXDLY_S 5 +#define PAD_CMD_RD_RXDLY2_SEL BIT(10) +#define PAD_CMD_RD_RXDLY_SEL BIT(11) +#define PAD_CMD_TX_DLY (0x1f << 12) + /* SDC_CFG_BUSWIDTH */ #define MSDC_BUS_1BITS 0x0 #define MSDC_BUS_4BITS 0x1 @@ -219,6 +238,21 @@ struct mtk_sd_regs { u32 sdc_fifo_cfg; }; +struct msdc_top_regs { + u32 emmc_top_control; + u32 emmc_top_cmd; + u32 emmc50_pad_ctl0; + u32 emmc50_pad_ds_tune; + u32 emmc50_pad_dat0_tune; + u32 emmc50_pad_dat1_tune; + u32 emmc50_pad_dat2_tune; + u32 emmc50_pad_dat3_tune; + u32 emmc50_pad_dat4_tune; + u32 emmc50_pad_dat5_tune; + u32 emmc50_pad_dat6_tune; + u32 emmc50_pad_dat7_tune; +}; + struct msdc_compatible { u8 clk_div_bits; u8 sclk_cycle_shift; @@ -249,6 +283,7 @@ struct msdc_tune_para { struct msdc_host { struct mtk_sd_regs *base; + struct msdc_top_regs *top_base; struct mmc *mmc; struct msdc_compatible *dev_comp; @@ -495,6 +530,7 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd, blocks = data->blocks; writel(CMD_INTS_MASK, &host->base->msdc_int); + writel(DATA_INTS_MASK, &host->base->msdc_int); writel(blocks, &host->base->sdc_blk_num); writel(cmd->cmdarg, &host->base->sdc_arg); writel(rawcmd, &host->base->sdc_cmd); @@ -641,13 +677,9 @@ static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) u32 size; int ret; - WATCHDOG_RESET(); - if (data->flags == MMC_DATA_WRITE) host->last_data_write = 1; - writel(DATA_INTS_MASK, &host->base->msdc_int); - size = data->blocks * data->blocksize; if (data->flags == MMC_DATA_WRITE) @@ -964,6 +996,36 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) return delay_phase; } +static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) +{ + void __iomem *tune_reg = &host->base->pad_tune; + + if (host->dev_comp->pad_tune0) + tune_reg = &host->base->pad_tune0; + + if (host->top_base) + clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY, + value << PAD_CMD_RXDLY_S); + else + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, + value << MSDC_PAD_TUNE_CMDRDLY_S); +} + +static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) +{ + void __iomem *tune_reg = &host->base->pad_tune; + + if (host->dev_comp->pad_tune0) + tune_reg = &host->base->pad_tune0; + + if (host->top_base) + clrsetbits_le32(&host->top_base->emmc_top_control, + PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S); + else + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, + value << MSDC_PAD_TUNE_DATRRDLY_S); +} + static int hs400_tune_response(struct udevice *dev, u32 opcode) { struct msdc_plat *plat = dev_get_platdata(dev); @@ -1010,7 +1072,7 @@ static int hs400_tune_response(struct udevice *dev, u32 opcode) PAD_CMD_TUNE_RX_DLY3_S); final_delay = final_cmd_delay.final_phase; - dev_err(dev, "Final cmd pad delay: %x\n", final_delay); + dev_info(dev, "Final cmd pad delay: %x\n", final_delay); return final_delay == 0xff ? -EIO : 0; } @@ -1217,21 +1279,14 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode) u32 rise_delay = 0, fall_delay = 0; struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; u8 final_delay, final_maxlen; - void __iomem *tune_reg = &host->base->pad_tune; int i, ret; - if (host->dev_comp->pad_tune0) - tune_reg = &host->base->pad_tune0; - clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); for (i = 0; i < PAD_DELAY_MAX; i++) { - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - i << MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - i << MSDC_PAD_TUNE_DATRRDLY_S); - + msdc_set_cmd_delay(host, i); + msdc_set_data_delay(host, i); ret = mmc_send_tuning(mmc, opcode, NULL); if (!ret) rise_delay |= (1 << i); @@ -1246,11 +1301,8 @@ static int msdc_tune_together(struct udevice *dev, u32 opcode) setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); for (i = 0; i < PAD_DELAY_MAX; i++) { - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - i << MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - i << MSDC_PAD_TUNE_DATRRDLY_S); - + msdc_set_cmd_delay(host, i); + msdc_set_data_delay(host, i); ret = mmc_send_tuning(mmc, opcode, NULL); if (!ret) fall_delay |= (1 << i); @@ -1263,27 +1315,17 @@ skip_fall: if (final_maxlen == final_rise_delay.maxlen) { clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - final_rise_delay.final_phase << - MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - final_rise_delay.final_phase << - MSDC_PAD_TUNE_DATRRDLY_S); final_delay = final_rise_delay.final_phase; } else { setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, - final_fall_delay.final_phase << - MSDC_PAD_TUNE_CMDRDLY_S); - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, - final_fall_delay.final_phase << - MSDC_PAD_TUNE_DATRRDLY_S); final_delay = final_fall_delay.final_phase; } - dev_err(dev, "Final pad delay: %x\n", final_delay); + msdc_set_cmd_delay(host, final_delay); + msdc_set_data_delay(host, final_delay); + dev_info(dev, "Final pad delay: %x\n", final_delay); return final_delay == 0xff ? -EIO : 0; } @@ -1400,8 +1442,12 @@ static void msdc_init_hw(struct msdc_host *host) 3 << MSDC_PB2_RESPWAIT_S); if (host->dev_comp->enhance_rx) { - setbits_le32(&host->base->sdc_adv_cfg0, - SDC_RX_ENHANCE_EN); + if (host->top_base) + setbits_le32(&host->top_base->emmc_top_control, + SDC_RX_ENH_EN); + else + setbits_le32(&host->base->sdc_adv_cfg0, + SDC_RX_ENHANCE_EN); } else { clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPSTSENSEL_M, @@ -1476,7 +1522,6 @@ static int msdc_drv_probe(struct udevice *dev) cfg->f_min = host->src_clk_freq / (4 * 255); else cfg->f_min = host->src_clk_freq / (4 * 4095); - cfg->f_max = host->src_clk_freq / 2; cfg->b_max = 1024; cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; @@ -1502,11 +1547,19 @@ static int msdc_ofdata_to_platdata(struct udevice *dev) struct msdc_plat *plat = dev_get_platdata(dev); struct msdc_host *host = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; + fdt_addr_t base, top_base; int ret; - host->base = (void *)dev_read_addr(dev); - if (!host->base) + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) return -EINVAL; + host->base = map_sysmem(base, 0); + + top_base = dev_read_addr_index(dev, 1); + if (top_base == FDT_ADDR_T_NONE) + host->top_base = NULL; + else + host->top_base = map_sysmem(top_base, 0); ret = mmc_of_parse(dev, cfg); if (ret) @@ -1568,6 +1621,15 @@ static const struct msdc_compatible mt7620_compat = { .enhance_rx = false }; +static const struct msdc_compatible mt7622_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, +}; + static const struct msdc_compatible mt7623_compat = { .clk_div_bits = 12, .sclk_cycle_shift = 20, @@ -1579,6 +1641,16 @@ static const struct msdc_compatible mt7623_compat = { .enhance_rx = false }; +static const struct msdc_compatible mt8512_compat = { + .clk_div_bits = 12, + .sclk_cycle_shift = 20, + .pad_tune0 = true, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, +}; + static const struct msdc_compatible mt8516_compat = { .clk_div_bits = 12, .sclk_cycle_shift = 20, @@ -1601,7 +1673,9 @@ static const struct msdc_compatible mt8183_compat = { static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat }, + { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, + { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat }, {} diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c index 3701481..fd33062 100644 --- a/drivers/phy/phy-mtk-tphy.c +++ b/drivers/phy/phy-mtk-tphy.c @@ -204,9 +204,8 @@ static int mtk_phy_init(struct phy *phy) struct mtk_phy_instance *instance = tphy->phys[phy->id]; int ret; - /* we may use a fixed-clock here */ ret = clk_enable(&instance->ref_clk); - if (ret && ret != -ENOSYS) + if (ret) return ret; switch (instance->type) { @@ -339,7 +338,8 @@ static int mtk_tphy_probe(struct udevice *dev) tphy->phys[index] = instance; index++; - err = clk_get_by_index_nodev(subnode, 0, &instance->ref_clk); + err = clk_get_optional_nodev(subnode, "ref", + &instance->ref_clk); if (err) return err; } diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 22ee623..58df508 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -4,6 +4,10 @@ config PINCTRL_MTK depends on PINCTRL_GENERIC bool +config PINCTRL_MT7622 + bool "MT7622 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT7623 bool "MT7623 SoC pinctrl driver" select PINCTRL_MTK @@ -12,6 +16,10 @@ config PINCTRL_MT7629 bool "MT7629 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT8512 + bool "MT8512 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT8516 bool "MT8516 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 0ab7b15..d7e8cf1 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -3,7 +3,9 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o # SoC Drivers +obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c new file mode 100644 index 0000000..1aa323c --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1) + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = { + PIN_FIELD(0, 0, 0x320, 0x10, 16, 4), + PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4), + PIN_FIELD(5, 5, 0x320, 0x10, 0, 4), + PINS_FIELD(6, 7, 0x300, 0x10, 4, 4), + PIN_FIELD(8, 9, 0x350, 0x10, 20, 4), + PINS_FIELD(10, 13, 0x300, 0x10, 8, 4), + PIN_FIELD(14, 15, 0x320, 0x10, 4, 4), + PIN_FIELD(16, 17, 0x320, 0x10, 20, 4), + PIN_FIELD(18, 21, 0x310, 0x10, 16, 4), + PIN_FIELD(22, 22, 0x380, 0x10, 16, 4), + PINS_FIELD(23, 24, 0x300, 0x10, 24, 4), + PINS_FIELD(25, 36, 0x300, 0x10, 12, 4), + PINS_FIELD(37, 50, 0x300, 0x10, 20, 4), + PIN_FIELD(51, 70, 0x330, 0x10, 4, 4), + PINS_FIELD(71, 72, 0x300, 0x10, 16, 4), + PIN_FIELD(73, 76, 0x310, 0x10, 0, 4), + PIN_FIELD(77, 77, 0x320, 0x10, 28, 4), + PIN_FIELD(78, 78, 0x320, 0x10, 12, 4), + PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4), + PIN_FIELD(83, 83, 0x350, 0x10, 28, 4), + PIN_FIELD(84, 84, 0x330, 0x10, 0, 4), + PIN_FIELD(85, 90, 0x360, 0x10, 4, 4), + PIN_FIELD(91, 94, 0x390, 0x10, 16, 4), + PIN_FIELD(95, 97, 0x380, 0x10, 20, 4), + PIN_FIELD(98, 101, 0x390, 0x10, 0, 4), + PIN_FIELD(102, 102, 0x360, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = { + PIN_FIELD(0, 102, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_di_range[] = { + PIN_FIELD(0, 102, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_do_range[] = { + PIN_FIELD(0, 102, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = { + PIN_FIELD(0, 31, 0x920, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x820, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = { + PIN_FIELD(0, 31, 0x930, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x830, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = { + PIN_FIELD(0, 31, 0x940, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x840, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = { + PIN_FIELD(0, 31, 0x960, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x860, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = { + PIN_FIELD(0, 31, 0x970, 0x10, 0, 1), + PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1), + PIN_FIELD(51, 70, 0x870, 0x10, 0, 1), + PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1), + PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1), + PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1), + PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1), +}; + +static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range), + [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range), + [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range), +}; + +static const struct mtk_pin_desc mt7622_pins[] = { + MT7622_PIN(0, "GPIO_A"), + MT7622_PIN(1, "I2S1_IN"), + MT7622_PIN(2, "I2S1_OUT"), + MT7622_PIN(3, "I2S_BCLK"), + MT7622_PIN(4, "I2S_WS"), + MT7622_PIN(5, "I2S_MCLK"), + MT7622_PIN(6, "TXD0"), + MT7622_PIN(7, "RXD0"), + MT7622_PIN(8, "SPI_WP"), + MT7622_PIN(9, "SPI_HOLD"), + MT7622_PIN(10, "SPI_CLK"), + MT7622_PIN(11, "SPI_MOSI"), + MT7622_PIN(12, "SPI_MISO"), + MT7622_PIN(13, "SPI_CS"), + MT7622_PIN(14, "I2C_SDA"), + MT7622_PIN(15, "I2C_SCL"), + MT7622_PIN(16, "I2S2_IN"), + MT7622_PIN(17, "I2S3_IN"), + MT7622_PIN(18, "I2S4_IN"), + MT7622_PIN(19, "I2S2_OUT"), + MT7622_PIN(20, "I2S3_OUT"), + MT7622_PIN(21, "I2S4_OUT"), + MT7622_PIN(22, "GPIO_B"), + MT7622_PIN(23, "MDC"), + MT7622_PIN(24, "MDIO"), + MT7622_PIN(25, "G2_TXD0"), + MT7622_PIN(26, "G2_TXD1"), + MT7622_PIN(27, "G2_TXD2"), + MT7622_PIN(28, "G2_TXD3"), + MT7622_PIN(29, "G2_TXEN"), + MT7622_PIN(30, "G2_TXC"), + MT7622_PIN(31, "G2_RXD0"), + MT7622_PIN(32, "G2_RXD1"), + MT7622_PIN(33, "G2_RXD2"), + MT7622_PIN(34, "G2_RXD3"), + MT7622_PIN(35, "G2_RXDV"), + MT7622_PIN(36, "G2_RXC"), + MT7622_PIN(37, "NCEB"), + MT7622_PIN(38, "NWEB"), + MT7622_PIN(39, "NREB"), + MT7622_PIN(40, "NDL4"), + MT7622_PIN(41, "NDL5"), + MT7622_PIN(42, "NDL6"), + MT7622_PIN(43, "NDL7"), + MT7622_PIN(44, "NRB"), + MT7622_PIN(45, "NCLE"), + MT7622_PIN(46, "NALE"), + MT7622_PIN(47, "NDL0"), + MT7622_PIN(48, "NDL1"), + MT7622_PIN(49, "NDL2"), + MT7622_PIN(50, "NDL3"), + MT7622_PIN(51, "MDI_TP_P0"), + MT7622_PIN(52, "MDI_TN_P0"), + MT7622_PIN(53, "MDI_RP_P0"), + MT7622_PIN(54, "MDI_RN_P0"), + MT7622_PIN(55, "MDI_TP_P1"), + MT7622_PIN(56, "MDI_TN_P1"), + MT7622_PIN(57, "MDI_RP_P1"), + MT7622_PIN(58, "MDI_RN_P1"), + MT7622_PIN(59, "MDI_RP_P2"), + MT7622_PIN(60, "MDI_RN_P2"), + MT7622_PIN(61, "MDI_TP_P2"), + MT7622_PIN(62, "MDI_TN_P2"), + MT7622_PIN(63, "MDI_TP_P3"), + MT7622_PIN(64, "MDI_TN_P3"), + MT7622_PIN(65, "MDI_RP_P3"), + MT7622_PIN(66, "MDI_RN_P3"), + MT7622_PIN(67, "MDI_RP_P4"), + MT7622_PIN(68, "MDI_RN_P4"), + MT7622_PIN(69, "MDI_TP_P4"), + MT7622_PIN(70, "MDI_TN_P4"), + MT7622_PIN(71, "PMIC_SCL"), + MT7622_PIN(72, "PMIC_SDA"), + MT7622_PIN(73, "SPIC1_CLK"), + MT7622_PIN(74, "SPIC1_MOSI"), + MT7622_PIN(75, "SPIC1_MISO"), + MT7622_PIN(76, "SPIC1_CS"), + MT7622_PIN(77, "GPIO_D"), + MT7622_PIN(78, "WATCHDOG"), + MT7622_PIN(79, "RTS3_N"), + MT7622_PIN(80, "CTS3_N"), + MT7622_PIN(81, "TXD3"), + MT7622_PIN(82, "RXD3"), + MT7622_PIN(83, "PERST0_N"), + MT7622_PIN(84, "PERST1_N"), + MT7622_PIN(85, "WLED_N"), + MT7622_PIN(86, "EPHY_LED0_N"), + MT7622_PIN(87, "AUXIN0"), + MT7622_PIN(88, "AUXIN1"), + MT7622_PIN(89, "AUXIN2"), + MT7622_PIN(90, "AUXIN3"), + MT7622_PIN(91, "TXD4"), + MT7622_PIN(92, "RXD4"), + MT7622_PIN(93, "RTS4_N"), + MT7622_PIN(94, "CTS4_N"), + MT7622_PIN(95, "PWM1"), + MT7622_PIN(96, "PWM2"), + MT7622_PIN(97, "PWM3"), + MT7622_PIN(98, "PWM4"), + MT7622_PIN(99, "PWM5"), + MT7622_PIN(100, "PWM6"), + MT7622_PIN(101, "PWM7"), + MT7622_PIN(102, "GPIO_E"), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. The + * hardware probably has multiple combinations of these pinouts. + */ + +/* EMMC */ +static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; +static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; + +static int mt7622_emmc_rst_pins[] = { 37, }; +static int mt7622_emmc_rst_funcs[] = { 1, }; + +/* LED for EPHY */ +static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; +static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; +static int mt7622_ephy0_led_pins[] = { 86, }; +static int mt7622_ephy0_led_funcs[] = { 0, }; +static int mt7622_ephy1_led_pins[] = { 91, }; +static int mt7622_ephy1_led_funcs[] = { 2, }; +static int mt7622_ephy2_led_pins[] = { 92, }; +static int mt7622_ephy2_led_funcs[] = { 2, }; +static int mt7622_ephy3_led_pins[] = { 93, }; +static int mt7622_ephy3_led_funcs[] = { 2, }; +static int mt7622_ephy4_led_pins[] = { 94, }; +static int mt7622_ephy4_led_funcs[] = { 2, }; + +/* Embedded Switch */ +static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, + 62, 63, 64, 65, 66, 67, 68, 69, 70, }; +static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; +static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, }; +static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, }; +/* RGMII via ESW */ +static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 70, }; +static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* RGMII via GMAC1 */ +static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, + 67, 68, 69, 70, }; +static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, }; + +/* RGMII via GMAC2 */ +static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, + 33, 34, 35, 36, }; +static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* I2C */ +static int mt7622_i2c0_pins[] = { 14, 15, }; +static int mt7622_i2c0_funcs[] = { 0, 0, }; +static int mt7622_i2c1_0_pins[] = { 55, 56, }; +static int mt7622_i2c1_0_funcs[] = { 0, 0, }; +static int mt7622_i2c1_1_pins[] = { 73, 74, }; +static int mt7622_i2c1_1_funcs[] = { 3, 3, }; +static int mt7622_i2c1_2_pins[] = { 87, 88, }; +static int mt7622_i2c1_2_funcs[] = { 0, 0, }; +static int mt7622_i2c2_0_pins[] = { 57, 58, }; +static int mt7622_i2c2_0_funcs[] = { 0, 0, }; +static int mt7622_i2c2_1_pins[] = { 75, 76, }; +static int mt7622_i2c2_1_funcs[] = { 3, 3, }; +static int mt7622_i2c2_2_pins[] = { 89, 90, }; +static int mt7622_i2c2_2_funcs[] = { 0, 0, }; + +/* I2S */ +static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; +static int mt7622_i2s1_in_data_pins[] = { 1, }; +static int mt7622_i2s1_in_data_funcs[] = { 0, }; +static int mt7622_i2s2_in_data_pins[] = { 16, }; +static int mt7622_i2s2_in_data_funcs[] = { 0, }; +static int mt7622_i2s3_in_data_pins[] = { 17, }; +static int mt7622_i2s3_in_data_funcs[] = { 0, }; +static int mt7622_i2s4_in_data_pins[] = { 18, }; +static int mt7622_i2s4_in_data_funcs[] = { 0, }; +static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; +static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; +static int mt7622_i2s1_out_data_pins[] = { 2, }; +static int mt7622_i2s1_out_data_funcs[] = { 0, }; +static int mt7622_i2s2_out_data_pins[] = { 19, }; +static int mt7622_i2s2_out_data_funcs[] = { 0, }; +static int mt7622_i2s3_out_data_pins[] = { 20, }; +static int mt7622_i2s3_out_data_funcs[] = { 0, }; +static int mt7622_i2s4_out_data_pins[] = { 21, }; +static int mt7622_i2s4_out_data_funcs[] = { 0, }; + +/* IR */ +static int mt7622_ir_0_tx_pins[] = { 16, }; +static int mt7622_ir_0_tx_funcs[] = { 4, }; +static int mt7622_ir_1_tx_pins[] = { 59, }; +static int mt7622_ir_1_tx_funcs[] = { 5, }; +static int mt7622_ir_2_tx_pins[] = { 99, }; +static int mt7622_ir_2_tx_funcs[] = { 3, }; +static int mt7622_ir_0_rx_pins[] = { 17, }; +static int mt7622_ir_0_rx_funcs[] = { 4, }; +static int mt7622_ir_1_rx_pins[] = { 60, }; +static int mt7622_ir_1_rx_funcs[] = { 5, }; +static int mt7622_ir_2_rx_pins[] = { 100, }; +static int mt7622_ir_2_rx_funcs[] = { 3, }; + +/* MDIO */ +static int mt7622_mdc_mdio_pins[] = { 23, 24, }; +static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; + +/* PCIE */ +static int mt7622_pcie0_0_waken_pins[] = { 14, }; +static int mt7622_pcie0_0_waken_funcs[] = { 2, }; +static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; +static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; +static int mt7622_pcie0_1_waken_pins[] = { 79, }; +static int mt7622_pcie0_1_waken_funcs[] = { 4, }; +static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; +static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; +static int mt7622_pcie1_0_waken_pins[] = { 14, }; +static int mt7622_pcie1_0_waken_funcs[] = { 3, }; +static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; +static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; + +static int mt7622_pcie0_pad_perst_pins[] = { 83, }; +static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; +static int mt7622_pcie1_pad_perst_pins[] = { 84, }; +static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; + +/* PMIC bus */ +static int mt7622_pmic_bus_pins[] = { 71, 72, }; +static int mt7622_pmic_bus_funcs[] = { 0, 0, }; + +/* Parallel NAND */ +static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, }; +static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, }; + +/* PWM */ +static int mt7622_pwm_ch1_0_pins[] = { 51, }; +static int mt7622_pwm_ch1_0_funcs[] = { 3, }; +static int mt7622_pwm_ch1_1_pins[] = { 73, }; +static int mt7622_pwm_ch1_1_funcs[] = { 4, }; +static int mt7622_pwm_ch1_2_pins[] = { 95, }; +static int mt7622_pwm_ch1_2_funcs[] = { 0, }; +static int mt7622_pwm_ch2_0_pins[] = { 52, }; +static int mt7622_pwm_ch2_0_funcs[] = { 3, }; +static int mt7622_pwm_ch2_1_pins[] = { 74, }; +static int mt7622_pwm_ch2_1_funcs[] = { 4, }; +static int mt7622_pwm_ch2_2_pins[] = { 96, }; +static int mt7622_pwm_ch2_2_funcs[] = { 0, }; +static int mt7622_pwm_ch3_0_pins[] = { 53, }; +static int mt7622_pwm_ch3_0_funcs[] = { 3, }; +static int mt7622_pwm_ch3_1_pins[] = { 75, }; +static int mt7622_pwm_ch3_1_funcs[] = { 4, }; +static int mt7622_pwm_ch3_2_pins[] = { 97, }; +static int mt7622_pwm_ch3_2_funcs[] = { 0, }; +static int mt7622_pwm_ch4_0_pins[] = { 54, }; +static int mt7622_pwm_ch4_0_funcs[] = { 3, }; +static int mt7622_pwm_ch4_1_pins[] = { 67, }; +static int mt7622_pwm_ch4_1_funcs[] = { 3, }; +static int mt7622_pwm_ch4_2_pins[] = { 76, }; +static int mt7622_pwm_ch4_2_funcs[] = { 4, }; +static int mt7622_pwm_ch4_3_pins[] = { 98, }; +static int mt7622_pwm_ch4_3_funcs[] = { 0, }; +static int mt7622_pwm_ch5_0_pins[] = { 68, }; +static int mt7622_pwm_ch5_0_funcs[] = { 3, }; +static int mt7622_pwm_ch5_1_pins[] = { 77, }; +static int mt7622_pwm_ch5_1_funcs[] = { 4, }; +static int mt7622_pwm_ch5_2_pins[] = { 99, }; +static int mt7622_pwm_ch5_2_funcs[] = { 0, }; +static int mt7622_pwm_ch6_0_pins[] = { 69, }; +static int mt7622_pwm_ch6_0_funcs[] = { 3, }; +static int mt7622_pwm_ch6_1_pins[] = { 78, }; +static int mt7622_pwm_ch6_1_funcs[] = { 4, }; +static int mt7622_pwm_ch6_2_pins[] = { 81, }; +static int mt7622_pwm_ch6_2_funcs[] = { 4, }; +static int mt7622_pwm_ch6_3_pins[] = { 100, }; +static int mt7622_pwm_ch6_3_funcs[] = { 0, }; +static int mt7622_pwm_ch7_0_pins[] = { 70, }; +static int mt7622_pwm_ch7_0_funcs[] = { 3, }; +static int mt7622_pwm_ch7_1_pins[] = { 82, }; +static int mt7622_pwm_ch7_1_funcs[] = { 4, }; +static int mt7622_pwm_ch7_2_pins[] = { 101, }; +static int mt7622_pwm_ch7_2_funcs[] = { 0, }; + +/* SD */ +static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; +static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; +static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; +static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +/* Serial NAND */ +static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; +static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; + +/* SPI NOR */ +static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; +static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; + +/* SPIC */ +static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; +static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; +static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; +static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; +static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; +static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; +static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; +static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; +static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; +static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; + +/* TDM */ +static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; +static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; +static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_0_out_data_pins[] = { 20, }; +static int mt7622_tdm_0_out_data_funcs[] = { 3, }; +static int mt7622_tdm_0_in_data_pins[] = { 21, }; +static int mt7622_tdm_0_in_data_funcs[] = { 3, }; +static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; +static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; +static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; +static int mt7622_tdm_1_out_data_pins[] = { 55, }; +static int mt7622_tdm_1_out_data_funcs[] = { 3, }; +static int mt7622_tdm_1_in_data_pins[] = { 56, }; +static int mt7622_tdm_1_in_data_funcs[] = { 3, }; + +/* UART */ +static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; +static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; +static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; +static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; +static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; +static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; +static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; +static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; +static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; +static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; +static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; +static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; +static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; +static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; +static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; +static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; +static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; +static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; +static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; +static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; +static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; +static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; +static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; +static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; +static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; +static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; +static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; +static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; +static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; +static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; + +/* Watchdog */ +static int mt7622_watchdog_pins[] = { 78, }; +static int mt7622_watchdog_funcs[] = { 0, }; + +/* WLAN LED */ +static int mt7622_wled_pins[] = { 85, }; +static int mt7622_wled_funcs[] = { 0, }; + +static const struct mtk_group_desc mt7622_groups[] = { + PINCTRL_PIN_GROUP("emmc", mt7622_emmc), + PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst), + PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds), + PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led), + PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led), + PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led), + PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led), + PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led), + PINCTRL_PIN_GROUP("esw", mt7622_esw), + PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1), + PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4), + PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw), + PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1), + PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2), + PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0), + PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0), + PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1), + PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2), + PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0), + PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1), + PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2), + PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data), + PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data), + PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data), + PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data), + PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data), + PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data), + PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data), + PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data), + PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx), + PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx), + PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx), + PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx), + PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx), + PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx), + PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio), + PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken), + PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq), + PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken), + PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq), + PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken), + PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq), + PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst), + PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst), + PINCTRL_PIN_GROUP("par_nand", mt7622_pnand), + PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus), + PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0), + PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1), + PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2), + PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0), + PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1), + PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2), + PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0), + PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1), + PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2), + PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0), + PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1), + PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2), + PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3), + PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0), + PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1), + PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2), + PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0), + PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1), + PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2), + PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3), + PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0), + PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1), + PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2), + PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0), + PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1), + PINCTRL_PIN_GROUP("snfi", mt7622_snfi), + PINCTRL_PIN_GROUP("spi_nor", mt7622_spi), + PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0), + PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1), + PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0), + PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1), + PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0), + PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold), + PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws", + mt7622_tdm_0_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws", + mt7622_tdm_0_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data), + PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data), + PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws", + mt7622_tdm_1_out_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws", + mt7622_tdm_1_in_mclk_bclk_ws), + PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data), + PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data), + PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx), + PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx), + PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts), + PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx), + PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts), + PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx), + PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts), + PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx), + PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts), + PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx), + PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts), + PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx), + PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx), + PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx), + PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts), + PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx), + PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx), + PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts), + PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx), + PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts), + PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog), + PINCTRL_PIN_GROUP("wled", mt7622_wled), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", }; +static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1", + "esw_p2_p3_p4", "mdc_mdio", + "rgmii_via_gmac1", + "rgmii_via_gmac2", + "rgmii_via_esw", }; +static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", + "i2c1_2", "i2c2_0", "i2c2_1", + "i2c2_2", }; +static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws", + "i2s_in_mclk_bclk_ws", + "i2s1_in_data", "i2s2_in_data", + "i2s3_in_data", "i2s4_in_data", + "i2s1_out_data", "i2s2_out_data", + "i2s3_out_data", "i2s4_out_data", }; +static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx", + "ir_0_rx", "ir_1_rx", "ir_2_rx"}; +static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led", + "ephy1_led", "ephy2_led", + "ephy3_led", "ephy4_led", + "wled", }; +static const char *const mt7622_flash_groups[] = { "par_nand", "snfi", + "spi_nor"}; +static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken", + "pcie0_0_clkreq", "pcie0_1_waken", + "pcie0_1_clkreq", "pcie1_0_waken", + "pcie1_0_clkreq", "pcie0_pad_perst", + "pcie1_pad_perst", }; +static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", }; +static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", + "pwm_ch1_2", "pwm_ch2_0", + "pwm_ch2_1", "pwm_ch2_2", + "pwm_ch3_0", "pwm_ch3_1", + "pwm_ch3_2", "pwm_ch4_0", + "pwm_ch4_1", "pwm_ch4_2", + "pwm_ch4_3", "pwm_ch5_0", + "pwm_ch5_1", "pwm_ch5_2", + "pwm_ch6_0", "pwm_ch6_1", + "pwm_ch6_2", "pwm_ch6_3", + "pwm_ch7_0", "pwm_ch7_1", + "pwm_ch7_2", }; +static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", }; +static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1", + "spic1_0", "spic1_1", "spic2_0", + "spic2_0_wp_hold", }; +static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws", + "tdm_0_in_mclk_bclk_ws", + "tdm_0_out_data", + "tdm_0_in_data", + "tdm_1_out_mclk_bclk_ws", + "tdm_1_in_mclk_bclk_ws", + "tdm_1_out_data", + "tdm_1_in_data", }; + +static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx", + "uart1_0_tx_rx", "uart1_0_rts_cts", + "uart1_1_tx_rx", "uart1_1_rts_cts", + "uart2_0_tx_rx", "uart2_0_rts_cts", + "uart2_1_tx_rx", "uart2_1_rts_cts", + "uart2_2_tx_rx", "uart2_2_rts_cts", + "uart2_3_tx_rx", + "uart3_0_tx_rx", + "uart3_1_tx_rx", "uart3_1_rts_cts", + "uart4_0_tx_rx", + "uart4_1_tx_rx", "uart4_1_rts_cts", + "uart4_2_tx_rx", + "uart4_2_rts_cts",}; +static const char *const mt7622_wdt_groups[] = { "watchdog", }; + +static const struct mtk_function_desc mt7622_functions[] = { + {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)}, + {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)}, + {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)}, + {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)}, + {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)}, + {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)}, + {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)}, + {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)}, + {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)}, + {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)}, + {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)}, + {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)}, + {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)}, + {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)}, + {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, +}; + +static struct mtk_pinctrl_soc mt7622_data = { + .name = "mt7622_pinctrl", + .reg_cal = mt7622_reg_cals, + .pins = mt7622_pins, + .npins = ARRAY_SIZE(mt7622_pins), + .grps = mt7622_groups, + .ngrps = ARRAY_SIZE(mt7622_groups), + .funcs = mt7622_functions, + .nfuncs = ARRAY_SIZE(mt7622_functions), + .gpio_mode = 1, + .rev = MTK_PINCTRL_V0, +}; + +static int mtk_pinctrl_mt7622_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7622_data); +} + +static const struct udevice_id mt7622_pctrl_match[] = { + { .compatible = "mediatek,mt7622-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7622_pinctrl) = { + .name = "mt7622_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7622_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt7622_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv), +}; + + diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c index fd37dfa..d58d840 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c @@ -1242,6 +1242,8 @@ static struct mtk_pinctrl_soc mt7623_data = { .ngrps = ARRAY_SIZE(mt7623_groups), .funcs = mt7623_functions, .nfuncs = ARRAY_SIZE(mt7623_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; /* diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c index aa6d1c2..37640dd 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c @@ -387,6 +387,8 @@ static struct mtk_pinctrl_soc mt7629_data = { .ngrps = ARRAY_SIZE(mt7629_groups), .funcs = mt7629_functions, .nfuncs = ARRAY_SIZE(mt7629_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; static int mtk_pinctrl_mt7629_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c b/drivers/pinctrl/mediatek/pinctrl-mt8512.c new file mode 100644 index 0000000..af43754 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <dm.h> + +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, false) +#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, true) +#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 30, false) + +static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = { + PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = { + PIN_FIELD(0, 115, 0x140, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_di_range[] = { + PIN_FIELD(0, 115, 0x000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_do_range[] = { + PIN_FIELD(0, 115, 0x860, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = { + PIN_FIELD(0, 115, 0x900, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = { + PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = { + PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1), + PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1), + PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1), + PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1), + PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1), + PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1), + PIN_FIELD(20, 20, 0x410, 0x10, 6, 1), + PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1), + PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1), + PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1), + PIN_FIELD(32, 32, 0x410, 0x10, 10, 1), + PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1), + PIN_FIELD(40, 40, 0x410, 0x10, 12, 1), + PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1), + PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1), + PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1), + PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1), + PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1), + PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1), + PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1), + PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1), + PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1), + PIN_FIELD(70, 70, 0x410, 0x10, 22, 1), + PIN_FIELD(71, 71, 0x410, 0x10, 23, 1), + PIN_FIELD(72, 72, 0x410, 0x10, 24, 1), + PIN_FIELD(73, 73, 0x410, 0x10, 25, 1), + PIN_FIELD(74, 74, 0x410, 0x10, 26, 1), + PIN_FIELD(75, 75, 0x410, 0x10, 27, 1), + PIN_FIELD(76, 76, 0x410, 0x10, 28, 1), + PIN_FIELD(77, 77, 0x410, 0x10, 29, 1), + PIN_FIELD(78, 78, 0x410, 0x10, 30, 1), + PIN_FIELD(79, 79, 0x410, 0x10, 31, 1), + PIN_FIELD(80, 80, 0x420, 0x10, 0, 1), + PIN_FIELD(81, 81, 0x420, 0x10, 1, 1), + PIN_FIELD(82, 82, 0x420, 0x10, 2, 1), + PIN_FIELD(83, 83, 0x420, 0x10, 3, 1), + PIN_FIELD(84, 84, 0x420, 0x10, 4, 1), + PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1), + PIN_FIELD(87, 87, 0x420, 0x10, 6, 1), + PIN_FIELDS(88, 91, 0x420, 0x10, 7, 1), + PIN_FIELDS(92, 98, 0x420, 0x10, 8, 1), + PIN_FIELDS(99, 101, 0x420, 0x10, 9, 1), + PIN_FIELDS(102, 104, 0x420, 0x10, 10, 1), + PIN_FIELDS(105, 111, 0x420, 0x10, 11, 1), + PIN_FIELDS(112, 115, 0x420, 0x10, 12, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_smt_range[] = { + PIN_FIELDS(0, 2, 0x470, 0x10, 0, 1), + PIN_FIELDS(3, 5, 0x470, 0x10, 1, 1), + PIN_FIELDS(6, 7, 0x470, 0x10, 2, 1), + PIN_FIELDS(8, 11, 0x470, 0x10, 3, 1), + PIN_FIELDS(12, 15, 0x470, 0x10, 4, 1), + PIN_FIELDS(16, 19, 0x470, 0x10, 5, 1), + PIN_FIELD(20, 20, 0x470, 0x10, 6, 1), + PIN_FIELDS(21, 25, 0x470, 0x10, 7, 1), + PIN_FIELDS(26, 27, 0x470, 0x10, 8, 1), + PIN_FIELDS(28, 31, 0x470, 0x10, 9, 1), + PIN_FIELD(32, 32, 0x470, 0x10, 10, 1), + PIN_FIELDS(33, 39, 0x470, 0x10, 11, 1), + PIN_FIELD(40, 40, 0x470, 0x10, 12, 1), + PIN_FIELDS(41, 43, 0x470, 0x10, 13, 1), + PIN_FIELDS(44, 47, 0x470, 0x10, 14, 1), + PIN_FIELDS(48, 51, 0x470, 0x10, 15, 1), + PIN_FIELDS(52, 53, 0x470, 0x10, 16, 1), + PIN_FIELDS(54, 57, 0x470, 0x10, 17, 1), + PIN_FIELDS(58, 63, 0x470, 0x10, 18, 1), + PIN_FIELDS(64, 65, 0x470, 0x10, 19, 1), + PIN_FIELDS(66, 67, 0x470, 0x10, 20, 1), + PIN_FIELDS(68, 69, 0x470, 0x10, 21, 1), + PIN_FIELD(70, 70, 0x470, 0x10, 22, 1), + PIN_FIELD(71, 71, 0x470, 0x10, 23, 1), + PIN_FIELD(72, 72, 0x470, 0x10, 24, 1), + PIN_FIELD(73, 73, 0x470, 0x10, 25, 1), + PIN_FIELD(74, 74, 0x470, 0x10, 26, 1), + PIN_FIELD(75, 75, 0x470, 0x10, 27, 1), + PIN_FIELD(76, 76, 0x470, 0x10, 28, 1), + PIN_FIELD(77, 77, 0x470, 0x10, 29, 1), + PIN_FIELD(78, 78, 0x470, 0x10, 30, 1), + PIN_FIELD(79, 79, 0x470, 0x10, 31, 1), + PIN_FIELD(80, 80, 0x480, 0x10, 0, 1), + PIN_FIELD(81, 81, 0x480, 0x10, 1, 1), + PIN_FIELD(82, 82, 0x480, 0x10, 2, 1), + PIN_FIELD(83, 83, 0x480, 0x10, 3, 1), + PIN_FIELD(84, 84, 0x480, 0x10, 4, 1), + PIN_FIELDS(85, 86, 0x480, 0x10, 5, 1), + PIN_FIELD(87, 87, 0x480, 0x10, 6, 1), + PIN_FIELDS(88, 91, 0x480, 0x10, 7, 1), + PIN_FIELDS(92, 98, 0x480, 0x10, 8, 1), + PIN_FIELDS(99, 101, 0x480, 0x10, 9, 1), + PIN_FIELDS(102, 104, 0x480, 0x10, 10, 1), + PIN_FIELDS(105, 111, 0x480, 0x10, 11, 1), + PIN_FIELDS(112, 115, 0x480, 0x10, 12, 1), +}; + +static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = { + PIN_FIELDS(0, 2, 0x710, 0x10, 0, 4), + PIN_FIELDS(3, 5, 0x710, 0x10, 4, 4), + PIN_FIELDS(6, 7, 0x710, 0x10, 8, 4), + PIN_FIELDS(8, 11, 0x710, 0x10, 12, 4), + PIN_FIELDS(12, 15, 0x710, 0x10, 16, 4), + PIN_FIELDS(16, 19, 0x710, 0x10, 20, 4), + PIN_FIELD(20, 20, 0x710, 0x10, 24, 4), + PIN_FIELDS(21, 25, 0x710, 0x10, 28, 4), + PIN_FIELDS(26, 27, 0x720, 0x10, 0, 4), + PIN_FIELDS(28, 31, 0x720, 0x10, 4, 4), + PIN_FIELD(32, 32, 0x720, 0x10, 8, 4), + PIN_FIELDS(33, 39, 0x720, 0x10, 12, 4), + PIN_FIELD(40, 40, 0x720, 0x10, 16, 4), + PIN_FIELDS(41, 43, 0x720, 0x10, 20, 4), + PIN_FIELDS(44, 47, 0x720, 0x10, 24, 4), + PIN_FIELDS(48, 51, 0x720, 0x10, 28, 4), + PIN_FIELDS(52, 53, 0x730, 0x10, 0, 4), + PIN_FIELDS(54, 57, 0x730, 0x10, 4, 4), + PIN_FIELDS(58, 63, 0x730, 0x10, 8, 4), + PIN_FIELDS(64, 65, 0x730, 0x10, 12, 4), + PIN_FIELDS(66, 67, 0x730, 0x10, 16, 4), + PIN_FIELDS(68, 69, 0x730, 0x10, 20, 4), + PIN_FIELD(70, 70, 0x730, 0x10, 24, 4), + PIN_FIELD(71, 71, 0x730, 0x10, 28, 4), + PIN_FIELDS(72, 75, 0x740, 0x10, 0, 4), + PIN_FIELDS(76, 79, 0x740, 0x10, 16, 4), + PIN_FIELD(80, 80, 0x750, 0x10, 0, 4), + PIN_FIELD(81, 81, 0x750, 0x10, 4, 4), + PIN_FIELD(82, 82, 0x750, 0x10, 8, 4), + PIN_FIELDS(83, 86, 0x740, 0x10, 16, 4), + PIN_FIELD(87, 87, 0x750, 0x10, 24, 4), + PIN_FIELDS(88, 91, 0x750, 0x10, 28, 4), + PIN_FIELDS(92, 98, 0x760, 0x10, 0, 4), + PIN_FIELDS(99, 101, 0x760, 0x10, 4, 4), + PIN_FIELDS(102, 104, 0x760, 0x10, 8, 4), + PIN_FIELDS(105, 111, 0x760, 0x10, 12, 4), + PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4), +}; + +static const struct mtk_pin_reg_calc mt8512_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8512_pin_do_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8512_pin_ies_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8512_pin_smt_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8512_pin_pullsel_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8512_pin_pullen_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8512_pin_drv_range), +}; + +static const struct mtk_pin_desc mt8512_pins[] = { + MTK_PIN(0, "GPIO0", DRV_GRP4), + MTK_PIN(1, "GPIO1", DRV_GRP4), + MTK_PIN(2, "GPIO2", DRV_GRP4), + MTK_PIN(3, "GPIO3", DRV_GRP4), + MTK_PIN(4, "GPIO4", DRV_GRP4), + MTK_PIN(5, "GPIO5", DRV_GRP4), + MTK_PIN(6, "GPIO6", DRV_GRP4), + MTK_PIN(7, "GPIO7", DRV_GRP4), + MTK_PIN(8, "GPIO8", DRV_GRP4), + MTK_PIN(9, "GPIO9", DRV_GRP4), + MTK_PIN(10, "GPIO10", DRV_GRP4), + MTK_PIN(11, "GPIO11", DRV_GRP4), + MTK_PIN(12, "GPIO12", DRV_GRP4), + MTK_PIN(13, "GPIO13", DRV_GRP4), + MTK_PIN(14, "GPIO14", DRV_GRP4), + MTK_PIN(15, "GPIO15", DRV_GRP4), + MTK_PIN(16, "GPIO16", DRV_GRP4), + MTK_PIN(17, "GPIO17", DRV_GRP4), + MTK_PIN(18, "GPIO18", DRV_GRP4), + MTK_PIN(19, "GPIO19", DRV_GRP4), + MTK_PIN(20, "GPIO20", DRV_GRP4), + MTK_PIN(21, "AUDIO_SYNC", DRV_GRP4), + MTK_PIN(22, "WIFI_INTB", DRV_GRP4), + MTK_PIN(23, "BT_INTB", DRV_GRP4), + MTK_PIN(24, "BT_STEREO", DRV_GRP4), + MTK_PIN(25, "RSTNB", DRV_GRP4), + MTK_PIN(26, "USB_ID", DRV_GRP4), + MTK_PIN(27, "USB_DRV", DRV_GRP4), + MTK_PIN(28, "EINT_GAUGEING", DRV_GRP4), + MTK_PIN(29, "CHG_IRQ", DRV_GRP4), + MTK_PIN(30, "CHG_OTG", DRV_GRP4), + MTK_PIN(31, "CHG_CEB", DRV_GRP4), + MTK_PIN(32, "FL_EN", DRV_GRP4), + MTK_PIN(33, "WAN_SMS_RDY", DRV_GRP4), + MTK_PIN(34, "SOC2WAN_RESET", DRV_GRP4), + MTK_PIN(35, "WAN_FM_RDY", DRV_GRP4), + MTK_PIN(36, "WAN_DIS", DRV_GRP4), + MTK_PIN(37, "WAN_VBUS_EN", DRV_GRP4), + MTK_PIN(38, "WAN_VBAT_EN", DRV_GRP4), + MTK_PIN(39, "WAN_PWR_EN", DRV_GRP4), + MTK_PIN(40, "KPROW0", DRV_GRP4), + MTK_PIN(41, "KPROW1", DRV_GRP4), + MTK_PIN(42, "KPCOL0", DRV_GRP4), + MTK_PIN(43, "KPCOL1", DRV_GRP4), + MTK_PIN(44, "PWM0", DRV_GRP4), + MTK_PIN(45, "PWM1", DRV_GRP4), + MTK_PIN(46, "PWM2", DRV_GRP4), + MTK_PIN(47, "PWM3", DRV_GRP4), + MTK_PIN(48, "JTMS", DRV_GRP4), + MTK_PIN(49, "JTCK", DRV_GRP4), + MTK_PIN(50, "JTDI", DRV_GRP4), + MTK_PIN(51, "JTDO", DRV_GRP4), + MTK_PIN(52, "URXD0", DRV_GRP4), + MTK_PIN(53, "UTXD0", DRV_GRP4), + MTK_PIN(54, "URXD1", DRV_GRP4), + MTK_PIN(55, "UTXD1", DRV_GRP4), + MTK_PIN(56, "URTS1", DRV_GRP4), + MTK_PIN(57, "UCTS1", DRV_GRP4), + MTK_PIN(58, "RTC32K_CK", DRV_GRP4), + MTK_PIN(59, "PMIC_DVS_REQ0", DRV_GRP4), + MTK_PIN(60, "PMIC_DVS_REQ1", DRV_GRP4), + MTK_PIN(61, "WATCHDOG", DRV_GRP4), + MTK_PIN(62, "PMIC_INT", DRV_GRP4), + MTK_PIN(63, "SUSPEND", DRV_GRP4), + MTK_PIN(64, "SDA0", DRV_GRP4), + MTK_PIN(65, "SCL0", DRV_GRP4), + MTK_PIN(66, "SDA1", DRV_GRP4), + MTK_PIN(67, "SCL1", DRV_GRP4), + MTK_PIN(68, "SDA2", DRV_GRP4), + MTK_PIN(69, "SCL2", DRV_GRP4), + MTK_PIN(70, "MSDC1_CMD", DRV_GRP4), + MTK_PIN(71, "MSDC1_CLK", DRV_GRP4), + MTK_PIN(72, "MSDC1_DAT0", DRV_GRP4), + MTK_PIN(73, "MSDC1_DAT1", DRV_GRP4), + MTK_PIN(74, "MSDC1_DAT2", DRV_GRP4), + MTK_PIN(75, "MSDC1_DAT3", DRV_GRP4), + MTK_PIN(76, "MSDC0_DAT7", DRV_GRP4), + MTK_PIN(77, "MSDC0_DAT6", DRV_GRP4), + MTK_PIN(78, "MSDC0_DAT5", DRV_GRP4), + MTK_PIN(79, "MSDC0_DAT4", DRV_GRP4), + MTK_PIN(80, "MSDC0_RSTB", DRV_GRP4), + MTK_PIN(81, "MSDC0_CMD", DRV_GRP4), + MTK_PIN(82, "MSDC0_CLK", DRV_GRP4), + MTK_PIN(83, "MSDC0_DAT3", DRV_GRP4), + MTK_PIN(84, "MSDC0_DAT2", DRV_GRP4), + MTK_PIN(85, "MSDC0_DAT1", DRV_GRP4), + MTK_PIN(86, "MSDC0_DAT0", DRV_GRP4), + MTK_PIN(87, "SPDIF", DRV_GRP4), + MTK_PIN(88, "PCM_CLK", DRV_GRP4), + MTK_PIN(89, "PCM_SYNC", DRV_GRP4), + MTK_PIN(90, "PCM_RX", DRV_GRP4), + MTK_PIN(91, "PCM_TX", DRV_GRP4), + MTK_PIN(92, "I2SIN_MCLK", DRV_GRP4), + MTK_PIN(93, "I2SIN_LRCK", DRV_GRP4), + MTK_PIN(94, "I2SIN_BCK", DRV_GRP4), + MTK_PIN(95, "I2SIN_DAT0", DRV_GRP4), + MTK_PIN(96, "I2SIN_DAT1", DRV_GRP4), + MTK_PIN(97, "I2SIN_DAT2", DRV_GRP4), + MTK_PIN(98, "I2SIN_DAT3", DRV_GRP4), + MTK_PIN(99, "DMIC0_CLK", DRV_GRP4), + MTK_PIN(100, "DMIC0_DAT0", DRV_GRP4), + MTK_PIN(101, "DMIC0_DAT1", DRV_GRP4), + MTK_PIN(102, "DMIC1_CLK", DRV_GRP4), + MTK_PIN(103, "DMIC1_DAT0", DRV_GRP4), + MTK_PIN(104, "DMIC1_DAT1", DRV_GRP4), + MTK_PIN(105, "I2SO_BCK", DRV_GRP4), + MTK_PIN(106, "I2SO_LRCK", DRV_GRP4), + MTK_PIN(107, "I2SO_MCLK", DRV_GRP4), + MTK_PIN(108, "I2SO_DAT0", DRV_GRP4), + MTK_PIN(109, "I2SO_DAT1", DRV_GRP4), + MTK_PIN(110, "I2SO_DAT2", DRV_GRP4), + MTK_PIN(111, "I2SO_DAT3", DRV_GRP4), + MTK_PIN(112, "SPI_CSB", DRV_GRP4), + MTK_PIN(113, "SPI_CLK", DRV_GRP4), + MTK_PIN(114, "SPI_MISO", DRV_GRP4), + MTK_PIN(115, "SPI_MOSI", DRV_GRP4), +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART */ +static int mt8512_uart0_0_rxd_txd_pins[] = { 52, 53, }; +static int mt8512_uart0_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8512_uart1_0_rxd_txd_pins[] = { 54, 55, }; +static int mt8512_uart1_0_rxd_txd_funcs[] = { 1, 1, }; +static int mt8512_uart2_0_rxd_txd_pins[] = { 28, 29, }; +static int mt8512_uart2_0_rxd_txd_funcs[] = { 1, 1, }; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *const mt8512_uart_groups[] = { "uart0_0_rxd_txd", + "uart1_0_rxd_txd", + "uart2_0_rxd_txd", }; + +/* SNAND */ +static int mt8512_snfi_pins[] = { 71, 76, 77, 78, 79, 80, }; +static int mt8512_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; + +/* MMC0 */ +static int mt8512_msdc0_pins[] = { 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, }; +static int mt8512_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static const struct mtk_group_desc mt8512_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8512_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8512_uart1_0_rxd_txd), + PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8512_uart2_0_rxd_txd), + + PINCTRL_PIN_GROUP("msdc0", mt8512_msdc0), + + PINCTRL_PIN_GROUP("snfi", mt8512_snfi), +}; + +static const char *const mt8512_msdc_groups[] = { "msdc0" }; + +static const struct mtk_function_desc mt8512_functions[] = { + {"uart", mt8512_uart_groups, ARRAY_SIZE(mt8512_uart_groups)}, + {"msdc", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, + {"snand", mt8512_msdc_groups, ARRAY_SIZE(mt8512_msdc_groups)}, +}; + +static struct mtk_pinctrl_soc mt8512_data = { + .name = "mt8512_pinctrl", + .reg_cal = mt8512_reg_cals, + .pins = mt8512_pins, + .npins = ARRAY_SIZE(mt8512_pins), + .grps = mt8512_groups, + .ngrps = ARRAY_SIZE(mt8512_groups), + .funcs = mt8512_functions, + .nfuncs = ARRAY_SIZE(mt8512_functions), +}; + +static int mtk_pinctrl_mt8512_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8512_data); +} + +static const struct udevice_id mt8512_pctrl_match[] = { + { .compatible = "mediatek,mt8512-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8512_pinctrl) = { + .name = "mt8512_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8512_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt8512_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 829b30e..62e339e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -369,6 +369,8 @@ static struct mtk_pinctrl_soc mt8516_data = { .ngrps = ARRAY_SIZE(mt8516_groups), .funcs = mt8516_functions, .nfuncs = ARRAY_SIZE(mt8516_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; static int mtk_pinctrl_mt8516_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c index 8d2cd94..91427ae 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c @@ -389,6 +389,8 @@ static struct mtk_pinctrl_soc mt8518_data = { .ngrps = ARRAY_SIZE(mt8518_groups), .funcs = mt8518_functions, .nfuncs = ARRAY_SIZE(mt8518_functions), + .gpio_mode = 0, + .rev = MTK_PINCTRL_V1, }; static int mtk_pinctrl_mt8518_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 3004335..c7351f3 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -294,7 +294,72 @@ static const struct pinconf_param mtk_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, }; -int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) + +int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg) +{ + int err, disable, pullup; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + + if (disable) { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0); + if (err) + return err; + + } else { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup); + if (err) + return err; + } + + return 0; +} + +int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg) +{ + int err, disable, pullup; + + disable = (arg == PIN_CONFIG_BIAS_DISABLE); + pullup = (arg == PIN_CONFIG_BIAS_PULL_UP); + + if (disable) { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0); + if (err) + return err; + } else { + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL, + pullup); + if (err) + return err; + } + + return 0; +} + +int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg) +{ + int err; + + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0); + if (err) + return err; + return 0; +} + +int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg) { struct mtk_pinctrl_priv *priv = dev_get_priv(dev); const struct mtk_pin_desc *desc = &priv->soc->pins[pin]; @@ -309,7 +374,30 @@ int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg) */ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { arg = (arg / tb->step - 1) * tb->scal; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4, + arg & 0x1); + if (err) + return err; + err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8, + (arg & 0x2) >> 1); + if (err) + return err; + } + + return 0; +} + + +int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg) +{ + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + const struct mtk_pin_desc *desc = &priv->soc->pins[pin]; + const struct mtk_drive_desc *tb; + int err = -ENOTSUPP; + tb = &mtk_drive[desc->drv_n]; + if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) { + arg = (arg / tb->step - 1) * tb->scal; err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg); if (err) return err; @@ -322,21 +410,17 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, unsigned int param, unsigned int arg) { int err = 0; + struct mtk_pinctrl_priv *priv = dev_get_priv(dev); + int rev = priv->soc->rev; switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: - arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : - (param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2; - - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL, - arg & 1); - if (err) - goto err; - - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, - !!(arg & 2)); + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_bias_set_v0(dev, pin, param); + else + err = mtk_pinconf_bias_set_v1(dev, pin, param); if (err) goto err; break; @@ -349,10 +433,8 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, goto err; break; case PIN_CONFIG_INPUT_ENABLE: - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1); - if (err) - goto err; - err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0); + if (rev == MTK_PINCTRL_V1) + err = mtk_pinconf_input_enable_v1(dev, pin, param); if (err) goto err; break; @@ -381,7 +463,10 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin, goto err; break; case PIN_CONFIG_DRIVE_STRENGTH: - err = mtk_pinconf_drive_set(dev, pin, arg); + if (rev == MTK_PINCTRL_V0) + err = mtk_pinconf_drive_set_v0(dev, pin, arg); + else + err = mtk_pinconf_drive_set_v1(dev, pin, arg); if (err) goto err; break; @@ -475,7 +560,10 @@ static int mtk_gpio_direction_output(struct udevice *dev, static int mtk_gpio_request(struct udevice *dev, unsigned int off, const char *label) { - return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0); + struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent); + + return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, + priv->soc->gpio_mode); } static int mtk_gpio_probe(struct udevice *dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 86559f0..e815761 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -3,10 +3,12 @@ * Copyright (C) 2018 MediaTek Inc. * Author: Ryder Lee <ryder.lee@mediatek.com> */ - #ifndef __PINCTRL_MEDIATEK_H__ #define __PINCTRL_MEDIATEK_H__ +#define MTK_PINCTRL_V0 0x0 +#define MTK_PINCTRL_V1 0x1 + #define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } #define MTK_PIN(_number, _name, _drv_n) { \ .number = _number, \ @@ -40,8 +42,12 @@ enum { PINCTRL_PIN_REG_DIR, PINCTRL_PIN_REG_DI, PINCTRL_PIN_REG_DO, - PINCTRL_PIN_REG_IES, PINCTRL_PIN_REG_SMT, + PINCTRL_PIN_REG_PD, + PINCTRL_PIN_REG_PU, + PINCTRL_PIN_REG_E4, + PINCTRL_PIN_REG_E8, + PINCTRL_PIN_REG_IES, PINCTRL_PIN_REG_PULLEN, PINCTRL_PIN_REG_PULLSEL, PINCTRL_PIN_REG_DRV, @@ -161,6 +167,8 @@ struct mtk_pinctrl_soc { int ngrps; const struct mtk_function_desc *funcs; int nfuncs; + int gpio_mode; + int rev; }; /** diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index c67e880..0bf8a16 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -60,6 +60,7 @@ #define DCM_TOP_EN BIT(0) enum scp_domain_type { + SCPSYS_MT7622, SCPSYS_MT7623, SCPSYS_MT7629, }; @@ -328,6 +329,7 @@ static int mtk_power_domain_hook(struct udevice *dev) case SCPSYS_MT7623: scpd->data = scp_domain_mt7623; break; + case SCPSYS_MT7622: case SCPSYS_MT7629: scpd->data = scp_domain_mt7629; break; @@ -379,6 +381,10 @@ static int mtk_power_domain_probe(struct udevice *dev) static const struct udevice_id mtk_power_domain_ids[] = { { + .compatible = "mediatek,mt7622-scpsys", + .data = SCPSYS_MT7622, + }, + { .compatible = "mediatek,mt7623-scpsys", .data = SCPSYS_MT7623, }, diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index ece7d87..bd95f70 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -100,6 +100,7 @@ config CONS_INDEX config DM_SERIAL bool "Enable Driver Model for serial drivers" depends on DM + select SYS_MALLOC_F help Enable driver model for serial. This replaces drivers/serial/serial.c with the serial uclass, which @@ -136,6 +137,7 @@ config SERIAL_SEARCH_ALL config SPL_DM_SERIAL bool "Enable Driver Model for serial drivers in SPL" depends on DM_SERIAL && SPL_DM + select SYS_SPL_MALLOC_F default y help Enable driver model for serial in SPL. This replaces @@ -146,6 +148,7 @@ config SPL_DM_SERIAL config TPL_DM_SERIAL bool "Enable Driver Model for serial drivers in TPL" depends on DM_SERIAL && TPL_DM + select SYS_TPL_MALLOC_F default y if TPL && DM_SERIAL help Enable driver model for serial in TPL. This replaces |