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authorWeijie Gao <weijie.gao@mediatek.com>2018-12-20 16:12:51 +0800
committerTom Rini <trini@konsulko.com>2019-01-14 17:43:18 -0500
commit3e066bcaefb51adcf5c0594d42abe145f701dbeb (patch)
treed5090d0a91d3152284c7c287d98d8d3a5bbc9d92 /drivers
parent37cbd8918c83c9b160e79c3b79f3521cd8f73537 (diff)
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reset: MedaiTek: add reset controller driver for MediaTek SoCs
This patch adds reset controller driver for MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/reset/Kconfig7
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-mediatek.c102
3 files changed, 110 insertions, 0 deletions
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 9c5208b..3a6d61f 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -106,4 +106,11 @@ config RESET_SOCFPGA
help
Support for reset controller on SoCFPGA platform.
+config RESET_MEDIATEK
+ bool "Reset controller driver for MediaTek SoCs"
+ depends on DM_RESET && ARCH_MEDIATEK && CLK
+ default y
+ help
+ Support for reset controller on MediaTek SoCs.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index f452087..8a4dcab 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c
new file mode 100644
index 0000000..e3614e6
--- /dev/null
+++ b/drivers/reset/reset-mediatek.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ * Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <regmap.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+
+struct mediatek_reset_priv {
+ struct regmap *regmap;
+ u32 regofs;
+ u32 nr_resets;
+};
+
+static int mediatek_reset_request(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int mediatek_reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int mediatek_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+
+ if (id >= priv->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(priv->regmap,
+ priv->regofs + ((id / 32) << 2), BIT(id % 32), BIT(id % 32));
+}
+
+static int mediatek_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+
+ if (id >= priv->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(priv->regmap,
+ priv->regofs + ((id / 32) << 2), BIT(id % 32), 0);
+}
+
+struct reset_ops mediatek_reset_ops = {
+ .request = mediatek_reset_request,
+ .free = mediatek_reset_free,
+ .rst_assert = mediatek_reset_assert,
+ .rst_deassert = mediatek_reset_deassert,
+};
+
+static int mediatek_reset_probe(struct udevice *dev)
+{
+ struct mediatek_reset_priv *priv = dev_get_priv(dev);
+
+ if (!priv->regofs && !priv->nr_resets)
+ return -EINVAL;
+
+ priv->regmap = syscon_node_to_regmap(dev_ofnode(dev));
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ return 0;
+}
+
+int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs)
+{
+ struct udevice *rst_dev;
+ struct mediatek_reset_priv *priv;
+ int ret;
+
+ ret = device_bind_driver_to_node(pdev, "mediatek_reset", "reset",
+ dev_ofnode(pdev), &rst_dev);
+ if (ret)
+ return ret;
+
+ priv = malloc(sizeof(struct mediatek_reset_priv));
+ priv->regofs = regofs;
+ priv->nr_resets = num_regs * 32;
+ rst_dev->priv = priv;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(mediatek_reset) = {
+ .name = "mediatek_reset",
+ .id = UCLASS_RESET,
+ .probe = mediatek_reset_probe,
+ .ops = &mediatek_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct mediatek_reset_priv),
+};