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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2015-12-09 18:46:43 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-06-24 13:07:57 +0200 |
| commit | 3427f4d2045729c8995b19407daf91ea9a50e4f8 (patch) | |
| tree | ca468dac178a837e6d38b353af17640ac2c22055 /drivers | |
| parent | 4c86e0834aeb3ae06389534ccbc90b8bcf5d95bf (diff) | |
| download | u-boot-3427f4d2045729c8995b19407daf91ea9a50e4f8.zip u-boot-3427f4d2045729c8995b19407daf91ea9a50e4f8.tar.gz u-boot-3427f4d2045729c8995b19407daf91ea9a50e4f8.tar.bz2 | |
fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes
Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/fpga/zynqpl.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index dcfe513..4ab354b 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -204,7 +204,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (bstype != BIT_PARTIAL) { + if (bstype != BIT_PARTIAL && bstype != BIT_NONE) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -511,7 +511,8 @@ struct xilinx_fpga_op zynq_op = { * Load the encrypted image from src addr and decrypt the image and * place it back the decrypted image into dstaddr. */ -int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen) +int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, + u8 bstype) { if (srcaddr < SZ_1M || dstaddr < SZ_1M) { printf("%s: src and dst addr should be > 1M\n", @@ -519,7 +520,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen) return FPGA_FAIL; } - if (zynq_dma_xfer_init(BIT_NONE)) { + if (zynq_dma_xfer_init(bstype)) { printf("%s: zynq_dma_xfer_init FAIL\n", __func__); return FPGA_FAIL; } |