Merge tag 'u-boot-amlogic-20220107' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into nextWIP/09Jan2022-next

- disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config

7 files changed, 49 insertions, 12 deletions

diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 0969c03..f350c7e 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -129,12 +129,6 @@ config SPI_FLASH_UNLOCK_ALL
 	 For legacy reasons, this option default to y. But if you intend to
 	 actually use the software protection bits you should say n here.
 
-config SF_DUAL_FLASH
-	bool "SPI DUAL flash memory support"
-	help
-	  Enable this option to support two flash memories connected to a single
-	  controller. Currently Xilinx Zynq qspi supports this.
-
 config SPI_FLASH_ATMEL
 	bool "Atmel SPI flash support"
 	help
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 3ae7bb1..b551ebd 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -355,6 +355,11 @@ const struct flash_info spi_nor_ids[] = {
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
+	{
+		INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
 	{ INFO("w25q80", 0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index b9fda42..ce0adb1 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -128,6 +128,20 @@ config DM_PMIC_FAN53555
 	  The driver implements read/write operations for use with the FAN53555
 	  regulator driver and binds the regulator driver to its node.
 
+config SPL_DM_PMIC_FAN53555
+	bool "Enable support for OnSemi FAN53555 in SPL"
+	depends on SPL_DM_REGULATOR && SPL_DM_I2C
+	select SPL_DM_REGULATOR_FAN53555
+	help
+	  This config enables implementation of driver-model PMIC
+	  uclass features for the FAN53555 regulator. The FAN53555 is
+	  a (family of) single-output regulators that supports
+	  transitioning between two different output voltages based on
+	  an voltage selection pin.
+
+	  The driver implements read/write operations for use with the FAN53555
+	  regulator driver and binds the regulator driver to its node.
+
 config DM_PMIC_MP5416
 	bool "Enable Driver Model for PMIC MP5416"
 	help
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index e1922df..401cde3 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -4,7 +4,7 @@
 # Lukasz Majewski <l.majewski@samsung.com>
 
 obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o
-obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_FAN53555) += fan53555.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 429ee33..2cdf4c9 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
 	writel(CQSPI_REG_INDIRECTRD_DONE,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
 
+	/* Check indirect done status */
+	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
+				CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
+	if (ret) {
+		printf("Indirect read clear completion error (%i)\n", ret);
+		goto failrd;
+	}
+
 	return 0;
 
 failrd:
@@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
 	/* Clear indirect completion status */
 	writel(CQSPI_REG_INDIRECTWR_DONE,
 	       plat->regbase + CQSPI_REG_INDIRECTWR);
+
+	/* Check indirect done status */
+	ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
+				CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
+	if (ret) {
+		printf("Indirect write clear completion error (%i)\n", ret);
+		goto failwr;
+	}
+
 	if (bounce_buf)
 		free(bounce_buf);
 	return 0;
diff --git a/drivers/sysreset/sysreset_watchdog.c b/drivers/sysreset/sysreset_watchdog.c
index 35efcac..8a659ee 100644
--- a/drivers/sysreset/sysreset_watchdog.c
+++ b/drivers/sysreset/sysreset_watchdog.c
@@ -20,9 +20,16 @@ static int wdt_reboot_request(struct udevice *dev, enum sysreset_t type)
 	struct wdt_reboot_plat *plat = dev_get_plat(dev);
 	int ret;
 
-	ret = wdt_expire_now(plat->wdt, 0);
-	if (ret)
-		return ret;
+	switch (type) {
+	case SYSRESET_COLD:
+	case SYSRESET_WARM:
+		ret = wdt_expire_now(plat->wdt, 0);
+		if (ret)
+			return ret;
+		break;
+	default:
+		return -ENOSYS;
+	}
 
 	return -EINPROGRESS;
 }
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 98d2965..5f85c0c 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -89,7 +89,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 	}
 
 	ret = clk_get_by_name(dev, "axi", &clk);
-	if (!ret) {
+	if (ret < 0) {
 		debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
 	} else {
 		ret = clk_enable(&clk);
@@ -100,7 +100,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 	}
 
 	ret = clk_get_by_name(dev, "disp_axi", &clk);
-	if (!ret) {
+	if (ret < 0) {
 		debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret);
 	} else {
 		ret = clk_enable(&clk);