Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblazeWIP/16Nov2021

Xilinx changes for v2022.01-rc3

sdhci:
- Fix emmc mini case with missing firmware interface

zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable

firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location

spi:
- gqsi: Fix write issue at low frequencies

net:
- gem: Disable broadcasts

4 files changed, 25 insertions, 4 deletions

diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index d4dc856..b44fede 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -29,6 +29,10 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
 {
 	struct zynqmp_ipi_msg msg;
 	int ret;
+	u32 buffer[PAYLOAD_ARG_CNT];
+
+	if (!res)
+		res = buffer;
 
 	if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
 	    res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
@@ -164,6 +168,7 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 		 * firmware API is limited by the SMC call size
 		 */
 		u32 regs[] = {api_id, arg0, arg1, arg2, arg3};
+		int ret;
 
 		if (api_id == PM_FPGA_LOAD) {
 			/* Swap addr_hi/low because of incompatibility */
@@ -173,7 +178,10 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 			regs[2] = temp;
 		}
 
-		ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload, PAYLOAD_ARG_CNT);
+		ret = ipi_req(regs, PAYLOAD_ARG_CNT, ret_payload,
+			      PAYLOAD_ARG_CNT);
+		if (ret)
+			return ret;
 #else
 		return -EPERM;
 #endif
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index c94825d..5cea4c6 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -69,6 +69,12 @@ __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
 	return 0;
 }
 
+__weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+			     u32 arg3, u32 *ret_payload)
+{
+	return 0;
+}
+
 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
 /* Default settings for ZynqMP Clock Phases */
 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index ff59982..c309c3c 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -60,6 +60,7 @@
 #define ZYNQ_GEM_NWCFG_SPEED100		0x00000001 /* 100 Mbps operation */
 #define ZYNQ_GEM_NWCFG_SPEED1000	0x00000400 /* 1Gbps operation */
 #define ZYNQ_GEM_NWCFG_FDEN		0x00000002 /* Full Duplex mode */
+#define ZYNQ_GEM_NWCFG_NO_BRDC		BIT(5) /* No broadcast */
 #define ZYNQ_GEM_NWCFG_FSREM		0x00020000 /* FCS removal */
 #define ZYNQ_GEM_NWCFG_SGMII_ENBL	0x08000000 /* SGMII Enable */
 #define ZYNQ_GEM_NWCFG_PCS_SEL		0x00000800 /* PCS select */
@@ -77,6 +78,7 @@
 
 #define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_DBUS_WIDTH | \
 					ZYNQ_GEM_NWCFG_FDEN | \
+					ZYNQ_GEM_NWCFG_NO_BRDC | \
 					ZYNQ_GEM_NWCFG_FSREM | \
 					ZYNQ_GEM_NWCFG_MDCCLKDIV)
 
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 2db4ae2..c772bae 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -37,6 +37,7 @@
  */
 #define GQSPI_IXR_TXNFULL_MASK		0x00000004 /* QSPI TX FIFO Overflow */
 #define GQSPI_IXR_TXFULL_MASK		0x00000008 /* QSPI TX FIFO is full */
+#define GQSPI_IXR_TXFIFOEMPTY_MASK	0x00000100 /* QSPI TX FIFO is Empty */
 #define GQSPI_IXR_RXNEMTY_MASK		0x00000010 /* QSPI RX FIFO Not Empty */
 #define GQSPI_IXR_GFEMTY_MASK		0x00000080 /* QSPI Generic FIFO Empty */
 #define GQSPI_IXR_GFNFULL_MASK		0x00000200 /* QSPI GENFIFO not full */
@@ -279,9 +280,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 
 	debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 
-	/* Dummy generic FIFO entry */
-	zynqmp_qspi_fill_gen_fifo(priv, 0);
-
 	zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 }
 
@@ -470,6 +468,13 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 		}
 	}
 
+	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
+				GQSPI_TIMEOUT, 1);
+	if (ret) {
+		printf("%s: Timeout\n", __func__);
+		return ret;
+	}
+
 	priv->tx_buf += len;
 	return 0;
 }