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authorPeng Fan <peng.fan@nxp.com>2017-04-10 19:44:33 +0800
committerStefano Babic <sbabic@denx.de>2017-05-18 11:23:31 +0200
commit27255fe82163c2459431e1a270338df3bf76e1ec (patch)
tree596748456d060632b9424da5c64bed4d1e5185a2 /drivers
parentfa8967cfbaed5582ba987756fa9f0470a9affbf4 (diff)
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net: fec: do not access reserved register for i.MX6ULL
The MIB RAM and FIFO receive start register does not exist on i.MX6ULL. Accessing these register will cause enet not work well or cause system report fault. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/fec_mxc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 910879b..ac7afb5 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -563,7 +563,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register for i.MX6UL */
- if (!is_mx6ul()) {
+ if (!is_mx6ul() && !is_mx6ull()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);