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| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-04-27 21:29:50 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-06-24 20:22:17 +0200 |
| commit | e9c9e9cbef368d03ceda6d2c453f79e34b8cd203 (patch) | |
| tree | 052b4f7cee9f72b017e3e4db46c351ceaa65fa8a /drivers | |
| parent | b092f96290539d98ebd2e9c159de8035a8142842 (diff) | |
| download | u-boot-e9c9e9cbef368d03ceda6d2c453f79e34b8cd203.zip u-boot-e9c9e9cbef368d03ceda6d2c453f79e34b8cd203.tar.gz u-boot-e9c9e9cbef368d03ceda6d2c453f79e34b8cd203.tar.bz2 | |
gpio: renesas: Handle R8A779A0 V3U INEN register
The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN
register. Add new R8A779A0 compatible string with a new quirk and also
a handler for this quirk which toggles the INEN register in the right
place. INEN register handling is based on "gpio: renesas: Add R8A779A0
V3U support" by Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpio/gpio-rcar.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 5f1ec39..76f4702 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -28,13 +28,17 @@ #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */ #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */ #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ +#define GPIO_INEN 0x50 /* General Input Enable Register */ #define RCAR_MAX_GPIO_PER_BANK 32 +#define RCAR_GPIO_HAS_INEN BIT(0) + DECLARE_GLOBAL_DATA_PTR; struct rcar_gpio_priv { void __iomem *regs; + u32 quirks; int pfc_offset; }; @@ -81,6 +85,14 @@ static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset, /* Configure postive logic in POSNEG */ clrbits_le32(regs + GPIO_POSNEG, BIT(offset)); + /* Select "Input Enable/Disable" in INEN */ + if (priv->quirks & RCAR_GPIO_HAS_INEN) { + if (output) + clrbits_le32(regs + GPIO_INEN, BIT(offset)); + else + setbits_le32(regs + GPIO_INEN, BIT(offset)); + } + /* Select "General Input/Output Mode" in IOINTSEL */ clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset)); @@ -149,6 +161,7 @@ static int rcar_gpio_probe(struct udevice *dev) int ret; priv->regs = dev_read_addr_ptr(dev); + priv->quirks = dev_get_driver_data(dev); uc_priv->bank_name = dev->name; ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", @@ -179,6 +192,7 @@ static const struct udevice_id rcar_gpio_ids[] = { { .compatible = "renesas,gpio-r8a77970" }, { .compatible = "renesas,gpio-r8a77990" }, { .compatible = "renesas,gpio-r8a77995" }, + { .compatible = "renesas,gpio-r8a779a0", .data = RCAR_GPIO_HAS_INEN }, { .compatible = "renesas,rcar-gen2-gpio" }, { .compatible = "renesas,rcar-gen3-gpio" }, { /* sentinel */ } |