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| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:10 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 11:57:46 +0530 |
| commit | 1af0334ab4effb0bd17c3b0cf1fc1b65ff4f3ef8 (patch) | |
| tree | 20db2ee21f1220b18fbe7b76189cacacfd5ac663 /drivers | |
| parent | 38b0852b0eab1c5ce18ed8125572ffb0bb6973fd (diff) | |
| download | u-boot-1af0334ab4effb0bd17c3b0cf1fc1b65ff4f3ef8.zip u-boot-1af0334ab4effb0bd17c3b0cf1fc1b65ff4f3ef8.tar.gz u-boot-1af0334ab4effb0bd17c3b0cf1fc1b65ff4f3ef8.tar.bz2 | |
mtd: spi-nor-core: Fix address width on flash chips > 16MB
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.
Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 6af9c67..bfe7ea5 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2603,7 +2603,11 @@ int spi_nor_scan(struct spi_nor *nor) /* already configured from SFDP */ } else if (info->addr_width) { nor->addr_width = info->addr_width; - } else if (mtd->size > SZ_16M) { + } else { + nor->addr_width = 3; + } + + if (nor->addr_width == 3 && mtd->size > SZ_16M) { #ifndef CONFIG_SPI_FLASH_BAR /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; @@ -2617,8 +2621,6 @@ int spi_nor_scan(struct spi_nor *nor) if (ret < 0) return ret; #endif - } else { - nor->addr_width = 3; } if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { |