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author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2021-01-17 18:11:25 +0530 |
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committer | Andes <uboot@andestech.com> | 2021-01-18 11:06:32 +0800 |
commit | bc8d12bfd8750de265b742f2ab9cdde2726ea85f (patch) | |
tree | 2bbdf6fd3df17150cba305c93de6c906043d8dea /drivers/timer | |
parent | a80f85138c9457141c799c022b5c924252031512 (diff) | |
download | u-boot-bc8d12bfd8750de265b742f2ab9cdde2726ea85f.zip u-boot-bc8d12bfd8750de265b742f2ab9cdde2726ea85f.tar.gz u-boot-bc8d12bfd8750de265b742f2ab9cdde2726ea85f.tar.bz2 |
riscv: timer: Add support for an early timer
Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'drivers/timer')
-rw-r--r-- | drivers/timer/andes_plmt_timer.c | 21 | ||||
-rw-r--r-- | drivers/timer/riscv_timer.c | 21 | ||||
-rw-r--r-- | drivers/timer/sifive_clint_timer.c | 21 |
3 files changed, 60 insertions, 3 deletions
diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c index db2cf86..a3797b2 100644 --- a/drivers/timer/andes_plmt_timer.c +++ b/drivers/timer/andes_plmt_timer.c @@ -18,11 +18,30 @@ /* mtime register */ #define MTIME_REG(base) ((ulong)(base)) -static u64 andes_plmt_get_count(struct udevice *dev) +static u64 notrace andes_plmt_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); } +#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_MMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); +} +#endif + static const struct timer_ops andes_plmt_ops = { .get_count = andes_plmt_get_count, }; diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 21ae184..3627ed7 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -16,7 +16,7 @@ #include <timer.h> #include <asm/csr.h> -static u64 riscv_timer_get_count(struct udevice *dev) +static u64 notrace riscv_timer_get_count(struct udevice *dev) { __maybe_unused u32 hi, lo; @@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev) return ((u64)hi << 32) | lo; } +#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_SMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return riscv_timer_get_count(NULL); +} +#endif + static int riscv_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c index de23b85..de7b4b9 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/sifive_clint_timer.c @@ -15,11 +15,30 @@ /* mtime register */ #define MTIME_REG(base) ((ulong)(base) + 0xbff8) -static u64 sifive_clint_get_count(struct udevice *dev) +static u64 notrace sifive_clint_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); } +#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) +/** + * timer_early_get_rate() - Get the timer rate before driver model + */ +unsigned long notrace timer_early_get_rate(void) +{ + return RISCV_MMODE_TIMER_FREQ; +} + +/** + * timer_early_get_count() - Get the timer count before driver model + * + */ +u64 notrace timer_early_get_count(void) +{ + return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); +} +#endif + static const struct timer_ops sifive_clint_ops = { .get_count = sifive_clint_get_count, }; |