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authorPatrice Chotard <patrice.chotard@st.com>2017-07-18 09:29:09 +0200
committerTom Rini <trini@konsulko.com>2017-07-26 11:28:08 -0400
commit541cd6e54eb80159d9212e2dda8fdea8c246eea7 (patch)
tree0972ec323085b55f59aa601501c370cb39c7aaae /drivers/spi
parent27265cee76ee7ee779e2e26549bdedb9d38a56de (diff)
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spi: stm32_qspi: add clk_get_rate() support
Replace proprietary clock_get() by clk_get_rate() The stm32_qspi is now "generic" and can be used by other STM32 SoCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/stm32_qspi.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index f0434a4..ef2b64e 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -165,6 +165,7 @@ struct stm32_qspi_platdata {
struct stm32_qspi_priv {
struct stm32_qspi_regs *regs;
+ ulong clock_rate;
u32 max_hz;
u32 mode;
@@ -471,6 +472,13 @@ static int stm32_qspi_probe(struct udevice *bus)
dev_err(bus, "failed to enable clock\n");
return ret;
}
+
+ priv->clock_rate = clk_get_rate(&clk);
+ if (priv->clock_rate < 0) {
+ clk_disable(&clk);
+ return priv->clock_rate;
+ }
+
#endif
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
@@ -536,7 +544,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
if (speed > plat->max_hz)
speed = plat->max_hz;
- u32 qspi_clk = clock_get(CLOCK_AHB);
+ u32 qspi_clk = priv->clock_rate;
u32 prescaler = 255;
if (speed > 0) {
prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;