Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegra

- Add support for Jetson Nano, plus miscellaneous other fixes found
  during Nano bringup.
- Add Igor's update_uboot wrapper patches.

1 files changed, 23 insertions, 16 deletions

diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c
index d82ecaa..6e540e9 100644
--- a/drivers/spi/tegra210_qspi.c
+++ b/drivers/spi/tegra210_qspi.c
@@ -2,7 +2,8 @@
 /*
  * NVIDIA Tegra210 QSPI controller driver
  *
- * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
+ *
  */
 
 #include <common.h>
@@ -41,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_CMD1_BITLEN_SHIFT		0
 
 /* COMMAND2 */
-#define QSPI_CMD2_TX_CLK_TAP_DELAY	BIT(6)
-#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK	GENMASK(11,6)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY	BIT(0)
-#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK	GENMASK(5,0)
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT	10
+#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK	GENMASK(14,10)
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT	0
+#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK	GENMASK(7,0)
 
 /* TRANSFER STATUS */
 #define QSPI_XFER_STS_RDY		BIT(30)
@@ -96,10 +97,8 @@ struct tegra210_qspi_priv {
 static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
 {
 	struct tegra_spi_platdata *plat = bus->platdata;
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(bus);
 
-	plat->base = devfdt_get_addr(bus);
+	plat->base = dev_read_addr(bus);
 	plat->periph_id = clock_decode_periph_id(bus);
 
 	if (plat->periph_id == PERIPH_ID_NONE) {
@@ -109,10 +108,11 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
 	}
 
 	/* Use 500KHz as a suitable default */
-	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
-					500000);
-	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
-					"spi-deactivate-delay", 0);
+	plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
+					       500000);
+	plat->deactivate_delay_us = dev_read_u32_default(bus,
+							 "spi-deactivate-delay",
+							 0);
 	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
 	      __func__, plat->base, plat->periph_id, plat->frequency,
 	      plat->deactivate_delay_us);
@@ -126,25 +126,32 @@ static int tegra210_qspi_probe(struct udevice *bus)
 	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 
 	priv->regs = (struct qspi_regs *)plat->base;
+	struct qspi_regs *regs = priv->regs;
 
 	priv->last_transaction_us = timer_get_us();
 	priv->freq = plat->frequency;
 	priv->periph_id = plat->periph_id;
 
+	debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
+	      priv->periph_id);
 	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
 	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
 
+	/* Set tap delays here, clock change above resets QSPI controller */
+	u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
+		   (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
+	writel(reg, &regs->command2);
+	debug("%s: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
+
 	return 0;
 }
 
-static int tegra210_qspi_claim_bus(struct udevice *bus)
+static int tegra210_qspi_claim_bus(struct udevice *dev)
 {
+	struct udevice *bus = dev->parent;
 	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
 	struct qspi_regs *regs = priv->regs;
 
-	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
-
 	debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
 
 	/* Set master mode and sw controlled CS */