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author | Tom Rini <trini@konsulko.com> | 2024-05-24 09:10:54 -0600 |
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committer | Tom Rini <trini@konsulko.com> | 2024-05-24 09:10:54 -0600 |
commit | 5e625dca4ed7fcb8aedb4b6400aeaf8a19bed856 (patch) | |
tree | 66215f2b04e24864a1cbe5ab61235913b44640e3 /drivers/spi/spi-sifive.c | |
parent | 377e91c162ab09ec20f96f966f380cb55c590edd (diff) | |
parent | 75eab7c61c4ff729f11d5b99bef831b5cd9b7f0c (diff) | |
download | u-boot-5e625dca4ed7fcb8aedb4b6400aeaf8a19bed856.zip u-boot-5e625dca4ed7fcb8aedb4b6400aeaf8a19bed856.tar.gz u-boot-5e625dca4ed7fcb8aedb4b6400aeaf8a19bed856.tar.bz2 |
Merge patch series "spi-nor: Add parallel and stacked memories support"WIP/24May2024-next
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> says:
This series adds support for Xilinx qspi parallel and stacked memeories.
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.
In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical.
Spi-nor will pass on the appropriate flash select flag to low level driver,
and it will select pass all the data to that particular flash.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling the
address space each operation is performed at addr/2 flash offset, where addr
is the address specified by the user.
Similarly for read and erase operations it will read from both flashes, so
size and offset are divided by 2 and send to flash.
Diffstat (limited to 'drivers/spi/spi-sifive.c')
-rw-r--r-- | drivers/spi/spi-sifive.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c index 0c8666c..15407d4 100644 --- a/drivers/spi/spi-sifive.c +++ b/drivers/spi/spi-sifive.c @@ -108,13 +108,13 @@ static void sifive_spi_prep_device(struct sifive_spi *spi, { /* Update the chip select polarity */ if (slave_plat->mode & SPI_CS_HIGH) - spi->cs_inactive &= ~BIT(slave_plat->cs); + spi->cs_inactive &= ~BIT(slave_plat->cs[0]); else - spi->cs_inactive |= BIT(slave_plat->cs); + spi->cs_inactive |= BIT(slave_plat->cs[0]); writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); /* Select the correct device */ - writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID); + writel(slave_plat->cs[0], spi->regs + SIFIVE_SPI_REG_CSID); } static int sifive_spi_set_cs(struct sifive_spi *spi, |