Merge patch series "spi-nor: Add parallel and stacked memories support"WIP/24May2024-next

Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> says:

This series adds support for Xilinx qspi parallel and stacked memeories.

In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.

In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical.

Spi-nor will pass on the appropriate flash select flag to low level driver,
and it will select pass all the data to that particular flash.

Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling the
address space each operation is performed at addr/2 flash offset, where addr
is the address specified by the user.

Similarly for read and erase operations it will read from both flashes, so
size and offset are divided by 2 and send to flash.

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 35030ab..238e622 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -50,6 +50,13 @@ config SPI_DIRMAP
 	  improvements as it automates the whole process of sending SPI memory
 	  operations every time a new region is accessed.
 
+config SPI_ADVANCE
+	bool "Enable the advance feature"
+	default y
+	help
+	  Enable the SPI advance feature support. By default this is set to y.
+	  If you intend not to use the advance feature support you should say n here.
+
 if DM_SPI
 
 config ALTERA_SPI