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| author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2021-07-06 19:01:07 +0900 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-07-14 16:48:06 -0400 |
| commit | 34707b32edad37427327a5358433d0591a07dcc1 (patch) | |
| tree | 2f21e07b204f22fcf6f22ad1a9c99911812f15a3 /drivers/reset | |
| parent | a1b4810adbb61acb6d0efe0f7fa0588e476c8647 (diff) | |
| download | u-boot-34707b32edad37427327a5358433d0591a07dcc1.zip u-boot-34707b32edad37427327a5358433d0591a07dcc1.tar.gz u-boot-34707b32edad37427327a5358433d0591a07dcc1.tar.bz2 | |
reset: uniphier: Add PCIe reset entry
Add reset control for PCIe controller on each SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Diffstat (limited to 'drivers/reset')
| -rw-r--r-- | drivers/reset/reset-uniphier.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 2694d13..c5af995 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -50,6 +50,7 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ + UNIPHIER_RESETX(24, 0x2008, 2), /* PCIE */ UNIPHIER_RESET_END, }; @@ -79,6 +80,7 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */ + UNIPHIER_RESETX(24, 0x200c, 4), /* PCIE */ UNIPHIER_RESET_END, }; @@ -95,6 +97,7 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */ UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ + UNIPHIER_RESETX(24, 0x200c, 3), /* PCIE */ UNIPHIER_RESET_END, }; |