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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2018-07-09 15:17:20 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-07-20 15:55:05 -0400 |
| commit | d090cbab64c893e6c6122e468282750aeeeae840 (patch) | |
| tree | e7c763d35e75bcd7b5d82c6fce964924c8c51566 /drivers/reset | |
| parent | a674313c2cebfad8e168a2011027470a2e640983 (diff) | |
| download | u-boot-d090cbab64c893e6c6122e468282750aeeeae840.zip u-boot-d090cbab64c893e6c6122e468282750aeeeae840.tar.gz u-boot-d090cbab64c893e6c6122e468282750aeeeae840.tar.bz2 | |
misc: stm32: Add STM32MP1 support
Following next kernel rcc bindings, we must use a MFD
RCC driver which is able to bind both clock and reset
drivers.
We can reuse and adapt RCC MFD driver already available
for MCU SoCs (F4/F7/H7).
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'drivers/reset')
| -rw-r--r-- | drivers/reset/stm32-reset.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index c21ede2..16d3dba 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -8,16 +8,12 @@ #include <dm.h> #include <errno.h> #include <reset-uclass.h> +#include <stm32_rcc.h> #include <asm/io.h> /* reset clear offset for STM32MP RCC */ #define RCC_CL 0x4 -enum rcc_type { - RCC_STM32 = 0, - RCC_STM32MP, -}; - struct stm32_reset_priv { fdt_addr_t base; }; @@ -40,7 +36,7 @@ static int stm32_reset_assert(struct reset_ctl *reset_ctl) debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__, reset_ctl->id, bank, offset); - if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP) + if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) /* reset assert is done in rcc set register */ writel(BIT(offset), priv->base + bank); else @@ -57,7 +53,7 @@ static int stm32_reset_deassert(struct reset_ctl *reset_ctl) debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__, reset_ctl->id, bank, offset); - if (dev_get_driver_data(reset_ctl->dev) == RCC_STM32MP) + if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) /* reset deassert is done in rcc clr register */ writel(BIT(offset), priv->base + bank + RCC_CL); else @@ -88,15 +84,9 @@ static int stm32_reset_probe(struct udevice *dev) return 0; } -static const struct udevice_id stm32_reset_ids[] = { - { .compatible = "st,stm32mp1-rcc-rst", .data = RCC_STM32MP }, - { } -}; - U_BOOT_DRIVER(stm32_rcc_reset) = { .name = "stm32_rcc_reset", .id = UCLASS_RESET, - .of_match = stm32_reset_ids, .probe = stm32_reset_probe, .priv_auto_alloc_size = sizeof(struct stm32_reset_priv), .ops = &stm32_reset_ops, |