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authorAndy Chiu <andy.chiu@sifive.com>2022-11-01 11:57:59 +0800
committerMichal Simek <michal.simek@amd.com>2022-12-05 08:55:54 +0100
commite23544cffe7057d678846498ec0fbf21eff9bc95 (patch)
tree383268b0328e476e545ead028790887ac4d4a795 /drivers/reset
parentd2c5607edde2544e059fa871927877213f6bd532 (diff)
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net: xilinx_axi: add PCS/PMA PHY
If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to get and set the real status of the PHY facing the external world. Then we should phy_connect() to the external PHY instead of the PCS/PMA one. Thus, we add a pcs-handle DT entry, which have been merged in Linux, and leave the configuration of it to the driver itself. Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY pressents only when the phy-mode is configured as SGMII or 1000Base-X, so it is always 1 Gbps and full-duplex and we may skip passing link information out. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Link: https://lore.kernel.org/r/20221101035800.912644-2-andy.chiu@sifive.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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