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authorRabeeh Khoury <rabeeh@solid-run.com>2018-09-06 12:37:48 +0300
committerStefan Roese <sr@denx.de>2018-09-19 13:54:27 +0200
commitd13b740ca621531fc3d86b33feed24592be0bd18 (patch)
treeb417c74697c78a46bb00ec1fbe1ead57f26c61ca /drivers/phy
parent3c2a3897e85177655134110bc32e04be668b1de8 (diff)
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phy: marvell: add SATA comphy RX/TX polarity invert support
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The 'phy-invert' DT property defines the inverted signals. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/marvell/comphy_cp110.c19
-rw-r--r--drivers/phy/marvell/comphy_hpipe.h6
2 files changed, 23 insertions, 2 deletions
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 6a60da3..9998c07 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -641,7 +641,8 @@ static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
}
static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base, int cp_index)
+ void __iomem *comphy_base, int cp_index,
+ u32 invert)
{
u32 mask, data, i, ret = 1;
void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
@@ -927,6 +928,19 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
HPIPE_PWR_CTR_RST_DFE_MASK);
+
+ /* Set RX / TX swaps */
+ data = mask = 0;
+ if (invert & PHY_POLARITY_TXD_INVERT) {
+ data |= (1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET);
+ mask |= HPIPE_SYNC_PATTERN_TXD_SWAP_MASK;
+ }
+ if (invert & PHY_POLARITY_RXD_INVERT) {
+ data |= (1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET);
+ mask |= HPIPE_SYNC_PATTERN_RXD_SWAP_MASK;
+ }
+ reg_set(hpipe_addr + HPIPE_SYNC_PATTERN_REG, data, mask);
+
/* SW reset for interupt logic */
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
@@ -2006,7 +2020,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
case PHY_TYPE_SATA3:
ret = comphy_sata_power_up(
lane, hpipe_base_addr, comphy_base_addr,
- ptr_chip_cfg->cp_index);
+ ptr_chip_cfg->cp_index,
+ serdes_map[lane].invert);
break;
case PHY_TYPE_USB3_HOST0:
case PHY_TYPE_USB3_HOST1:
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
index d99da7b..a692035 100644
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ b/drivers/phy/marvell/comphy_hpipe.h
@@ -221,6 +221,12 @@
(0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
#define HPIPE_SYNC_PATTERN_REG 0x090
+#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
+#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \
+ (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
+#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11
+#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \
+ (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
#define HPIPE_INTERFACE_REG 0x94
#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10