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| author | Tom Rini <trini@konsulko.com> | 2021-09-27 09:45:36 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-09-27 09:45:36 -0400 |
| commit | e908d20fcbd847e17345591fc171b59d9a156516 (patch) | |
| tree | def104237fd9b8888a37a5c3378b4ef7e26b6d43 /drivers/phy/marvell | |
| parent | bb38d77ca779cc8bdad3d4ceb6cecc687f4987c2 (diff) | |
| parent | 0b9bcf665cd98fe9db0956c894006b250a7d465f (diff) | |
| download | u-boot-e908d20fcbd847e17345591fc171b59d9a156516.zip u-boot-e908d20fcbd847e17345591fc171b59d9a156516.tar.gz u-boot-e908d20fcbd847e17345591fc171b59d9a156516.tar.bz2 | |
Merge tag 'v2021.10-rc5' into next
Prepare v2021.10-rc5
Diffstat (limited to 'drivers/phy/marvell')
| -rw-r--r-- | drivers/phy/marvell/comphy_cp110.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 418318d..4fe2dfc 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -36,6 +36,10 @@ DECLARE_GLOBAL_DATA_PTR; (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) | \ ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds)) +/* Invert polarity are bits 1-0 of the mode */ +#define COMPHY_FW_SATA_FORMAT(mode, invert) \ + ((invert) | COMPHY_FW_MODE_FORMAT(mode)) + #define COMPHY_SATA_MODE 0x1 #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ #define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */ @@ -607,7 +611,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); + mode = COMPHY_FW_SATA_FORMAT(COMPHY_SATA_MODE, + serdes_map[lane].invert); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, |