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| author | Pali Rohár <pali@kernel.org> | 2021-09-24 16:11:55 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2021-10-08 08:33:52 +0200 |
| commit | 4adb16b29a31590f536b72e635370aff73732b4d (patch) | |
| tree | 47fbda04a09ae3caa2763f0e17cb543de8cb096b /drivers/phy/marvell | |
| parent | 646a1522478a30889354a378b2617b4c08d2c9fb (diff) | |
| download | u-boot-4adb16b29a31590f536b72e635370aff73732b4d.zip u-boot-4adb16b29a31590f536b72e635370aff73732b4d.tar.gz u-boot-4adb16b29a31590f536b72e635370aff73732b4d.tar.bz2 | |
phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode.
Same change was included in TF-A project:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/phy/marvell')
| -rw-r--r-- | drivers/phy/marvell/comphy_a3700.c | 2 | ||||
| -rw-r--r-- | drivers/phy/marvell/comphy_a3700.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 06822d1..504f4b2 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -200,7 +200,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) * 6. Enable the output of 100M/125M/500M clock */ reg_set16(phy_addr(PCIE, MISC_REG0), - 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); + 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF); /* * 7. Enable TX diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 8748c6c..23c8ffb 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -120,6 +120,7 @@ static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr) #define MISC_REG0 0x4f #define rb_clk100m_125m_en BIT(4) +#define rb_txdclk_2x_sel BIT(6) #define rb_clk500m_en BIT(7) #define rb_ref_clk_sel BIT(10) |