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authorIgal Liberman <igall@marvell.com>2018-05-14 11:20:54 +0300
committerStefan Roese <sr@denx.de>2021-04-29 07:45:24 +0200
commit341e548eb8f586c39c49efbd0b90eaf283fbee63 (patch)
treee6426dd0c088063f67402e48c2b6b6a8be23bf85 /drivers/phy/marvell
parenta007f236260d15fadea6643b2dd8ca5e6387e506 (diff)
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phy: marvell: add support for SFI1
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Diffstat (limited to 'drivers/phy/marvell')
-rw-r--r--drivers/phy/marvell/comphy_core.c2
-rw-r--r--drivers/phy/marvell/comphy_cp110.c14
2 files changed, 9 insertions, 7 deletions
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 9293607..2c9d7b2 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -41,7 +41,7 @@ static const char *get_type_string(u32 type)
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
"SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
"USB3", "USB3_HOST0", "USB3_HOST1",
- "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP",
+ "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
"IGNORE"
};
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 349109b..576538f 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
u32 lane)
{
int ret;
+ u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
debug_enter();
- if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
+ if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
pr_err("Comphy %d isn't configured to SFI\n", lane);
return 0;
}
@@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case COMPHY_TYPE_SFI:
- mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
- COMPHY_UNIT_ID0,
+ case COMPHY_TYPE_SFI0:
+ case COMPHY_TYPE_SFI1:
+ /* Calculate SFI id */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
+ mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
- ptr_chip_cfg->comphy_base_addr, lane,
- mode);
+ ptr_chip_cfg->comphy_base_addr, lane, mode);
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1: