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| author | Pali Rohár <pali@kernel.org> | 2023-04-20 21:44:23 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-05-01 18:59:33 -0400 |
| commit | c06597ff1151580d3ab7094c0175138b3896d16d (patch) | |
| tree | d0dbeb6b52725f11eac33e859f031d4a4b44f5be /drivers/pci | |
| parent | 159f104076d4a0693599900deb8173f2af5942a4 (diff) | |
| download | u-boot-c06597ff1151580d3ab7094c0175138b3896d16d.zip u-boot-c06597ff1151580d3ab7094c0175138b3896d16d.tar.gz u-boot-c06597ff1151580d3ab7094c0175138b3896d16d.tar.bz2 | |
pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0
At BDF address 00:00.0 is fictional device which PCI configuration header
is for configuring mpc85xx PCI controller itself. PCI config space of this
device has ATMU inbound registers on position of PCI BARs. Trying to do PCI
auto configuration of this device cause rewriting ATMU inbound registers.
To avoid it, do not allow overwriting registers at BARs positions. And
because this device does not have any PCI memory, return zeros when trying
to read PCI BARs config space registers. It signals to auto configuration
tool to not allocate any PCI memory for this device.
This information is taken from MPC8544E Reference Manual, sections
17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website:
https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pci_mpc85xx.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index 833de81..249cfe6 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -27,6 +27,13 @@ static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf, return 0; } + /* Skip mpc85xx PCI controller's ATMU inbound registers */ + if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5) { + *value = 0; + return 0; + } + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); @@ -56,6 +63,11 @@ static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf, if (offset > 0xff) return 0; + /* Skip mpc85xx PCI controller's ATMU inbound registers */ + if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 && + (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5) + return 0; + addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset); out_be32(priv->cfg_addr, addr); sync(); |