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authorAndrew Scull <ascull@google.com>2022-04-21 16:11:07 +0000
committerTom Rini <trini@konsulko.com>2022-05-03 15:50:45 -0400
commitec8eba8c2d4e10e77699c56918d2078210aa1339 (patch)
tree90f8fc61f747fc7b9b333ba32e86eac31dd600ff /drivers/pci
parent60f4142aa2e4156c6e4661184e6e9d9f1f8fb561 (diff)
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pci: Check region ranges are addressable
When parsing the `ranges` DT node, check that both extremes of the regions are addressable without overflow. This assumption can then be safely made when processing the regions. Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci-uclass.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 8bbeb62..0424cd3 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1013,7 +1013,22 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
- debug(" - beyond the 32-bit boundary, ignoring\n");
+ debug(" - pci_addr beyond the 32-bit boundary, ignoring\n");
+ continue;
+ }
+
+ if (!IS_ENABLED(CONFIG_PHYS_64BIT) && upper_32_bits(addr)) {
+ debug(" - addr beyond the 32-bit boundary, ignoring\n");
+ continue;
+ }
+
+ if (~((pci_addr_t)0) - pci_addr < size) {
+ debug(" - PCI range exceeds max address, ignoring\n");
+ continue;
+ }
+
+ if (~((phys_addr_t)0) - addr < size) {
+ debug(" - phys range exceeds max address, ignoring\n");
continue;
}