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| author | Suneel Garapati <sgarapati@marvell.com> | 2019-10-19 17:10:20 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-08-25 08:01:16 +0200 |
| commit | 4cf56ec07f673f99c87862dbb7e72bc077685474 (patch) | |
| tree | d40e8b752e61d666aab70f047b008e6ef30634c3 /drivers/pci/pci-uclass.c | |
| parent | bc30140d20d041a6ed5d52175e9953c36f8f5473 (diff) | |
| download | u-boot-4cf56ec07f673f99c87862dbb7e72bc077685474.zip u-boot-4cf56ec07f673f99c87862dbb7e72bc077685474.tar.gz u-boot-4cf56ec07f673f99c87862dbb7e72bc077685474.tar.bz2 | |
pci: pci-uclass: Add multi entry support for memory regions
Enable PCI memory regions in ranges property to be of multiple entry.
This helps to add support for SoC's like OcteonTX/TX2 where every
peripheral is on PCI bus.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/pci/pci-uclass.c')
| -rw-r--r-- | drivers/pci/pci-uclass.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index cf1bbcc..19ea3ae 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -936,10 +936,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, } pos = -1; - for (i = 0; i < hose->region_count; i++) { - if (hose->regions[i].flags == type) - pos = i; + if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) { + for (i = 0; i < hose->region_count; i++) { + if (hose->regions[i].flags == type) + pos = i; + } } + if (pos == -1) pos = hose->region_count++; debug(" - type=%d, pos=%d\n", type, pos); |