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| author | Tom Rini <trini@konsulko.com> | 2021-10-21 07:52:15 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-10-21 07:52:15 -0400 |
| commit | f200a4bcecf1be6d8b546f0eb6af6403c93d80dd (patch) | |
| tree | 5c5dfde8a916fd40ce0455ed1a7ead151719ecbb /drivers/pci/pci-aardvark.c | |
| parent | 79b8849d4c1e73df2a79a1d5a5f6166d0dd67a12 (diff) | |
| parent | bd4064ff8a82460d6a497faf66ac5830ffe452b1 (diff) | |
| download | u-boot-f200a4bcecf1be6d8b546f0eb6af6403c93d80dd.zip u-boot-f200a4bcecf1be6d8b546f0eb6af6403c93d80dd.tar.gz u-boot-f200a4bcecf1be6d8b546f0eb6af6403c93d80dd.tar.bz2 | |
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Turris MOX and Omnia changes, mostly moving to Kconfig (Marek)
- a37xx: pci: Misc smaller fixes (Pali)
- cmd: tlv_eeprom: Fix building with DEBUG enabled (Sven)
- termios_linux.h: Fix tcsendbreak() implementation (Pali)
- mvebu: Add missing "if SPL" (Tom)
Diffstat (limited to 'drivers/pci/pci-aardvark.c')
| -rw-r--r-- | drivers/pci/pci-aardvark.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 38eff49..9e623b6 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -445,7 +445,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, * for returning CRS, so that if U-Boot does support CRS in the future, * it will work for Aardvark. */ - allow_crs = pcie->cfgcrssve; + allow_crs = (offset == PCI_VENDOR_ID) && (size == PCI_SIZE_32) && pcie->cfgcrssve; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, @@ -581,6 +581,10 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, if (offset >= 0x10 && offset < 0x34) { data = pcie->cfgcache[(offset - 0x10) / 4]; data = pci_conv_size_to_32(data, value, offset, size); + /* This PCI bridge does not have configurable bars */ + if ((offset & ~3) == PCI_BASE_ADDRESS_0 || + (offset & ~3) == PCI_BASE_ADDRESS_1) + data = 0x0; pcie->cfgcache[(offset - 0x10) / 4] = data; } else if ((offset & ~3) == PCI_ROM_ADDRESS1) { data = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); |