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| author | Tom Rini <trini@konsulko.com> | 2021-03-31 09:47:30 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-03-31 09:47:30 -0400 |
| commit | db8b46120aed6554d1ff405260ea6d2cc2439fcc (patch) | |
| tree | 40326d1f241593e0593f7168eda5a09f19ce49ae /drivers/net/zynq_gem.c | |
| parent | 7d23eb9260d5ce0ccb219a17cfc90c29101d4fa5 (diff) | |
| parent | c5465684b9c74780fdeb30568c586d824eafd75c (diff) | |
| download | u-boot-db8b46120aed6554d1ff405260ea6d2cc2439fcc.zip u-boot-db8b46120aed6554d1ff405260ea6d2cc2439fcc.tar.gz u-boot-db8b46120aed6554d1ff405260ea6d2cc2439fcc.tar.bz2 | |
Merge tag 'xilinx-for-v2021.07' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into nextWIP/31Mar2021-next
Xilinx changes for v2021.07
net:
- Fix gem PCS support
spi:
- Small trivial fixes
zynq:
- Enable time/timer commands
- Update bitmain platform
- Several DT changes
zynqmp:
- Update clock driver
- mini config alignments
- Add/update psu_init for zcu208/zcu216/zc1275
- Several DT changes
- Enable efi debug command (also for Versal)
Diffstat (limited to 'drivers/net/zynq_gem.c')
| -rw-r--r-- | drivers/net/zynq_gem.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index baf06a2..ff59982 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -454,14 +454,6 @@ static int zynq_gem_init(struct udevice *dev) priv->int_pcs) { nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | ZYNQ_GEM_NWCFG_PCS_SEL; -#ifdef CONFIG_ARM64 - if (priv->phydev->phy_id != PHY_FIXED_ID) - writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, - ®s->pcscntrl); - else - writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL, - ®s->pcscntrl); -#endif } switch (priv->phydev->speed) { @@ -480,6 +472,23 @@ static int zynq_gem_init(struct udevice *dev) break; } +#ifdef CONFIG_ARM64 + if (priv->interface == PHY_INTERFACE_MODE_SGMII && + priv->int_pcs) { + /* + * Disable AN for fixed link configuration, enable otherwise. + * Must be written after PCS_SEL is set in nwconfig, + * otherwise writes will not take effect. + */ + if (priv->phydev->phy_id != PHY_FIXED_ID) + writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, + ®s->pcscntrl); + else + writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL, + ®s->pcscntrl); + } +#endif + ret = clk_set_rate(&priv->tx_clk, clk_rate); if (IS_ERR_VALUE(ret)) { dev_err(dev, "failed to set tx clock rate\n"); |