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| author | Weijie Gao <weijie.gao@mediatek.com> | 2022-09-09 19:59:26 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-09-23 15:09:15 -0400 |
| commit | e7ad046b64cf7d745e32c2e223d24c4f7f867521 (patch) | |
| tree | cb1bada2ba028944b137e7d0008baed22a2ced51 /drivers/net/mtk_eth.h | |
| parent | 7d928c3f2798fc2602e3c320b533fa721a92df38 (diff) | |
| download | u-boot-e7ad046b64cf7d745e32c2e223d24c4f7f867521.zip u-boot-e7ad046b64cf7d745e32c2e223d24c4f7f867521.tar.gz u-boot-e7ad046b64cf7d745e32c2e223d24c4f7f867521.tar.bz2 | |
net: mediatek: add support for PDMA v2
This patch adds support for PDMA v2 hardware. The PDMA v2 has extended the
DMA descriptor to 8-words, and some of its fields have changed comparing
to the v1 hardware.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/net/mtk_eth.h')
| -rw-r--r-- | drivers/net/mtk_eth.h | 53 |
1 files changed, 45 insertions, 8 deletions
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index 65bc9fc..236c498 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -15,6 +15,7 @@ enum mkt_eth_capabilities { MTK_TRGMII_BIT, MTK_TRGMII_MT7621_CLK_BIT, + MTK_NETSYS_V2_BIT, /* PATH BITS */ MTK_ETH_PATH_GMAC1_TRGMII_BIT, @@ -22,6 +23,7 @@ enum mkt_eth_capabilities { #define MTK_TRGMII BIT(MTK_TRGMII_BIT) #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) +#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) /* Supported path present on SoCs */ #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) @@ -35,7 +37,8 @@ enum mkt_eth_capabilities { #define MT7623_CAPS (MTK_GMAC1_TRGMII) /* Frame Engine Register Bases */ -#define PDMA_BASE 0x0800 +#define PDMA_V1_BASE 0x0800 +#define PDMA_V2_BASE 0x6000 #define GDMA1_BASE 0x0500 #define GDMA2_BASE 0x1500 #define GMAC_BASE 0x10000 @@ -74,6 +77,8 @@ enum mkt_eth_capabilities { #define SGMSYS_SPEED_2500 BIT(2) /* Frame Engine Registers */ +#define FE_GLO_MISC_REG 0x124 +#define PDMA_VER_V2 BIT(4) /* PDMA */ #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) @@ -444,6 +449,17 @@ struct mtk_rx_dma { unsigned int rxd4; } __packed __aligned(4); +struct mtk_rx_dma_v2 { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; + unsigned int rxd5; + unsigned int rxd6; + unsigned int rxd7; + unsigned int rxd8; +} __packed __aligned(4); + struct mtk_tx_dma { unsigned int txd1; unsigned int txd2; @@ -451,20 +467,41 @@ struct mtk_tx_dma { unsigned int txd4; } __packed __aligned(4); +struct mtk_tx_dma_v2 { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; + unsigned int txd5; + unsigned int txd6; + unsigned int txd7; + unsigned int txd8; +} __packed __aligned(4); + /* PDMA TXD fields */ #define PDMA_TXD2_DDONE BIT(31) #define PDMA_TXD2_LS0 BIT(30) -#define PDMA_TXD2_SDL0_M GENMASK(29, 16) -#define PDMA_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_TXD2_SDL0_M, (_v)) +#define PDMA_V1_TXD2_SDL0_M GENMASK(29, 16) +#define PDMA_V1_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V1_TXD2_SDL0_M, (_v)) +#define PDMA_V2_TXD2_SDL0_M GENMASK(23, 8) +#define PDMA_V2_TXD2_SDL0_SET(_v) FIELD_PREP(PDMA_V2_TXD2_SDL0_M, (_v)) + +#define PDMA_V1_TXD4_FPORT_M GENMASK(27, 25) +#define PDMA_V1_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V1_TXD4_FPORT_M, (_v)) +#define PDMA_V2_TXD4_FPORT_M GENMASK(27, 24) +#define PDMA_V2_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD4_FPORT_M, (_v)) -#define PDMA_TXD4_FPORT_M GENMASK(27, 25) -#define PDMA_TXD4_FPORT_SET(_v) FIELD_PREP(PDMA_TXD4_FPORT_M, (_v)) +#define PDMA_V2_TXD5_FPORT_M GENMASK(19, 16) +#define PDMA_V2_TXD5_FPORT_SET(_v) FIELD_PREP(PDMA_V2_TXD5_FPORT_M, (_v)) /* PDMA RXD fields */ #define PDMA_RXD2_DDONE BIT(31) #define PDMA_RXD2_LS0 BIT(30) -#define PDMA_RXD2_PLEN0_M GENMASK(29, 16) -#define PDMA_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_RXD2_PLEN0_M, (_v)) -#define PDMA_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_RXD2_PLEN0_M, (_v)) +#define PDMA_V1_RXD2_PLEN0_M GENMASK(29, 16) +#define PDMA_V1_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V1_RXD2_PLEN0_M, (_v)) +#define PDMA_V1_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V1_RXD2_PLEN0_M, (_v)) +#define PDMA_V2_RXD2_PLEN0_M GENMASK(23, 8) +#define PDMA_V2_RXD2_PLEN0_GET(_v) FIELD_GET(PDMA_V2_RXD2_PLEN0_M, (_v)) +#define PDMA_V2_RXD2_PLEN0_SET(_v) FIELD_PREP(PDMA_V2_RXD2_PLEN0_M, (_v)) #endif /* _MTK_ETH_H_ */ |