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author | Tom Rini <trini@konsulko.com> | 2017-11-29 08:26:07 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2017-11-29 08:26:07 -0500 |
commit | b06c46de632c55f4c39d404c6f0f65e414b31050 (patch) | |
tree | dea1702529c8d33c5e70eb5eb6ecf7d08eed23b9 /drivers/mtd | |
parent | fcc8250c2f7c982f3593a8eecf737f8e2c95f222 (diff) | |
parent | a04a5daae25a74ad2ac90b66667dac126242baa0 (diff) | |
download | u-boot-b06c46de632c55f4c39d404c6f0f65e414b31050.zip u-boot-b06c46de632c55f4c39d404c6f0f65e414b31050.tar.gz u-boot-b06c46de632c55f4c39d404c6f0f65e414b31050.tar.bz2 |
Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.1
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/nand/Kconfig | 7 | ||||
-rw-r--r-- | drivers/mtd/nand/zynq_nand.c | 23 |
2 files changed, 28 insertions, 2 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index cbdbd2f..47ec435 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -154,6 +154,13 @@ config NAND_ZYNQ This enables Nand driver support for Nand flash controller found on Zynq SoC. +config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS + bool "Enable use of 1st stage bootloader timing for NAND" + depends on NAND_ZYNQ + help + This flag prevent U-boot reconfigure NAND flash controller and reuse + the NAND timing from 1st stage bootloader. + comment "Generic NAND options" # Enhance depends when converting drivers to Kconfig which use this config diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c index 948f059..076b878 100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@ -35,6 +35,8 @@ (0x1 << 4) | /* Clear interrupt */ \ (0x1 << 6)) /* Disable ECC interrupt */ +#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS + /* Assuming 50MHz clock (20ns cycle time) and 3V operation */ #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \ (0x2 << 17) | /* t_ar from nand_cycles */ \ @@ -43,6 +45,7 @@ (0x2 << 8) | /* t_rea from nand_cycles */ \ (0x5 << 4) | /* t_wc from nand_cycles */ \ (0x5 << 0)) /* t_rc from nand_cycles */ +#endif #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \ @@ -81,6 +84,13 @@ #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */ #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */ +#ifndef NAND_CMD_LOCK_TIGHT +#define NAND_CMD_LOCK_TIGHT 0x2c +#endif + +#ifndef NAND_CMD_LOCK_STATUS +#define NAND_CMD_LOCK_STATUS 0x7a +#endif /* SMC register set */ struct zynq_nand_smc_regs { @@ -141,6 +151,11 @@ static const struct zynq_nand_command_format zynq_nand_commands[] = { {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0}, {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0}, {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0}, + {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0}, + {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0}, + {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0}, + {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0}, + {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0}, {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0}, /* Add all the flash commands supported by the flash device */ }; @@ -245,8 +260,10 @@ static int zynq_nand_init_nand_flash(int option) /* disable interrupts */ writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr); +#ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS /* Initialize the NAND interface by setting cycles and operation mode */ writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr); +#endif if (option & NAND_BUSWIDTH_16) writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor); else @@ -989,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd) return 0; } -static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +int zynq_nand_init(struct nand_chip *nand_chip, int devnum) { struct zynq_nand_info *xnand; struct mtd_info *mtd; @@ -1175,12 +1192,14 @@ fail: return err; } +#ifdef CONFIG_SYS_NAND_SELF_INIT static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -void board_nand_init(void) +void __weak board_nand_init(void) { struct nand_chip *nand = &nand_chip[0]; if (zynq_nand_init(nand, 0)) puts("ZYNQ NAND init failed\n"); } +#endif |