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| author | Tom Rini <trini@konsulko.com> | 2022-01-09 07:56:31 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-01-09 07:56:31 -0500 |
| commit | 0dadad6d7c5769d6258baeaf1b8db843b0dfa01f (patch) | |
| tree | 53825eeb3b8474d6dce270eb7d84c3afe875ba1b /drivers/mtd | |
| parent | 2a4b89a8ff69c3bbc7a2798e8b195d5489be95c1 (diff) | |
| parent | 4c8d067bc520fc2ce6dcd7c5833b090f22c67185 (diff) | |
| download | u-boot-0dadad6d7c5769d6258baeaf1b8db843b0dfa01f.zip u-boot-0dadad6d7c5769d6258baeaf1b8db843b0dfa01f.tar.gz u-boot-0dadad6d7c5769d6258baeaf1b8db843b0dfa01f.tar.bz2 | |
Merge tag 'u-boot-amlogic-20220107' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into nextWIP/09Jan2022-next
- disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 5 |
2 files changed, 5 insertions, 6 deletions
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 0969c03..f350c7e 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -129,12 +129,6 @@ config SPI_FLASH_UNLOCK_ALL For legacy reasons, this option default to y. But if you intend to actually use the software protection bits you should say n here. -config SF_DUAL_FLASH - bool "SPI DUAL flash memory support" - help - Enable this option to support two flash memories connected to a single - controller. Currently Xilinx Zynq qspi supports this. - config SPI_FLASH_ATMEL bool "Atmel SPI flash support" help diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3ae7bb1..b551ebd 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -355,6 +355,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |