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authorMarkus Hoffrogge <mhoffrogge@gmail.com>2022-06-30 01:26:39 +0200
committerAndre Przywara <andre.przywara@arm.com>2022-07-18 11:34:26 +0100
commit5fd30ed78539e11c2c155001a88f483441a96ebd (patch)
tree1a55bb9dc07e67c57ae9c39246f26459516d60af /drivers/mtd
parent4a9f37df1d5e103ad2560db1446511c4f59d289c (diff)
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sunxi-nand: fix the PIO instead of DMA implementation
The sunxi nand SPL loader was broken at least for SUN4I, SUN5I and SUN7I SOCs since the implementation change from DMA to PIO usage - commit 6ddbb1e. Root cause for this issue is the NFC control flag NFC_CTL_RAM_METHOD being set by method nand_apply_config. This flag controls the bus being used for the NFCs internal RAM access. It must be set for the DMA use case only. See A33_Nand_Flash_Controller_Specification.pdf page 12. This fix is tested by myself on a Cubietruck A20 board. Others should test it on new generation SOCs as well. Signed-off-by: Markus Hoffrogge <mhoffrogge@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/raw/sunxi_nand_spl.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c
index a29a76c..6de0b0a 100644
--- a/drivers/mtd/nand/raw/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c
@@ -208,7 +208,7 @@ static void nand_apply_config(const struct nfc_config *conf)
val = readl(SUNXI_NFC_BASE + NFC_CTL);
val &= ~NFC_CTL_PAGE_SIZE_MASK;
- writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
+ writel(val | NFC_CTL_PAGE_SIZE(conf->page_size),
SUNXI_NFC_BASE + NFC_CTL);
writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);