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| author | Christophe Kerello <christophe.kerello@st.com> | 2019-04-05 11:41:50 +0200 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2019-04-12 16:09:13 +0200 |
| commit | 7bb75023a720432a32840c6df543aae92653b23d (patch) | |
| tree | e3fd663b8b22bd5ea6f9d3c31b51da47be869e65 /drivers/mtd/nand/raw/Kconfig | |
| parent | 6899385f41ee43170c82dddc814323d2e2901a22 (diff) | |
| download | u-boot-7bb75023a720432a32840c6df543aae92653b23d.zip u-boot-7bb75023a720432a32840c6df543aae92653b23d.tar.gz u-boot-7bb75023a720432a32840c6df543aae92653b23d.tar.bz2 | |
mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch adds the polling mode, a basic mode that do not need
any DMA channels.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Diffstat (limited to 'drivers/mtd/nand/raw/Kconfig')
| -rw-r--r-- | drivers/mtd/nand/raw/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 7f76e5e..dc087ab 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -256,6 +256,17 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS This flag prevent U-boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. +config NAND_STM32_FMC2 + bool "Support for NAND controller on STM32MP SoCs" + depends on ARCH_STM32MP + select SYS_NAND_SELF_INIT + imply CMD_NAND + help + Enables support for NAND Flash chips on SoCs containing the FMC2 + NAND controller. This controller is found on STM32MP SoCs. + The controller supports a maximum 8k page size and supports + a maximum 8-bit correction error per sector of 512 bytes. + comment "Generic NAND options" config SYS_NAND_BLOCK_SIZE |