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| author | Andre Przywara <andre.przywara@arm.com> | 2021-04-29 09:31:58 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2021-07-10 01:22:09 +0100 |
| commit | ca496baf9b84913c941f8247fc416b39f158d142 (patch) | |
| tree | eef36469422068cd55ab7863155047d6e89170b0 /drivers/mmc | |
| parent | f4826fb137a4514163aeea31ca8d17e70fcb37e4 (diff) | |
| download | u-boot-ca496baf9b84913c941f8247fc416b39f158d142.zip u-boot-ca496baf9b84913c941f8247fc416b39f158d142.tar.gz u-boot-ca496baf9b84913c941f8247fc416b39f158d142.tar.bz2 | |
mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT
When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about
pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which
are always below 1GB on all Allwinner SoCs, so there is no problem with
anything having more than 32 bits.
Add the proper casts to make it compile cleanly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/sunxi_mmc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 87b79fc..869af99 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -631,14 +631,14 @@ static int sunxi_mmc_probe(struct udevice *dev) cfg->f_min = 400000; cfg->f_max = 52000000; - priv->reg = (void *)dev_read_addr(dev); + priv->reg = dev_read_addr_ptr(dev); /* We don't have a sunxi clock driver so find the clock address here */ ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, 1, &args); if (ret) return ret; - ccu_reg = (u32 *)ofnode_get_addr(args.node); + ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node); priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4; |