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| author | Michal Simek <michal.simek@xilinx.com> | 2021-07-09 05:53:44 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-07-26 09:18:45 +0200 |
| commit | 419b4a86f784c819c520d88658799cb71063f87e (patch) | |
| tree | 7c3a2da051e656530821c0b174a501cf531f3be3 /drivers/mmc/zynq_sdhci.c | |
| parent | c0436fcf1a5af15e5035cea71e39d3610fdecc35 (diff) | |
| download | u-boot-419b4a86f784c819c520d88658799cb71063f87e.zip u-boot-419b4a86f784c819c520d88658799cb71063f87e.tar.gz u-boot-419b4a86f784c819c520d88658799cb71063f87e.tar.bz2 | |
mmc: zynq_sdhci: Make variables/structure static
All these variables/structure are local and should be static.
Issues are reported by sparse:
drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not declared. Should it be static?
drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared. Should it be static?
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'drivers/mmc/zynq_sdhci.c')
| -rw-r--r-- | drivers/mmc/zynq_sdhci.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 47862c0..ba87ee8 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -50,12 +50,16 @@ struct arasan_sdhci_priv { #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) /* Default settings for ZynqMP Clock Phases */ -const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}; -const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}; +static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, + 0, 183, 54, 0, 0}; +static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72, + 135, 48, 72, 135, 0}; /* Default settings for Versal Clock Phases */ -const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}; -const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}; +static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, + 0, 0, 162, 90, 0, 0}; +static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, + 90, 36, 60, 90, 0}; static const u8 mode2timing[] = { [MMC_LEGACY] = MMC_TIMING_LEGACY, @@ -541,8 +545,8 @@ static void arasan_sdhci_set_control_reg(struct sdhci_host *host) sdhci_set_uhs_timing(host); } -const struct sdhci_ops arasan_ops = { - .platform_execute_tuning = &arasan_sdhci_execute_tuning, +static const struct sdhci_ops arasan_ops = { + .platform_execute_tuning = &arasan_sdhci_execute_tuning, .set_delay = &arasan_sdhci_set_tapdelay, .set_control_reg = &arasan_sdhci_set_control_reg, }; |