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| author | Haibo Chen <haibo.chen@nxp.com> | 2021-03-03 17:05:46 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-04-08 23:44:40 +0200 |
| commit | 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2 (patch) | |
| tree | 588f99ca8cff444255aad60793e42b082e8c5e27 /drivers/mmc/uniphier-sd.c | |
| parent | dec7755c442ff84358704a5566e4ae908afecf13 (diff) | |
| download | u-boot-63756575b42b8b4fb3f59cbbf0cedf03331bc2d2.zip u-boot-63756575b42b8b4fb3f59cbbf0cedf03331bc2d2.tar.gz u-boot-63756575b42b8b4fb3f59cbbf0cedf03331bc2d2.tar.bz2 | |
mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these
are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the
card clock output.
After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"),
we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because
the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during
voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON,
after CMD11, hardware will gate off the card clock automatically, so card do
not detect the clock off/on behavior, so will draw the data0 line low until
next command.
Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support")
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Diffstat (limited to 'drivers/mmc/uniphier-sd.c')
0 files changed, 0 insertions, 0 deletions