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authorVasily Khoruzhick <anarsoul@gmail.com>2018-11-05 20:24:28 -0800
committerJagan Teki <jagan@amarulasolutions.com>2018-11-13 22:07:39 +0530
commit20940ef2a397446a209350900d3bd618c3fd5b94 (patch)
tree0b584459737f9b65585876e3ea3ca696933b66ac /drivers/mmc/sunxi_mmc.c
parent4f9d34e633c498b9f706a78f465d337c041f4a65 (diff)
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mmc: sunxi: add support for automatic delay calibration
A64 and H6 support automatic delay calibration and Linux driver uses it instead of hardcoded delays. Add support for it to u-boot driver. Fixes eMMC instability on Pinebook Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Tested-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cc: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/mmc/sunxi_mmc.c')
-rw-r--r--drivers/mmc/sunxi_mmc.c21
1 files changed, 20 insertions, 1 deletions
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 39f15eb..147eb9b 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
{
unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
bool new_mode = false;
+ bool calibrate = false;
u32 val = 0;
if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
new_mode = true;
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
+ calibrate = true;
+#endif
+
/*
* The MMC clock has an extra /2 post-divider when operating in the new
* mode.
@@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
val = CCM_MMC_CTRL_MODE_SEL_NEW;
setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
#endif
- } else {
+ } else if (!calibrate) {
+ /*
+ * Use hardcoded delay values if controller doesn't support
+ * calibration
+ */
val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
}
@@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
writel(rval, &priv->reg->clkcr);
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
+ /* A64 supports calibration of delays on MMC controller and we
+ * have to set delay of zero before starting calibration.
+ * Allwinner BSP driver sets a delay only in the case of
+ * using HS400 which is not supported by mainline U-Boot or
+ * Linux at the moment
+ */
+ writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
+#endif
+
/* Re-enable Clock */
rval |= SUNXI_MMC_CLK_ENABLE;
writel(rval, &priv->reg->clkcr);