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| author | Tom Rini <trini@konsulko.com> | 2021-01-15 07:23:50 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-01-15 07:23:50 -0500 |
| commit | b47e293b71dd87294abf62b59cae81222f6056df (patch) | |
| tree | 32ce823dce6c14d17f820e3c66549ca09fd051bc /drivers/mmc/socfpga_dw_mmc.c | |
| parent | 35772ff4f63a302e0b873096372c70292fb0af79 (diff) | |
| parent | 40551cf99c237f93d9e0e07b6dd8f31b3868a0f0 (diff) | |
| download | u-boot-WIP/15Jan2021.zip u-boot-WIP/15Jan2021.tar.gz u-boot-WIP/15Jan2021.tar.bz2 | |
Merge branch '2021.04-rc' of https://github.com/lftan/u-bootWIP/15Jan2021
- Add ATF flow for SoC64 devices
- Update socfpgaimage to support print header and update padding flow
Diffstat (limited to 'drivers/mmc/socfpga_dw_mmc.c')
| -rw-r--r-- | drivers/mmc/socfpga_dw_mmc.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index dc008c5..aa0d3a2 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,6 +6,7 @@ #include <common.h> #include <log.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/secure_reg_helper.h> #include <asm/arch/system_manager.h> #include <clk.h> #include <dm.h> @@ -13,6 +14,7 @@ #include <errno.h> #include <fdtdec.h> #include <dm/device_compat.h> +#include <linux/intel-smc.h> #include <linux/libfdt.h> #include <linux/err.h> #include <malloc.h> @@ -46,7 +48,7 @@ static void socfpga_dwmci_reset(struct udevice *dev) reset_deassert_bulk(&reset_bulk); } -static void socfpga_dwmci_clksel(struct dwmci_host *host) +static int socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | @@ -58,14 +60,28 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + int ret; + + ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC, + sdmmc_mask); + if (ret) { + printf("DWMMC: Failed to set clksel via SMC call"); + return ret; + } +#else writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); +#endif /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + + return 0; } static int socfpga_dwmmc_get_clk_rate(struct udevice *dev) |